JPH04243086A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPH04243086A JPH04243086A JP3004125A JP412591A JPH04243086A JP H04243086 A JPH04243086 A JP H04243086A JP 3004125 A JP3004125 A JP 3004125A JP 412591 A JP412591 A JP 412591A JP H04243086 A JPH04243086 A JP H04243086A
- Authority
- JP
- Japan
- Prior art keywords
- request
- memory
- writing
- memory section
- test mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims abstract description 3
- 230000004044 response Effects 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は記憶装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device.
【0002】0002
【従来の技術】従来、この種の記憶装置は、DRAM内
の情報を一定値に書き込む場合、すなわちメモリクリア
等のライト動作をDRAMのアドレス分、例えばIMD
RAMで220(=1048576回)行う必要がある
。
又記憶装置においてBANK構成や増設単位の実施の仕
方によりこれが何倍にもなっていた。2. Description of the Related Art Conventionally, in this type of storage device, when writing information in a DRAM to a constant value, in other words, a write operation such as memory clearing is performed by writing an address of a DRAM, for example, an IMD.
It is necessary to perform this process 220 times (=1048576 times) in RAM. In addition, in the storage device, this amount has been multiplied many times depending on the BANK configuration and the implementation of expansion units.
【0003】0003
【発明が解決しようとする課題】上述した従来の記憶装
置はDRAM内の情報を一定値に書き込む場合、すなわ
ちメモリクリア等ライト動作をDRAMのアドレス分例
えばIMDRAMですと220回(=1048576回
)行う必要がある。又BANK構成や増設単位の実施の
仕方によりこれが何倍にもなってしまうので、書き込む
だけで膨大な時間がかかってしまうという欠点がある。[Problems to be Solved by the Invention] In the conventional storage device described above, when writing information in DRAM to a constant value, that is, write operations such as memory clearing are performed 220 times (=1048576 times) for the address of DRAM, for example, in the case of IMDRAM. There is a need. Moreover, this amount can be multiplied many times depending on the BANK configuration and the implementation of expansion units, so there is a drawback that it takes an enormous amount of time just to write.
【0004】0004
【課題を解決するための手段】本発明の記憶装置は、読
み出し要求及び書き込み要求によりメモリ部からデータ
を読み出したり、書き込んだりできるメモリ制御部と、
複数ビット並列テスト機能を持ったメモリ部と、前記メ
モリ部をテストモードにセットするための要求を外部か
ら行なえる要求手段を有している。[Means for Solving the Problems] A storage device of the present invention includes a memory control unit that can read and write data from a memory unit in response to a read request and a write request;
It has a memory section having a multi-bit parallel test function, and a request means that can issue a request to set the memory section to a test mode from the outside.
【0005】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【0006】図1は本発明の一実施例を示すブロック図
である。メモリ制御部10はテストモード要求信号40
0を受け取るとメモリ部20にテストモード・セットの
ための制御信号500を出力する。その後メモリ部20
に対する動作は複数ビット並列テスト状態になり、ライ
ト要求時にメモリ制御部10はアドレス信号100とデ
ータ信号200と制御信号300を受け取り、メモリ部
20にライト系の制御信号500を出力する。FIG. 1 is a block diagram showing one embodiment of the present invention. The memory control unit 10 receives the test mode request signal 40
When receiving 0, it outputs a control signal 500 for setting the test mode to the memory section 20. After that, the memory section 20
The operation is in a multi-bit parallel test state, and at the time of a write request, the memory control unit 10 receives the address signal 100, data signal 200, and control signal 300, and outputs a write-related control signal 500 to the memory unit 20.
【0007】これは、テストモードがセットされていな
い状態のノーマル動作と同じである。これにより、複数
ビットを並列に書き込むことができる。テストモードを
リセットする要求を受け取ると、メモリ部20にテスト
・モードリセットのための制御信号500を出力し終了
する。[0007] This is the same as normal operation when the test mode is not set. This allows multiple bits to be written in parallel. When a request to reset the test mode is received, a control signal 500 for resetting the test mode is output to the memory section 20, and the process ends.
【0008】[0008]
【発明の効果】本発明の記憶装置は、DRAM内の情報
を一定値に書き込むため(すなわち、メモリクリア等)
のライト動作数を減少させ、時間を削減できる効果があ
る。[Effects of the Invention] The storage device of the present invention is useful for writing information in DRAM to a constant value (i.e., memory clearing, etc.)
This has the effect of reducing the number of write operations and time.
【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
10 メモリ制御部 20 メモリ部 100 アドレス信号 200 データ信号 300 制御信号 400 テストモード要求信号 500 制御信号 10 Memory control section 20 Memory section 100 Address signal 200 Data signal 300 Control signal 400 Test mode request signal 500 Control signal
Claims (1)
メモリ部からデータを読み出したり、書き込んだりでき
るメモリ制御部と、複数ビット並列テスト機能を持った
メモリ部と、前記メモリ部をテストモードにセットする
ための要求を外部から行なえる要求手段とを含むことを
特徴とする記憶装置。1. A memory control unit that can read and write data from a memory unit in response to a read request and a write request, a memory unit that has a multi-bit parallel test function, and a memory unit that can set the memory unit to a test mode. 1. A storage device comprising a request means that can make a request from outside.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3004125A JPH04243086A (en) | 1991-01-18 | 1991-01-18 | Storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3004125A JPH04243086A (en) | 1991-01-18 | 1991-01-18 | Storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04243086A true JPH04243086A (en) | 1992-08-31 |
Family
ID=11576068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3004125A Pending JPH04243086A (en) | 1991-01-18 | 1991-01-18 | Storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04243086A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008100495A1 (en) * | 2007-02-13 | 2008-08-21 | Gainspan Corporation | Method and system of fast clearing of memory using a built-in self-test circuit |
-
1991
- 1991-01-18 JP JP3004125A patent/JPH04243086A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008100495A1 (en) * | 2007-02-13 | 2008-08-21 | Gainspan Corporation | Method and system of fast clearing of memory using a built-in self-test circuit |
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