JP2003132696A - Semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test device provided with a defect analyzing device in which fail information inputted at high speed by performing a test can be stored in a low speed memory corresponding to an address space of a DUT without applying interleave constitution. SOLUTION: In a semiconductor test device provided with a defect analyzing memory section which tests a memory part of the DUT and by which a device to be tested incorporates at least memory elements, the defect analyzing memory section is provided with a cache memory means in which a fail signal of the prescribed plurality of bits generated based on performing a DUT test and corresponding prescribed address information are once stored in a buffer, converted to continuous data string, and supplied to a fail storage memory means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus equipped with a failure analysis apparatus capable of storing fail information at individual addresses in an address space of a memory or a device under test (DUT) including the memory. In particular, the present invention relates to a semiconductor test device including a failure analysis device configured to store a fail information that is input at a high speed by applying a low speed memory.

[0002]

2. Description of the Related Art FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus. The main components are the timing generator TG, the pattern generator PG, the waveform shaper FC, the pin electronics PE, the logical comparator DC, and the fail memory FM.
With. The pin electronics PE includes a driver DR, a comparator CP, and others. Here, since the semiconductor test apparatus is publicly known and well known in the art, other signals and constituent elements, and detailed description thereof will be omitted except for the main part of the present application.

Fail memory FM (Fail Analysis Memo)
ry: a failure analysis memory) is an address failure memory AFM (Address Failure Memory) which is a main element of the failure analysis device of the present application, which analyzes an address where a failure has occurred.
And other elements. The AFM provided in the FM is
At least a high-speed memory unit having the same memory configuration as the data width and address space of the DUT and having a speed equal to or higher than the access speed of the DUT is provided in correspondence with the number of DUTs to be simultaneously measured. The high-speed memory means has two phases.
A high-speed operation is realized based on a memory group having an interleaved structure such as a four-phase form or a four-phase form. Further, there are various speed memories as the DUT, for example, a medium capacity memory that operates at a cycle of 500 MHz or more, and a low speed but large capacity memory, and the failure analysis device must be configured to cover these. There is. Since the technique of forming the interleave is publicly known, its explanation is omitted. An example of the storage capacity of this AFM is, for example, 25 DUTs.
In the case of the same measurement number of 64 at 6 Mbits, a large-capacity storage device for the number of interleaved phases × 256 Mbits × 64 is provided. Further, the number of fail signals FAIL received from the logical comparator DC is, for example, one DUT is an I / O pin having an 18-bit width, and it is assumed that 64 simultaneous measurement is performed.
There are a large number of 8 × 64 = 1152 bits. On the other hand, A
The address signal applied to the FM is generated from the pattern generator PG, for example, an address signal PGA having a 32-bit width.
The DR can be received corresponding to the interleaved configuration, and the fail information can be accumulated and stored in the address position corresponding to the address where the DUT fails.

By the way, a basic functional test of the write / read operation of the memory of the DUT is performed in the pre-test of the previous stage. Those that fail at this stage will be excluded from further testing. Therefore, the AFM performed after the above-mentioned preliminary test
In this test in which fail-fail information is stored, it can be said that fail does not occur in a large proportion in the entire address space of the DUT. FIG. 2 shows fail signals FB1 to FB for each bit.
An example of the occurrence situation of n is shown. The fail occurrence status is a discrete occurrence status for each bit or an intermittent occurrence status. In the device pass / fail judgment, if a failure occurs even once, it is a defective product, but in the case of a test mode in which ranks are classified according to characteristics such as access time, a large number of failures occur.

Next, the internal principle configuration of the AFM according to the present invention shown in FIG. 3 will be described. The essential components include an address selection unit 11, a memory control unit 21, and a memory unit 81. Here, it is assumed that the pattern generator PG generates an address signal PGADR having a width of 32 bits and all the bits are used in the memory section 81. The first clock CLK1 is a clock synchronized with the fail generation period, and has a high speed of, for example, 500 MHz. The second clock CLK2 is a low-speed clock for storing in the interleave memory of the memory unit, and is, for example, 250 MHz / 125 MHz corresponding to the number of interleave phases. The address selection unit 11 receives the 32-bit width address signal PGADR generated from the pattern generator PG, and branches it into two or four branches corresponding to the interleaved memory unit 81 to obtain a phase corresponding to the interleaved structure. Thus, the fail address signal 11si which is phase-shifted and distributed by the first clock CLK1 and synchronized with the low-speed second clock CLK2 is supplied to the memory unit 81.

The memory control unit 21 receives, for example, a fail signal (fail data) FAIL having a width of 1152 bits from the logical comparator DC, generates a write signal WT1i when even one bit of fail information exists, and the write signal WT1i. And the fail data FAIL1 having a width of 1152 bits are phase-shifted and distributed by the first clock CLK1 so as to have a phase corresponding to the interleaved configuration, and are supplied to each interleave memory in synchronization with the second clock CLK2 having a low speed. . When the interleaved memory has an individual memory structure that can be subdivided into 1-bit units, the individual fail data FAIL1 is applied as the write signal WT1i. Further, in the case of the memory configuration in which the interleave memory is subdivided into units of a predetermined plurality of bits, the individual write signal WT1i is generated only when fail information is present in the predetermined plurality of bits in the write signal WT1i. And supplies it to the interleave memory.

The memory section 81 is provided with an interleave memory having the number of phases corresponding to the interleave structure and a cumulative addition means. The interleave memory for one phase has, for example, 25
When the write signal WT1i distributed as described above is provided with a 6M × 1152 bit capacity, the cumulative addition means controls the read-modify-write operation to perform cumulative addition for each stored bit. Store.

According to the above-mentioned conventional structure, it is necessary to increase the number of interleaved phases L from 2 phases to 4 phases and from 4 phases to 8 phases as the DUT becomes a faster device. The advantage of the interleaved structure is that it can be distributed and stored in the same address in a low-speed memory. However, on the contrary, there is a big problem that the memory capacity increases in proportion to the number of interleaved phases. For example, in the case of two phases, two systems of 256 M words are required, and in the case of four phases, four systems of 256 M words are required. Further, there is a problem that the number of boards is increased due to an increase in peripheral circuit elements accompanying the interleaved structure.

[0009]

As described above, in the prior art, memories of various speeds, such as 1 GH, are used.
For an AFM that is required to store fail information for a wide range of devices, including medium-capacity memory that operates in cycles of z or more, and low-speed but large-capacity memory, it is necessary to increase the number of interleaved phases. Become. However, in the interleaved failure analysis device, there is a problem that the circuit scale increases by a factor of 2/4 in proportion to the number of phases, which causes a problem that the number of boards to be mounted increases and the cost increases. is there. On the other hand, the fail occurrence status can be said to be an intermittent occurrence status as shown in FIG. Therefore, a problem to be solved by the present invention is to provide a failure analysis device capable of storing fail information that is input at high speed by a test execution in a low-speed memory corresponding to an address space of a DUT without applying an interleaved structure. It is to provide a semiconductor test apparatus including.

[0010]

A first solution will be described.
In order to solve the above-mentioned problems, the device under test is a device including at least a memory element (for example, SRAM, D
RAM, non-volatile memory, system LSI, ASIC)
In the semiconductor test apparatus including the failure analysis memory unit 100 for testing the memory part of the DUT, the DUT
A high-speed predetermined multiple-bit fail signal (fail data FAIL) which is intermittently generated based on the test execution of
The predetermined address information obtained by accessing the memory element corresponding to the fail signal is temporarily buffer-stored, and converted into a continuous data string of low-speed cycle in the fail-storage memory means of low-speed cycle operation, and then the fail-storage memory means. The semiconductor test apparatus is characterized in that the failure analysis memory unit is provided with a cache memory means for supplying to the defect analysis memory section. According to the above invention, it is possible to realize a semiconductor test apparatus including a failure analysis apparatus that can practically store fail information that is input at high speed by performing a test in a low-speed memory corresponding to the DUT address space. Therefore, the DUT
There is an advantage that a low-speed operation memory of a fraction of the memory access speed at the time of test can be applied, and the same memory capacity as the address space of the DUT is sufficient.

Next, the second solving means will be shown. In order to solve the above-mentioned problems, the device under test is a device containing at least a memory element, and in a semiconductor test apparatus including a failure analysis memory unit 100 that tests a memory part of the DUT, an intermittent test is performed based on the DUT test execution. The cache memory means for temporarily buffering a predetermined high-speed predetermined multiple-bit fail signal (fail data FAIL) and predetermined address information for accessing the memory element corresponding to the fail signal is provided. Is stored in the low-speed cycle operation, and the fail signal (fail information) buffer-stored by the cache memory means and the address information are continuously output in the low-speed cycle operation. The fail storage memory means receives the address information. A failure analysis memory unit 100 is provided, which OR-adds corresponding bits of the previously stored fail data read by accessing the corresponding address and the fail information, and stores and saves the OR-added cumulative fail data at the address. There is a semiconductor test apparatus characterized by the above.

Next, a third solving means will be shown. The fourth here
The figure shows the solution according to the invention. In order to solve the above-mentioned problems, the device under test is a device containing at least a memory element, and in the semiconductor test apparatus including the failure analysis memory unit 100 for testing the memory part of the DUT, the failure analysis memory unit 100 fails. A fail signal indicating a defective cell obtained by accessing a predetermined memory address obtained by performing a predetermined test of the DUT is provided with a fail storage memory unit having a predetermined capacity required for analysis (for example, the memory unit 80) and the corresponding fail signal. When receiving the address information, the fail signal is cumulatively stored in an address position corresponding to the address information of the fail storing memory means, and a predetermined capacity (for example, about 100 words) provided in the preceding stage of the fail storing memory means. Cache memory means (for example, cache memory unit 3
0), the cache memory means receives a fail signal (fail data FAIL) which is intermittently generated based on the test execution of the DUT, and the fail signal and address information corresponding to the fail signal are once provided in the cache memory. A buffer for storing in the buffer means, and the fail information and the address information stored in the buffer are successively and sequentially output to the fail storing memory means of a low-speed cycle operation provided in a subsequent stage, and accumulated in a predetermined manner. There is a test device.

Next, a fourth solving means will be shown. As one mode of the above-mentioned cache memory means, a high-speed cache memory means having a capacity capable of buffer storage is applied even if a fail signal is generated a predetermined number of times consecutively at a maximum test speed for the DUT. There is a semiconductor test equipment.

Next, a fifth solving means will be shown. 6th here
The figure shows the solution according to the invention. As one mode of the above-mentioned cache memory means, there is an address direction division cache memory configuration which is provided with the address division means 50 for dividing the address space in a predetermined manner and correspondingly divides the cache memory means in the address direction. There is the above-mentioned semiconductor testing device characterized by the above.

Next, the sixth solving means will be described. As one mode of the above-mentioned cache memory means, a data direction division cache memory which receives a fail signal FAIL of a predetermined plurality of bits corresponding to a DUT, and divides the cache memory means with respect to the data of the plurality of bits in the data direction There is the above-mentioned semiconductor test device characterized by having a configuration.

Next, a seventh solving means will be shown. As one mode of the above-mentioned cache memory means, there is a bidirectional divided cache memory configuration divided so that both methods of the data direction divided cache memory configuration and the address direction divided cache memory configuration can be applied. There is the semiconductor testing device described above.

Next, an eighth solution means will be shown. 7th here
The figure shows the solution according to the invention. The pre-cumulative addition means 70 for accumulating and adding fail data is provided in the preceding stage of the cache memory means, and the pre-cumulative addition means 70 receives the next failed fail address signal 10s received as an input and the previously received failed fail. Both are compared with the address signal 10s, and if they match, the fail data FAIL received last time and this time
There is the above-mentioned semiconductor test apparatus characterized in that the number of times of buffer storage in the cache memory means is reduced by logically ORing each bit of 1 and holding the update.

Next, a ninth solving means will be shown. 8th here
The figure shows the solution according to the invention. The address masking means 210 is provided in the preceding stage of the above-mentioned pre-cumulative adding means 70, and the address signal (post-masking address data 210s) obtained as a result of receiving the fail address signal 10s and arbitrarily masking individual address bits to "0" is described above. There is the above-mentioned semiconductor test device characterized by supplying to the pre-cumulative addition means 70.

Next, a tenth solving means will be described. As one mode of the fail storage memory means (for example, the memory unit 80), at least a memory capacity of an address space corresponding to the address space of the memory portion of the DUT is provided, and fail bits of the same address are individually cumulatively OR-added There is the above-mentioned semiconductor test device including an adding means.

If desired, the means of the present invention may be combined with the element means of the above-mentioned solving means as appropriate to form other practical constituent means. Further, although the reference numerals given to the above respective elements correspond to the reference numerals shown in the embodiments of the present invention and the like, the present invention is not limited to this, and constituent means to which other practical equivalents are applied. Also good.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment to which the present invention is applied will be described below with reference to the drawings. Further, the scope of the claims is not limited by the description content of the following embodiments, and the elements and connection relationships described in the embodiments are not necessarily essential to the solving means.
Furthermore, the forms / forms of the elements and connection relationships described in the embodiments are examples, and the form / form contents are not limited to these.

The present invention will be described below with reference to FIGS. 4, 5 and 6. The elements corresponding to those of the conventional configuration are designated by the same reference numerals, and the description of the overlapping portions will be omitted.

FIG. 4 is a block diagram of the internal principle of the AFM of the present invention. The essential components are the address selection unit 10, the memory control unit 20, and the cache memory unit 30.
And a memory unit 80. The address selection unit 10
Upon receiving the 32-bit width address signal PGADR generated from the pattern generator PG, the buffered fail address signal 10s is supplied to the cache memory unit 30.

The memory control unit 20 receives a fail signal FAIL having a width of 1152 bits from the logical comparator DC, generates a write signal WT1 when fail information is present in any bit, and outputs the write signal and 1152.
The bit-width fail signal FAIL and the first clock CL
The data is supplied to the cache memory unit 30 in synchronization with K1.

The cache memory unit 30 is a temporary buffer memory, which is a high-speed buffer memory having a small width of 1152 + 32 bits, for example, a few K words. This capacity is several kW / 25 with respect to the memory capacity of the memory unit 80.
Since it is 6 MW, it has an extremely small capacity of about 1/100000. As shown in the internal configuration diagram of FIG.
The memory is an O (Fast In Fast Out) type memory, and a write operation and a read operation can be simultaneously executed in parallel. In FIG. 5, at one of the write ports, when the write input end WEN is asserted in synchronization with the high-speed first clock CLK1, the input data at the data input ends WAD and WDD are input to FI.
Store in FO form. At the other read port, when the empty signal ENPTY indicating the empty data state is negated, the read enable input terminal REN is always asserted, so the stored data is stored at the data output terminal RQ,
It is output from RDQ in synchronization with the low-speed second clock CLK2. When the empty signal ENPTY is asserted, since the stored data is empty, the standby state of no operation is entered. Since the operating principle of the FIFO type cache memory is well known, its internal structure is omitted.

Returning to FIG. 4, the cache memory unit 30
At one write port, the memory control unit 20
In response to the write signal WT1 from, the fail data FAIL1 is buffer-stored in synchronization with the first clock CLK1 only when this signal is asserted. On the other read port, unless the buffer contents are empty, the slow second
1 at the timing synchronized with the transfer cycle of the clock CLK2
The fail data FAIL2 having a width of 152 bits and the fail address data 30s having a width of 32 bits are continuously output and supplied to the memory unit 80. In addition, the write signal WT
2 is an empty signal E as shown in the internal configuration example of FIG.
The NPTY is inverted and supplied to the memory unit 80. As shown in FIG. 2, the cache memory unit 30 buffer-stores a high-speed fail signal FAIL that occurs intermittently at a cycle of, for example, 500 MHz, and the stored data continues at a low speed of a quarter of a 125 MHz, for example. Can be output after being converted into a typical data string. However, as shown in the burst-like occurrence portion in FIG. 2A, if fail signals are continuously generated under the condition that the capacity of the cache memory unit 30 is far exceeded, buffer storage cannot be performed. However, depending on the operation mode of memory failure analysis, it is often practically applicable.

The memory section 80 includes a single fail storage memory and cumulative addition means. A single memory
It is sufficient if it has the same capacity as the address space of the DUT. For example, it has a capacity of 256 M × 1152 bits. And
The fail address data 30s is transferred to the address input terminal a
And the fail data FAIL2 is received at the data input terminal d, and when the write signal WT2 is asserted, the cumulative addition means is controlled to perform, for example, a read-modify-write operation, and accumulated for each stored bit. Add and store.

According to the configuration example of FIG. 4 described above, as shown in FIG. 2, a high-speed fail signal FAIL which is intermittently generated, for example, at a cycle of 500 MHz can be buffer-stored. The stored data is converted into a continuous data string at a low speed of ¼ 125 MHz cycle and is output. As a result, the data is practically stored in the memory unit 80 of one system without the conventional interleave structure. It is possible to obtain a great advantage that it is possible to practically perform a failure analysis of the DUT. Therefore, the capacity of the fail storage memory according to the present invention can be reduced to 1/2 when the number of interleaved phases is 2 in the conventional case, and to 1/4 when the number of interleaved phases is 4 phases.
The number of boards on which these circuits are mounted can be reduced in proportion to this. Therefore, it is possible to obtain the advantage of realizing a significantly cheaper failure analysis device. Furthermore, there is an advantage that it can be easily mounted in a high-speed, large-capacity DUT that will appear in the future in the accommodation space of the current failure analysis device.

Next, FIG. 6 shows another configuration example of the internal principle configuration diagram of the AFM of the present invention. The main components are the address selection unit 10, the memory control unit 20, the address division unit 50, the first cache memory unit 30a,
The second cache memory unit 30b and the first memory unit 80a
And a second memory unit 80b. This is a configuration in which the cache memory unit and the memory unit are divided into two systems. This is an example of an address-direction divided cache memory configuration in which the cache memory is divided in the address direction.

The address dividing means 50 divides the address for storing the fail into two. For example, the entire address space is hexadecimal from "0000,0000" to "FFFF, FFFF"
Assuming that, by applying the most significant bit MSB, one lower address space "0000,0000" to "7FFF, FFF
F ”and the other upper address space from“ 8000,0000 ”to“ FF
FF, FFFF "is divided into two. As another example of division, there is an example of division into even-numbered address space and odd-numbered address space by applying the least significant bit LSB. From the fail address signal 10s of 32 bits, the divided fail address signal 50s of the remaining 31-bit width obtained by deleting any one bit of the 32-bit fail address signal 10s is received by the first cache memory unit 30a and the second cache memory. For example, the most significant bit MSB is deleted or the least significant bit LSB is deleted to divide the address space into the address space described above Further, the write signal WT1 from the memory control unit 20 is received, When the most significant bit MSB or the least significant bit LSB to be deleted is "0", the first write signal WT 1a is asserted and supplied to the first cache memory unit 30a, and conversely, when "1", the second cache memory unit 30a is supplied.
The write signal WT1b is asserted and supplied to the second cache memory unit 30b.

One of the first cache memory units 30a is
When the most significant bit MSB is applied, the divided fail address signal 50s in the lower address space "0000,0000" to "7FFF, FFFF" is buffer-stored. Since this is the same operation as the cache memory unit 30 shown in FIG. 4 except that the address width is 31 bits, the description thereof will be omitted. According to this, only half of the lower address space can be cached, so that there is an advantage that the probability of occurrence of overflow of the cache can be almost halved compared to the configuration example of FIG.

The other second cache memory unit 30b is also similar to the first cache memory unit 30a and buffer-stores the divided fail address signal 50s in the upper address space "8000,0000" to "FFFF, FFFF". To do. According to this, only half of the upper address space can be cached, so that there is an advantage that the probability of occurrence of overflow of the cache can be almost halved. As a method of dividing the address into two, a dividing method of dividing the address space into an even number side address space and an odd number side address space is effective in many cases.

Since the first memory section 80a only needs to store the lower address space "0000,0000" to "7FFF, FFFF", D
The advantage is that the memory capacity is half the total address space of the UT. Similarly, since the second memory unit 80b only needs to store the upper address space "8000,0000" to "FFFF, FFFF", the memory capacity is half that of the entire address space of the DUT.

According to the above-described configuration example of the invention shown in FIG. 6, the address space is divided into two, and each divided memory is provided with a cache memory, whereby the first memory section 80a divided into two systems.
And the total memory capacity of the second memory unit 80b is DU
The advantage that the same memory capacity as the entire address space of T is sufficient is obtained, and the defect analysis of the DUT can be practically performed. Moreover, a low-speed and inexpensive memory can be applied. As a result, with respect to the total memory capacity of the memory unit 81 having the conventional interleave structure shown in FIG.
Alternatively, a great advantage that it can be greatly reduced to 1/4 is obtained. Therefore, there is an advantage that it can be constructed at a significantly low cost.

The technical idea of the present invention is not limited to the concrete configuration examples and connection mode examples of the above-described embodiment. Furthermore, based on the technical idea of the present invention, the above-described embodiments may be appropriately modified and widely applied. For example, although the configuration example of FIG. 6 described above is a specific example in which the address space is divided into two caches and the fail signal is stored in the memory unit, the number of divisions corresponding to the number of interleaved phases may be used. For example, if the number of interleaved phases in the conventional configuration is four, the address space is divided into four areas, each of which is provided with a cache memory, and the memory capacity in the subsequent stage is 1 /
With the configuration including the four memory units, the probability of occurrence of overflow can be further reduced. Moreover, since the memory capacity to be mounted is 1/4 of that of the conventional configuration, a significant reduction effect can be obtained. In addition, in consideration of the mounting space and cost, the structure is further divided, for example, 1/8, 1
It may be divided into / 16 and the like.

In the configuration of FIG. 6 described above, the configuration example of the address-direction divided cache memory for dividing the cache memory in the address direction (address space) is shown.
A data direction division cache memory configuration for performing division in the data direction may be adopted. That is, the 1152-bit fail data is divided into 18-bit units, 36-bit units, and other desired units. A cache memory is separately provided for each of the above-mentioned divided parts. As a result, for example, if there is a failure even in 1 bit out of 1152 bits, it is buffer-stored together with the 32-bit address signal only in the corresponding cache memory. As a result, the utilization efficiency of the cache memory is improved, and the cache memory as a whole has the great advantage that the probability of occurrence of overflow can be further reduced. Further, a data direction and address direction divided cache memory structure may be used in which both methods of the data direction divided cache memory structure and the address direction divided cache memory structure are used together.

Further, the address dividing means 5 having the above-mentioned configuration shown in FIG.
In 0, a specific example in which the deletion bits (divided address bits) applied to division in the fail address signal 10s are fixed to the highest or lowest order has been described, but any address bit may be applied if desired. A division address bit selection designation means may be additionally provided. In this case, for example, there is an advantage that the test program applied to the failure analysis of the marching pattern, the galloping pattern, the checker pattern, or the like can be executed under the condition setting that does not cause the overflow properly. It is also possible to switch the selection designation in sequence and to make a test that does not overflow.

Further, when there are consecutive burst-like failures, the storage in the cache memory 40 overflows. Therefore, overflow detection means 36 (see FIG. 5) indicating that the overflow has occurred may be additionally provided. In this case, the memory unit 8
Since it is possible to know whether or not all the fail information is stored in 0, there is an advantage that it can be effectively used as an aid to failure analysis.

When the cache memory 40 overflows, an overflow address storing cache memory for storing the address signal PGADR at that time may be additionally provided. The capacity may be a small capacity of, for example, a 32-bit width and several K words, and can be realized with a small capacity of 1/30 or less with respect to the cache memory 40 having the 1152-bit width. In this case, it is possible to detect and specify addresses in which failures continuously occur, and therefore, it is possible to obtain an advantage that it can be effectively used as an aid to defect analysis.

In the failure analysis, which characteristics on which part on the memory chip are shown are analyzed and used as feedback information for the yield process, uniform characteristics, improved characteristics, improved quality, etc. to the pre-process of wafer manufacturing. There is a case. In this case, there is a test mode in which a huge number of failures occur in most of the entire address space. In this case, it is often sufficient if the sections of neighboring plural memory cells can be evaluated as a group unit. For example, in some cases, it may be sufficient to perform fail evaluation in group units of small blocks obtained by dividing the entire IC chip surface into 1024. Here, there is a correlation between the memory cells in group units and the addresses to be accessed. Therefore, FIG.
As shown in another configuration example of the internal principle configuration diagram of AFM,
It is a configuration example in which the pre-cumulative addition means 70 is added to the stage before storing in the cache memory 40 in the configuration of FIG. 4.
An address comparison unit 72 and a cumulative addition unit 74 are provided inside the pre-cumulative addition unit 70. The pre-cumulative addition means 70 may be applied to the configuration of FIG. The address comparing means 72 holds the latest fail address signal 10sb having a 32-bit width that has failed, and compares both the latest fail address signal 10sb and the fail address signal 10s that failed this time. Then, first, when it is detected that both address values are the same, the cache memory 40 does not store the same and the fail data FAIL1 of 1152 bit width accumulated so far by the cumulative addition unit 74 and the fail received this time. Each bit of the data FAIL1 is individually logically ORed and updated and held in the cumulative addition unit 74. Secondly, when the two address values are different, the fail data FAIL2 held by the cumulative addition unit 74 and the latest fail address signal 10sb
And are supplied to the cache memory 40 to be stored therein. After that, the received fail address signal 10s and the fail data FAIL1 are loaded into the cumulative addition unit 74. Therefore, according to the configuration example of FIG. 7, since the failures that occur successively at the same address can be combined into one, the possibility of overflow at the time of storage in the cache memory 40 can be reduced.

As shown in another configuration example of the internal principle configuration diagram of the AFM of FIG. 8, in the configuration example of FIG. 7, an address mask means 210 is added to the input side of the address comparison means 72. is there. The address mask means 21
0 may be applied to the configuration of FIG. The address masking unit 210 receives the fail address signal 10s having a 32-bit width from the address selecting unit 10 and arbitrarily masks individual bits to "0", so that the masked address data 210 is obtained.
It outputs s. For example, in the address signal PGADR having a 32-bit width, the lower 2 bits are masked.
As a result, the masked address data 2 in which a plurality of designated addresses for accessing the DUT are converted into the same address value
10 s is supplied to the pre-cumulative addition means 70. Therefore,
According to the configuration example of FIG. 8, since the failure occurrences that are continuously input under the condition that the masked post-masking address data 210s are the same can be combined into one,
The possibility of overflow at the time of storage in the cache memory 40 can be further reduced, and the failure analysis of the DUT can be practically performed.

[0042]

The present invention has the following effects based on the above description. As described above, according to the present invention, a cache memory is inserted in a predetermined stage in front of the fail storage memory so that a fail signal FAIL which is intermittently generated at a high speed cycle is continuously transmitted at a low speed. It can be converted into a data string and stored in a fail storage memory that operates at a low speed cycle, which enables practical failure analysis of the DUT. Moreover, the capacity of the fail storage memory can be reduced to 1/2 when the number of conventional interleaved phases is 2 and can be reduced to 1/4 when the number of interleaved phases is 4 as described above. Also, since it can be reduced in proportion to this, there is a great advantage that a significantly cheaper failure analysis apparatus can be realized. Further, as shown in the exemplary configuration of the invention of FIG. 6, the possibility that the cache memory overflows can be practically eliminated by dividing the address space into a plurality of N and providing a cache memory in each of the divided areas.
It is possible to analyze the DUT failure more practically. Also in this case, the total memory capacity divided into N systems is the same memory capacity as the entire address space of the DUT. Therefore, the memory capacity is 1/2, 1/4, etc. as compared with the conventional one. A big advantage that can be reduced to. Therefore, the technical effect of the present invention is great, and the economic effect in industry is also great.

[Brief description of drawings]

FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus.

FIG. 2 is a diagram showing an example of a fail occurrence situation for each bit of a fail signal FAIL.

FIG. 3 is a block diagram showing the internal principle of a conventional AFM according to the present application.

FIG. 4 is a diagram showing the internal principle of an AFM according to the present invention.

FIG. 5 is an internal configuration diagram of a cache memory unit according to the present invention.

FIG. 6 is another configuration example of the internal principle configuration diagram of the AFM of the present invention.

FIG. 7 is another configuration example of the internal principle configuration diagram of the AFM of the present invention.

FIG. 8 is another configuration example of the internal principle configuration diagram of the AFM of the present invention.

[Explanation of symbols]

10, 11 Address selection unit 20, 21 Memory control unit 30 Cache memory unit 30a First cache memory unit 30b Second cache memory unit 40 Cache memory 50 Address division unit 70 Pre-cumulative addition unit 72 Address comparison unit 74 Cumulative addition unit 80, 81 memory unit 80a first memory unit 80b second memory unit 100 failure analysis memory unit 210 address mask means AFM address failure memory (Address Failure)
Memory) DC logic comparator DUT Device under test FM Failure analysis memory (fail memory) PG pattern generator

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 11/413 G11C 11/34 341D 5M024 16/02 17/00 601Z 11/34 371A

Claims (9)

[Claims] 1. A device under test (DUT) is a device containing at least a memory element, and occurs in a semiconductor test apparatus including a failure analysis memory unit for testing a memory portion of the DUT, based on a test execution of the DUT. A cache memory in which a predetermined plurality of bits of fail signal and corresponding predetermined address information are temporarily buffer-stored, converted into a continuous data string in the fail storage memory means of low-speed cycle operation, and supplied to the fail storage memory means. A semiconductor test apparatus, comprising means for the failure analysis memory unit. 2. A device under test (DUT) is a device containing at least a memory element, and in a semiconductor test apparatus including a failure analysis memory unit for testing a memory portion of the DUT, the device under test is intermittently tested based on the execution of the DUT test. A high-speed predetermined multi-bit fail signal generated in the above and a predetermined address information for accessing the memory element corresponding to the fail signal, and a cache memory means for temporarily storing the buffer, and a low-speed cycle operation for predetermined storage of the fail information. Fail storage memory means, and the fail signal (fail information) buffered by the cache memory means and the address information are continuously output in a low-speed cycle operation, and the fail storage memory means receives the fail signal and outputs the address. The previous storage file that was read by accessing the address corresponding to the information A semiconductor test apparatus comprising: a failure analysis memory unit that OR-adds corresponding bits of fail data and the fail information, and stores and saves the OR-added cumulative fail data at the address. 3. A device under test (DUT) is a device containing at least a memory element, and in a semiconductor test apparatus having a failure analysis memory unit for testing a memory portion of the DUT, the failure analysis memory unit is used for fail analysis. A fail storage memory means of a required capacity is provided, and when a fail signal indicating a defective cell obtained by accessing a prescribed memory address obtained by performing a predetermined test of the DUT and address information corresponding to the fail signal are received. , The fail signal is cumulatively stored at an address position corresponding to the address information of the fail storing memory means, and the fail storing memory means is provided with a cache memory means of a predetermined capacity before the fail storing memory means, and intermittently based on a test of the DUT. The fail signal that is generated dynamically, the cache memory means receives the fail signal. Buffer signal and the address information corresponding thereto are temporarily buffer-stored in the cache memory means, and the buffer-stored fail information and address information are successively and sequentially provided to the fail-storage memory means in a low-speed cycle operation provided in the subsequent stage. A semiconductor test apparatus, which outputs and stores in a predetermined manner. 4. The cache memory means is a high-speed cache memory means having a capacity capable of being stored in a buffer even if a fail signal is generated a predetermined number of times consecutively at a maximum test speed for the DUT. The semiconductor test apparatus according to claim 1. 5. The semiconductor test apparatus according to claim 1, wherein the cache memory means has an address direction divided cache memory structure which is provided by dividing the cache memory means in the address direction. 6. The semiconductor test apparatus according to claim 1, wherein the cache memory means has a data direction division cache memory configuration in which the cache memory means is divided in the data direction. 7. The cache memory means is a bidirectionally divided cache memory structure divided so that both methods of the data direction divided cache memory structure and the address direction divided cache memory structure can be applied. 4. The semiconductor test device according to claim 1, wherein: 8. A pre-cumulative addition means for accumulating and adding fail data is provided in a preceding stage of the cache memory means, wherein the pre-cumulative addition means receives a fail next fail address signal as an input and a previously received fail. The fail address signal is compared with each other, and when the two match, the respective bits of the fail data received last time and this time are individually logically ORed to be updated and held, so that the number of times of buffer storage in the cache memory means can be determined. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is reduced. 9. An address masking means is provided in the preceding stage of the pre-cumulative adding means, and an address signal as a result of receiving a fail address signal and arbitrarily masking individual address bits to "0" is supplied to the pre-cumulative adding means. The semiconductor test apparatus according to claim 8, wherein the semiconductor test apparatus is supplied.