JPH11250698A - Parallel test circuit device of semiconductor storage and testing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the inspection time of a semiconductor integrated device incorporating a memory with a multiple-bit width by dividing a memory where data are read and written in m-bit width into a plurality of divided memory blocks where data are read and written with q-bit width on inspection and comparing each data with m/q-bit width for discrimination. SOLUTION: A memory that is read and written by write data 141-144 and read data 151-154 with 16-bit width is divided into divided memory blocks 101-104 that is read and written by the write data 144 and the read data 154. The divided memory blocks 101-104 write 4-bit wide test write data 191-194 and outputs 16-bit wide test read memory data 61-64, four bits at a time. A parallel read output test circuit 1 is controlled by a test address enable signal 90, a test data selection signal 100, and a test address 80, thus outputting a 4-bit wide test read data 71-74.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel test circuit device for a semiconductor memory device and a test circuit device using the same.

[0002]

2. Description of the Related Art In recent years, in electronic equipment using a semiconductor integrated circuit device, a semiconductor manufacturing process has been miniaturized, and a plurality of systems are mixedly mounted on one chip to develop a large-scale and highly integrated semiconductor integrated circuit device. Is becoming possible. Among them, a large-capacity memory is built in, a multi-bit read / write data width is increased, and a data transfer rate within the semiconductor integrated circuit device is improved, thereby realizing a multi-bit width memory realizing high functionality. A built-in semiconductor integrated device has been developed.

However, when inspecting a semiconductor integrated device incorporating such a multi-bit width memory, it is necessary to adopt a configuration in which the memory can be directly accessed from the outside. However, all of the multi-bit width data bits are allocated to the terminals. In some cases, the number of terminals of the semiconductor integrated circuit device is limited and difficult. Further, since a large number of data comparators of the memory inspection device are required, the memory inspection device becomes expensive and the inspection cost increases.

On the other hand, as another means, a method of incorporating a BIST circuit in a semiconductor integrated circuit device and inspecting a built-in memory without directly accessing from outside can be considered. In this case, data is read / written with a multi-bit width. Therefore, a multi-bit data line and a multi-bit read circuit inside the BIST circuit are required, so that the area of the inspection circuit in the semiconductor integrated circuit device increases.

Therefore, when testing the memory portion of a semiconductor integrated circuit device having a built-in multi-bit width memory, a multi-bit width data is divided into small bit widths by adding a test address at the time of the test. A test circuit accessible by width was provided. Also, if multiple bits of memory with different bit and address configurations are mixed,
After the test circuits are provided, each memory is individually inspected.

[0006]

However, in a conventional test circuit device for a semiconductor memory device, during a normal operation,
In spite of being able to read / write in multi-bit width, read / write is divided into small bit widths during inspection, so “multi-bit width / small bit width” in normal operation to access the entire memory area The double access is required, the inspection time becomes longer, and the inspection cost becomes higher.
In the case where there are a plurality of readable and writable memories having different bit configurations and a multi-bit width, the above-described problem is further serious because the inspection has been performed individually in the related art. Therefore, in a test circuit device of a semiconductor memory device, it is required to efficiently test the entire memory area with a small bit width.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel test circuit device and a test circuit device for a semiconductor memory device capable of efficiently testing a semiconductor integrated device having a multi-bit width memory with a small bit width. .

[0008]

According to a first aspect of the present invention, there is provided a parallel test circuit device for a semiconductor memory device, which is a memory that can be read and written with a multi-bit width (m-bit width) and has a small bit width (q-bit width) at the time of inspection. ), A plurality of divided memory blocks divided by the number of bits (q) to be read and written in parallel, and one bit each having a small bit width provided for each of the plurality of divided memory blocks and assigned to each divided memory block. Means for extending each bit and writing input data with m / q bit width for each divided memory block, and m / q bit width provided for each divided memory block written by this means and read from the divided memory block Means for comparing each bit for each data of, and means for determining whether all the comparison results of the divided memory blocks match,
Means for outputting one representative bit for each divided memory block when all the data match, and outputting one bit of unique data when they do not match.

According to the first aspect of the present invention, the entire memory area can be inspected with a small bit width with the same number of accesses as the number of accesses for reading and writing with a multi-bit width. Reading and writing can be performed with all combination data values except for unique data values output when data to be read and written with a small bit width do not match, thereby improving inspection efficiency. In addition, the inspection time is m / q times shorter than the conventional inspection time using a test address divided into a small bit width, and if normal, the data value of reading / writing with a small bit width becomes the same. A test pattern of a memory capable of reading and writing with a multi-bit width and capable of reading and writing can be equivalent to a reading and writing pattern for a conventional memory.

According to a second aspect of the present invention, there is provided a parallel test circuit device for a semiconductor memory device, which is a memory capable of reading and writing with a multi-bit width (m-bit width), and the number of bits (q) to be read and written in parallel with a small bit width during inspection. A first plurality of divided memory blocks divided by (1) and a memory readable and writable in a multi-bit width (n-bit width) having the same address configuration and a different bit configuration as the first plurality of divided memory blocks. Sometimes a second plurality of divided memory blocks divided by the number of bits (q) to be read and written in parallel with a small bit width, and each of the first plurality of divided memory blocks and the second plurality of divided memory blocks Provided, each bit of a small bit width is allocated, each bit of the small bit data is extended for each divided memory block, and a multi-bit width is allocated for each divided memory block. Means for writing input data with a small bit width, means for comparing each bit for each multi-bit / small bit width data read from the divided memory block written by the means, Means for judging whether the comparison results of the blocks all match, and means for outputting one representative bit for each divided memory block when all the results match, and outputting one bit of unique data when they do not match It is a thing.

According to the parallel test circuit device for a semiconductor memory device according to the second aspect, in addition to the same effects as those of the first aspect, even when there are a plurality of readable / writable memories with a multi-bit width having different bit configurations, the number of bits is small. Inspection by width becomes possible. In addition, what has been individually inspected in the past can be inspected in parallel with a small bit width, so the inspection time can be greatly reduced.If normal, the data value for reading and writing with a small bit width is the same, so the address configuration is the same Thus, a test pattern of a memory capable of reading and writing in a plurality of multi-bit widths having different bit configurations can be equivalent to a read / write pattern for a conventional memory.

According to a third aspect of the present invention, there is provided a parallel test circuit device for a semiconductor memory device, wherein the second plurality of memory blocks are replaced with the first plurality of divided memories instead of the second plurality of divided memory blocks. This memory is readable and writable in a multi-bit width (n-bit width) having a different block configuration, address configuration and bit configuration, and is divided by the number of bits (q) to be read and written in parallel with a small bit width during inspection.

According to the parallel test circuit device of the semiconductor memory device according to the present invention, what has been individually tested in the past can be tested in parallel with a small bit width, so that the test time can be greatly reduced and the normal test can be performed normally. If the read / write data value of the small bit width is the same, the test pattern of the memory that can read and write with multiple bit widths with different address configuration and bit configuration uses the same test pattern as the read / write pattern for the conventional memory it can. Other effects are the same as those of the second aspect. When comparing multi-bit width / small bit width data read in units of divided memory blocks, comparison is made while ignoring read data from a memory that specifies an address where each bit cannot be read or written for each data.

According to a fourth aspect of the present invention, there is provided a test circuit device for a semiconductor memory device according to the first, second or third aspect of the present invention, and data for the parallel test circuit device of the semiconductor memory device. And a BIST circuit for reading and writing. According to the test circuit device of the fourth aspect, in addition to the same effects as those of the first, second and third aspects, the multi-bit width data line and the multi-bit width read circuit inside the BIST circuit are not required. Necessary, the area of the inspection circuit in the semiconductor integrated circuit device does not increase, and the generation pattern of the BIST circuit and the data comparison circuit for the data to be read / written with a small bit width are the same as those of the conventional memory read / write detection circuit. Can be used.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (First Embodiment) FIG. 1 shows a parallel test circuit device 300 of a semiconductor memory device according to a first embodiment of the present invention.
Indicates that a memory capable of reading and writing data with a multi-bit width (m, for example, 16-bit width) has the same number of accesses as a read / write operation with a small bit width (q (<m), for example, 4-bit width) at the time of inspection. Can read / write the entire memory area, and the unique value read when the read data of a small bit width and the write data do not match (one type)
You can read and write the same data values except for.

In FIG. 1, during normal operation, write data 141 to 144 (WD1 to 16).
Read data 151 to 154 (RD1 to RD1) having a bit width
At the time of inspection of a memory readable and writable with a multi-bit width (16-bit width) of 6), 4-bit-wide test write data 19
1 to 194 (TWD1 to 4) · Test read data 71 to 74 (TRD1 to 4) of 4 bit width
In order to make it possible to read and write data with a bit width of 16 bits, write data 141 to 144 and read data 151 to
154 is 4-bit write data 141 / read data 151, write data 142 / read data 152,
The divided memory blocks 101 to 104, which can be read and written by the write data 143 / read data 153 and the write data 144 / read data 154, are divided into four (the number of bits of a small bit width), and the test write data 191 to
Each of the 194 bits is divided into each of the divided memory blocks 101-101.
Allocated one bit to 104, divided memory block 1
01 to 104 are written as address data 160 (AD), write signal 170 (WE), read signal 180 (RE), test address enable signal 90 (TADE), test data selection signal 100 (TSEL), and test address 80 (TA).
D1 to D2), and the 4-bit test write data 191 to 194 are divided into divided memory blocks 101 to 104.
And the 16-bit width test read memory data 61-64 is divided into four divided memory blocks 101-104.
Outputs bit by bit (multi-bit width / small bit width). The circuit configuration of each of the divided memory blocks 101 to 104 has the same circuit operation except for the weighting of data bits. The 16-bit test read memory data 61 to 64 are stored in the parallel read test circuit 1 (PT
ST1) and the parallel read test circuit 1
Are controlled by a test address enable signal 90, a test data selection signal 100, and a test address 80, and output test read data 71 to 74 having a 4-bit width (decimal bit width).

FIG. 2 shows the parallel read test circuit 1 shown in FIG.
FIG. 2 shows an internal block diagram of the data comparison circuit 20.
(TDC1) and the judgment test data output circuit 30 (TDO
S1) and the test data readout circuit 11 constituted by the above. Test read memory data 61 is connected to the data comparison circuit 20 and the judgment test data output circuit 30, the data comparison circuit 20 outputs a data comparison result signal 41, and the judgment test data output circuit 30 outputs the test address 80 and the test address permission. The test read data 71 is output under the control of the signal 90, the test data selection signal 100, and the coincidence determination signal 51. The circuit configuration of each of the test data read circuits 11 to 14 is the same as that of the test data read circuit 11 except for the weighting of data bits. The data comparison result signals 41 to 41 output from the respective test data read circuits 11 to 14
The reference numeral 44 is connected to the match determination circuit 50 (JCC), and the match determination circuit 50 returns a match determination signal 51 to each of the test data read circuits 11 to 14.

The parallel read / write operation at the time of test read / write, which is a feature of the present invention, is performed by a test address enable signal 9
0 is disabled and the test data selection signal 100 is enabled, and during a parallel test write, the test data selection signal 1
When 00 is enabled, the data input selection circuit 120 (D
In IN1), the operation is such that the test write data 191 having a 1-bit width is selected and the write data 141 having a 4-bit width is not selected. When the test address enable signal 90 is disabled, the test address 80 is disabled, and the data input selection circuit 120 replaces each bit of the 4-bit width memory write data 121 with the 1-bit width test write data 191. The data expansion operation is realized by outputting data at the same time. The data of the 4-bit width memory write data 121 is transmitted to the 4-bit width readable / writable memory 110 (MEM), and is written in the 4-bit width to the address specified by the address data 160 by the write signal 170. Since the divided memory blocks 101 to 104 perform the same operation as described above, the 4-bit test write data 191 to 194 are expanded to a 16-bit width by the data input selection circuit 120.
Write signal 1 at the address of the specified address data 160
70, the divided memory block 101 divided into four
Each data is written to the readable / writable memory 110 with a 4-bit width of ~ 104.

Next, at the time of the parallel test read, in order to read the 16-bit data written by expanding the 4-bit test write data 191 to 194, the 4-bit data in the divided memory block 101 is read by the read signal 180. The 4-bit data at the address designated by the address data 160 from the memory 110 readable and writable by the width propagates to the data output selection circuit 130 (DOUT1) via the 4-bit memory read data 111. When the test data selection signal 100 is enabled in the data output selection circuit 130, the 4-bit test read memory data 61
And disables the output of the 4-bit width write data 151. Divided memory blocks 101-104
Performs the same operation as described above, so that the read signal 180
Of the address of the designated address data 160
Each of the divided memory blocks 101 to 104 is read from the readable / writable memory 110 having a 4-bit width in 4-bit widths, and transmitted to the parallel read test circuit 1 as 16-bit width test read memory data 61 to 64. You. The transmitted test read memory data 61 to 64 having a 4-bit width are transmitted to the parallel read test circuit 1 shown in FIG.
The test read memory data 61 having a 4-bit width propagated to each of the test data read circuits 11 to 14 is propagated to the data comparison circuit 20 and the judgment test data output circuit 30 in the test data read circuit 11. You. Since the transmitted 4-bit test read memory data 61 is the same as the 4-bit data generated by expanding the same data when the 1-bit test write data 191 is written, the data comparison circuit 20 The test read memory data 61 having a 4-bit width is compared for each bit, and a data comparison result signal 41 as a comparison result is output. Since the test data read circuits 11 to 14 perform the same operation as described above, the data comparison result signal 41
To 44 are transmitted to the match determination circuit 50, and the match determination circuit 5
At 0, it is determined whether or not all of the data comparison result signals 41 to 44 match, and the match determination signal 51 is returned to each of the determination test data output circuits 30 in the test data read circuits 11 to 14. In the test data output circuit 30, when the test address permission signal 90 is disabled, the test address 80 is disabled. If all of the returned match determination signals 51 match, the 4-bit width of the divided memory block 101 is changed. Read / write memory 110
Selects one representative bit of the test read memory data 61 having a 4-bit width read out from the memory, and generates a unique 1-bit data if at least one of the results of the match determination signal 51 does not match. , Test data selection signal 10
When 0 is enabled, it operates to output the selectively generated 1-bit data to the test read data 71.
The test data read circuits 11 to 14 perform the same operation as described above, so that the 16-bit data at the address specified by the address data 160 by the read signal 180 is read as the 4-bit test read data 71 to 74. Can be.

By the above-described parallel read / write operation at the time of test read / write, the 4-bit test write data 19 is written.
1 to 194 enable 16-bit width writing to the entire memory area at the same number of times as the normal 16-bit width writing. If the read data is the same as the write data and the data is normal, the 16-bit width data after writing is written. The same data value as the 4-bit width test write data 191 to 194 when writing from the entire memory area is performed at the same number of times as the normal 16-bit width read time when reading the 4-bit width test read data 71 If the read data is invalid,
Test read data 71-
A parallel test circuit device of a semiconductor memory device which can be read out by 74 is realized. Assuming that the data values of the unique 4-bit test read data 71 to 74 when the read data is not normal are (1001), there are 15 combinations of 4-bit data excluding (1001). Can be read and written. generally,
For the read / write test of the semiconductor memory device, three types of test pattern data, that is, all-bit 0 pattern, all-bit 1 pattern, and checker pattern (a pattern in which adjacent bit patterns are contradictory) are sufficient. Due to the parallel read / write operation during read / write, 4
The entire memory area can be inspected with the same number of accesses as the number of accesses for reading and writing a semiconductor memory device having a bit width of 16 bits, and the inspection time can be greatly reduced. In the case of the first embodiment, the efficiency is increased four times.

Next, the conventional read / write operation at the time of test read / write operates when the test address enable signal 90 and the test data selection signal 100 are enabled, and at the time of conventional test write, the divided memory block 10
1, when the test data selection signal 100 is enabled, the data input selection circuit 120 operates to select the 1-bit width test write data 191 and to deselect the 4-bit width write data 141. When the test address permission signal 90 is enabled, one bit of the 4-bit width memory write data 121 of the data input selection circuit 120 selected by the four combinations of addresses generated by the 2-bit width test address 80 is used. It operates to output the same data as the test write data 191. The selected 1-bit data of the 4-bit width memory write data 121 is propagated to the 4-bit width readable / writable memory 110 of the divided memory block 101, and the write signal 170 causes the 1-bit address to be assigned to the address specified by the address data 160. Bit data is written. Since the divided memory blocks 101 to 104 perform the same operation as described above, the 4-bit test write data 191 to 19
4 writes the bit selected by the 2-bit test address 80 to the address specified by the address data 160 by the write signal 170 using the divided memory blocks 101 to 101.
A 4-bit wide readable and writable memory 11
Bits are written to 0 bit by bit. At the time of the conventional test read, the 4-bit width data of the address designated by the address data 160 from the 4-bit width readable / writable memory 110 in the written divided memory block 101 is read by the read signal 180. Is transmitted to the data output selection circuit 130 through the memory read data 111 of FIG. When the test data selection signal 100 is enabled, the data output selection circuit 130 outputs the 4-bit width test read memory data 61 and disables the 4-bit width write data 151 output. Since the divided memory blocks 101 to 104 perform the same operation as described above,
The divided memory block 101 divided into four at the address of the designated address data 160 by the read signal 180
Readable and writable memory 1 with 4-bit width of
The data is read out from 10 to 4 bits at a time and transmitted to the parallel read test circuit 1 as test read memory data 61 to 64 having 16 bits. The transmitted 4-bit test read memory data 61 to 64 are transmitted to the respective test data read circuits 11 to 14 in the parallel read test circuit 1 of FIG. 61 is a test data read circuit 1
1 is transmitted to the data comparison circuit 20 and the judgment test data output circuit 30. When the test address enable signal 90 is enabled, the determination test data output circuit 30 disables the match determination signal 51, and outputs a 4-bit width designated by four combinations of addresses generated by the 2-bit width test address 80. Test read memory data 6
It operates to select 1 bit of 1 and output it to the test read data 71. Test data read circuits 11-1
4 performs the same operation as described above, so that the 4 bits selected by the test address 80 out of the 16-bit data at the address specified by the address data 160 are used as the test read data 71 to 74 by the read signal 180. Can be read.

By the read / write operation at the time of the conventional test read / write, the divided memory blocks 101 to 10 specified by the address data 160 and the test address 80 are obtained.
4 is a readable / writable memory 110 with a 4-bit width in each
To the address 4 bits of test write data 191 to 19
Conventionally, data can be read and written by using test read data 71 to 74 having a width of 4 and 4 bits, and by adding a test address 80 at the time of inspection, 16-bit width data is divided into 4-bit widths and can be accessed with a 4-bit width. The operation of the test circuit is realized.

Finally, the normal read / write operation is performed when the test address enable signal 90 and the test data selection signal 100 are disabled.
At the time of normal writing, in the divided memory block 101, when the test data selection signal 100 is disabled in the data input selection circuit 120, the 1-bit width test write data 191 is disabled, and the 4-bit width write data 141 is output. The selected signal is transmitted to the memory 110 that can read and write data in a 4-bit width via the memory write data 121 having a 4-bit width, and is written into the address specified by the address data 160 in a 4-bit width by a write signal 170. Since the divided memory blocks 101 to 104 perform the same operation as described above, the address data 160 to which the write data 141 to 144 having a 16-bit width are designated is written.
Are written to the memory 110 which can be read and written in a 4-bit width of the divided memory blocks 101 to 104 by the write signal 170 at the address. At the time of normal read, in order to read the written 16-bit width data, the 4-bit width from the 4-bit width memory 110 of the divided memory block 101 at the address specified by the address data 160 by the read signal 180 is used. Is transmitted to the data output selection circuit 130 via the memory read data 111 having a 4-bit width. Since the data output selection circuit 130 disables the test data selection signal 100,
The transmitted 4-bit width memory read data 111 is output as 4-bit width read data 151, and the test read memory data 61 is disabled. Since the divided memory blocks 101 to 104 perform the same operation as described above, the address data 160
The 16-bit data at the address designated by (1) can be read as the read data 151-154.

By the above-described read / write operation at the time of normal read / write, 16-bit width write data 141 to 1 is written to the address of the semiconductor memory device designated by address data 160.
44 and the read data 151 to 154 enable reading and writing, thereby realizing a normal reading and writing operation. (Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 shows a parallel test circuit device 301 of a semiconductor memory device according to a second embodiment of the present invention, in which a memory readable and writable with an m-bit width (16-bit width) having the same address configuration and a different bit configuration, and n A multi-bit readable / writable memory having a plurality of readable / writable memories with a bit width (12-bit width) can be read / written in parallel with a small bit width (q = 4 bit width). When the read data of the bit width and the write data do not match, reading and writing can be performed with the same data value except for a unique value (one type) read.

In FIG. 3, write data 141 to 144 and read data 151 having different bit widths during normal operation are shown.
Readable / writable memory 200 with 16-bit width of ~ 154
And write data 241 to 244 and read data 251
Readable / writable memory 210 with a 12-bit width of ~ 254
As in the first embodiment, the memory 200 readable / writable with a 16-bit width is divided into four (the number of bits of a small bit width) into divided memory blocks 101 to 104 readable / writable with a 4-bit width. The memory 210 readable / writable in width is divided into four memory blocks 201 to 204 readable / writable in 3-bit width. Each of the divided memory blocks 101 to 104 of the memory 200 capable of reading and writing each bit of the 4-bit width test write data 191 to 194 in a 16-bit width and each of the divided memory blocks 201 to 104 of the memory 210 capable of reading and writing a 12-bit width. 20
4 is divided into one bit at a time, and divided memory blocks 101 to 104 of the memory 200 readable and writable with a 16-bit width.
The divided memory blocks 201 to 204 of the memory 210 readable and writable with a 12-bit width are
A write signal 170, a read signal 180, a test address enable signal 90, a test data selection signal 100, a test address 80, and a 16-bit readable / writable memory 2.
The memory 200 is readable and writable with a 16-bit width, and the memory 210 is readable and writable with a 12-bit width. Has the same address configuration, the same address data 160 is used for all memory areas.
4-bit test write data 191-1 specified by
94 and 16-bit readable and writable memories 200 and 1
Data can be written to the address of the memory 210 that can be read and written with a 2-bit width.

At the time of reading, the memory 200 readable and writable with a 16-bit width stores the 16-bit test read memory data 261 to 264 in the divided memory block 10.
The memory 210 which outputs 4 bits at a time from 1 to 104 and is readable and writable in a 12-bit width is used to divide the test read memory data 271 to 274 having a 12-bit width into divided memory blocks 2
It outputs 3 bits at a time from 01 to 204. The circuit configuration of each of the divided memory blocks 101 to 104 of the memory 200 readable and writable with a 16-bit width has the same circuit operation except for the weighting of data bits.
The circuit configuration of each of the divided memory blocks 201 to 204 of the memory 210 readable and writable with a 2-bit width is the same as that of the circuit operation except for the weighting of data bits. 16-bit test read memory data 261 to 26 of the memory 200 readable and writable in 16-bit width
4 and 12 bits of memory 210 readable and writable in 12-bit width
The bit-width test read memory data 271 to 274 are connected to a parallel read test circuit 400 (PTST2), and the parallel read test circuit 400 generates a test address enable signal 90, a test data selection signal 100, a test address 80, and a memory enable signal. 291 and 292
And outputs test read data 71 to 74 having a 4-bit width (fractional bit width).

FIG. 4 shows the parallel read test circuit 4 in FIG.
FIG. 4 shows an internal block diagram of the data comparison circuit 420 (TDC2) and the judgment test data output circuit 430.
(TDOS2). Test read memory data 261 and 271 are connected to the data comparison circuit 420 and the judgment test data output circuit 430, the data comparison circuit 420 outputs the data comparison result signal 41, and the judgment test data output circuit 430 The test read data 71 is output under the control of the address permission signal 90, the test data selection signal 100, the coincidence determination signal 51, and the memory enable signals 291 and 292.

Each test data read circuit 411-
The circuit configuration of the test data readout circuit 414 differs only in the weighting of data bits.
It is the same as 11. Data comparison result signal 4 output from each of test data read circuits 411 to 414
1 to 44 are connected to the match determination circuit 50, and the match determination circuit 50 returns the match determination signal 51 to the respective test data read circuits 411 to 414.

The parallel read / write operation at the time of test read / write, which is a feature of the present invention, is performed by a test address enable signal 9
It operates when 0 is disabled, the test data select signal 100 is enabled, and both of the memory enable signals 291 and 292 are enabled. At the time of parallel test write, reading and writing are performed in a 16-bit width as in the first embodiment. The divided memory blocks 101 to 10 of the possible memory 200
4, the test write data 191-
194 is expanded to a 16-bit width, and is written to each of the divided memory blocks 101 to 104 by a write signal 170 at the address of the designated address data 160 in units of 4 bits. On the other hand, in the divided memory blocks 201 to 204 of the memory 210 readable and writable in a 12-bit width, the 4-bit test write data 191 to 1
94 is expanded to a 12-bit width, and three bits are written into each of the divided memory blocks 201 to 204 by the write signal 170 at the address of the designated address data 160.

Next, at the time of the parallel test read, the 16-bit data of the memory 200 readable and writable with the 16-bit width written and expanded with the test write data 191 to 194 having the 4-bit width and the readable and writable data with the 12-bit width are written. In order to read the 12-bit data of the memory 210, the memory 200 readable and writable with the 16-bit width of the address designated by the address data 160 is read by the read signal 180.
Are read from the divided memory blocks 101 to 104 in units of 4 bits at a time, and are read as test read memory data 261 to 264 having a width of 16 bits.
On the other hand, from the divided memory blocks 201 to 204 of the memory 210 readable and writable with a 12-bit width,
The data is read out bit by bit and transmitted to the parallel read test circuit 400 as test read memory data 271 to 274 having a width of 12 bits. The transmitted 4-bit test read memory data 261 to 264 and the 3-bit test read memory data 271 to 274 are transmitted to the respective test data read circuits 411 to 414 in the parallel read test circuit 400 of FIG. Propagated, propagated 4
The test read memory data 261 having a bit width and the test read memory data 271 having a 3-bit width are transmitted to the data comparison circuit 420 and the judgment test data output circuit 430 in the test data read circuit 411. 4 propagated
Since the bit-width test read memory data 261 and the 3-bit width test read memory data 271 are the same as the data generated by extending the same data when writing the 1-bit width test write data 191, the data comparison circuit 420 Then, a total of 7 bits of the transmitted 4-bit test read memory data 261 and the 3-bit test read memory data 271 are compared for each bit, and a data comparison result signal 41 as a comparison result is output. Since the test data read circuits 411 to 414 perform the same operation as described above, the data comparison result signals 41 to 44 are propagated to the match determination circuit 50, and the match determination circuit 50 matches all the data comparison result signals 41 to 44. Whether the test data readout circuits 411 to 41
4 is returned to each judgment test data output circuit 430. In the test data output circuit 430, when the test address enable signal 90 is disabled and the memory enable signals 291 and 292 are both enabled, the test address 80 is disabled, and the results of the returned match determination signal 51 are all matched. If so, one representative bit is selected from a total of 7 bits of the 4-bit width test read memory data 261 or the 3-bit width test read memory data 271, and if at least one result of the match determination signal 51 does not match, it is unique. The test data selection signal 100 is enabled, and when the test data selection signal 100 is enabled, the selected and generated 1-bit data is transferred to the test read data 7.
It operates to output to 1. The test data read circuits 411 to 414 operate in the same manner as the contents described above, so that the memory 200 capable of reading and writing in the 16-bit width of the address specified by the address data 160 by the read signal 180 is used.
The 16-bit data and the 12-bit data of the memory 210 readable and writable with the 12-bit width can be simultaneously read out using the 4-bit test read data 71 to 74.

By the parallel read / write operation at the time of the test read / write, the 4-bit test write data 19 is written.
According to 1 to 194, the memory 200 capable of reading and writing with the same 16-bit width and the memory 210 capable of reading and writing with the 12-bit width can simultaneously write to all memory areas at the same number of times as the normal number of times of writing with multiple bits. When the read data is the same as the write data and is normal, the same data value as the 4-bit-wide test write data 191 to 194 at the time of writing is written to 4
A parallel test circuit device of a semiconductor memory device that can be read with test read data 71 to 74 having a bit width and, if the read data is invalid, can read data having a unique 4-bit width with test read data 71 to 74 Has been realized. According to the parallel read / write operation at the time of test read / write of the present invention, a plurality of semiconductor memory devices having a small bit width (4 bit width) and the same multi-bit width (16 bit width and 12 bit width) having the same address configuration can be used. The entire memory area can be inspected with the same number of accesses as the number of accesses for reading and writing, and the inspection time can be greatly reduced. In the case of the second embodiment, the efficiency is increased eight times. Next, the read / write operation at the time of the conventional test read / write is performed according to the test address enable signal 90.
When the test data selection signal 100 is enabled, the memory enable signal 291 is enabled, and the memory enable signal 292 is disabled, the memory 200 readable and writable with a 16-bit width is used for the conventional test read / write of the first embodiment. The parallel read test circuit 400 selects the 4-bit test read memory data 261 to 264 read from the 16-bit readable / writable memory 200, and performs the same operation as the conventional operation of the first embodiment. The same operation as the test read / write operation is performed.
Divides the 16-bit width data into 4-bit widths, and makes it possible to read and write the 4-bit width test write data 191 to 194 and the 4-bit width test read data 71 to 74 into the 16-bit width readable / writable memory 200. This realizes the operation of a conventional test circuit that can be accessed with a 4-bit width. On the other hand, when the test address permission signal 90 and the test data selection signal 100 are enabled, the memory enable signal 291 is disabled, and the memory enable signal 292 is enabled, the memory 210 that can be read and written with a 12-bit width is the first embodiment. Performs the same operation as the conventional test read / write operation, and the parallel read test circuit 400 selects 4-bit test read memory data 271 to 274 read from the 12-bit readable / writable memory 210, and The same operation as the conventional test read / write operation of the embodiment is performed.
The bit-width data is divided into 4-bit widths, and the data can be read / written to / from the memory 210 readable / writable with the 12-bit width using the 4-bit width test write data 191 to 194 and the 4-bit width test read data 71 to 74. The operation of a conventional test circuit that can be accessed with a bit width is realized.

Finally, the read / write operation in the normal read / write mode is as follows. The test address permission signal 90 and the test data selection signal 100 are disabled, the memory enable signal 291 is enabled, and the memory enable signal 2 is enabled.
When 92 is disabled, 16-bit readable / writable memory 200 and parallel read test circuit 400
Performs the same operation as the read / write operation at the time of normal read / write of the first embodiment, and can read / write the memory 200 having a 16-bit width specified by the address data 160.
Can be read and written to the address with 16-bit write data 141 to 144 and read data 151 to 154,
A normal read / write operation is realized.

On the other hand, when the test address enable signal 90 and the test data selection signal 100 are disabled, the memory enable signal 291 is disabled, and the memory enable signal 292 is enabled, the memory 210 that can be read / written with a 12-bit width and the parallel read test are used. Circuit 40
0 performs the same operation as the read / write operation at the time of the normal read / write of the first embodiment.
Readable / writable memory 21 with 12-bit width specified by
Write data 241 to 244 of 12-bit width to address 0
And read data 251 to 254, thereby enabling normal read / write operation.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. In the description of the second embodiment, a test circuit device for reading and writing a plurality of memories having the same address structure but different bit structures which can be read and written with a multi-bit width in parallel with a small bit width has been described with reference to FIGS. The parallel read test circuit 400 shown in FIG. 4 in FIG.
This is a parallel test circuit device of a semiconductor memory device replaced with 00, which is different from the address configuration and the bit configuration, and is readable and writable with an m-bit width (16-bit width) and readable and writable with an n-bit width (12-bit width). A multi-bit readable / writable memory having a plurality of possible memories, all the memories can be read / written in parallel with a small bit width (4 bit width) at the time of inspection, and the read data of the small bit width and the write data do not match. In this case, reading and writing can be performed with the same data value except for the unique value (one type) read out.

The operation of FIG. 3 except for the parallel read test circuit 400 shown in FIG. 4 in FIG. 3 is the same as the operation described in the second embodiment. For this reason, FIG.
Only the operation of the parallel read test circuit 500 shown in FIG. FIG. 5 shows a data comparison circuit 520 (TDC
3) and the judgment test data output circuit 530 (TDOS3)
And a test data read circuit 511 composed of Test read memory data 261 and 271 are provided to data comparison circuit 520 and determination test data output circuit 530.
Is connected to the data comparison circuit 520, and the address overflow signal 591 of the memory 200 readable and writable in 16 bits and the memory 210 readable and writable in 12 bits are connected.
, And outputs the data comparison result signal 41 controlled by the address overflow signal 592, and the test data output circuit 530 outputs the test address 80, the test address enable signal 90, the test data selection signal 100, and the match determination signal 5
The test read data is controlled by a memory enable signal 291 and an address overflow signal 591 of the memory 200 readable and writable in 1 and 16 bit width, a memory enable signal 292 of the memory 210 readable and writable in 12 bit width, and an address overflow signal 592. 71 is output.

Each test data read circuit 511-
The circuit configuration of the circuit 514 is the same as that of the test data read circuit 511 except for the weighting of data bits. Each test data read circuit 51
Data comparison result signals 41 to 4 output from 1 to 514
4 is connected to the coincidence discrimination circuit 50, and the coincidence discrimination circuit 50 returns the coincidence discrimination signal 51 to each of the test data read circuits 511 to 514 in the same manner as in the second embodiment.

At the time of parallel read / write at the time of test read / write which is a feature of the present invention, the test data read circuit 51
When the address overflow signal 591 indicating that the address of the memory 200 readable and writable in 16 bits has overflowed is turned on, the data comparison circuit 520 in 1 has a 4-bit width transmitted from the memory 200 readable and writable in 16 bits. Test read memory data 2
The comparison is not performed for each of the four bits of 61, but is performed for each of the three bits of the test read memory data 271 having a width of three bits transmitted from the memory 210 that is readable and writable with a width of 12 bits. , When the address overflow signal 592 indicating that the address of the memory 210 readable and writable with a 12-bit width overflows, the memory 21 readable and writable with a 12-bit width
The 3-bit test read memory data 271 propagated from the 16-bit readable / writable memory 200 is not compared for every 3 bits of the 3-bit test read memory data 271 propagated from 0. Perform a bit-by-bit comparison of only the bits. When neither the address overflow signal 591 nor the address overflow signal 592 is present, a comparison is made for every 7 bits of the test read memory data 261 and 271 as in the second embodiment. Thereafter, the comparison circuit 520 outputs a data comparison result signal 41 indicating a comparison result indicating whether or not the data match.
Is output. Test data read circuits 511 to 514
Performs the same operation as described above, the data comparison result signals 41 to 44 are propagated to the match determination circuit 50, and the match determination circuit 50 determines whether all of the data comparison result signals 41 to 44 match or not. The determination signal 51 is returned to each of the determination test data output circuits 530 in the test data read circuits 511 to 514. In the test data output circuit 530, when the test address enable signal 90 is disabled and both of the memory enable signals 291 and 292 are enabled, the test address 80 is disabled, and the results of the returned match determination signal 51 are all matched. If there is, when the address overflow signal 591 of the memory 200 readable and writable with a 16-bit width is asserted, a representative 1 bit is selected from a total of 3 bits of the test read memory data 271 having a 3-bit width, and conversely, reading and writing with a 12-bit width When the address overflow signal 592 of the possible memory 210 is asserted, a representative 1 bit is selected from a total of 4 bits of the test read memory data 261 having a width of 4 bits,
When neither the address overflow signal 591 nor the address overflow signal 592 is present, the representative 1 from the total 7 bits of the test read memory data 261 and 271 as in the second embodiment.
Select a bit. If at least one result of the match determination signal 51 does not match, the operation is performed to generate unique 1-bit data. When the test data selection signal 100 is enabled, the selected and generated 1-bit data is output. It operates to output data to the test read data 71.
Since the test data read circuits 411 to 414 perform the same operation as the above-described contents, the 16-bit test read memory data 261 of the 16-bit readable / writable memory 200 and the 12-bit readable / writable memory 210 of the memory 200
Of the 12-bit wide test read memory data 271
The data can be read simultaneously as the test read data 71 to 74 having the bit width. The operation of the parallel read test circuit 500 is the same as that of the parallel read test circuit 400 of the second embodiment except for the above.

By the above-described operation of the parallel read test circuit 500, the number of accesses to read / write a plurality of semiconductor memory devices having different address configurations and bit configurations with different multi-bit widths (16-bit width and 12-bit width) is improved. Small bit width (4 bit width) with the same number of accesses
Can inspect the entire memory area, and the inspection time can be greatly reduced.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a parallel test of the semiconductor memory device according to the first, second, or third embodiment for reading and writing data by a BIST (Built In Self Test) circuit that diagnoses reading and writing of a memory. 1 shows a test circuit device using a circuit device.

That is, the test circuit device includes a parallel test circuit device of the semiconductor memory device according to the first, second, or third embodiment, and a parallel test circuit device of the semiconductor memory device. A BIST circuit for reading and writing data from and to the device. In FIG. 6, the parallel test circuit device 300 of the semiconductor memory device performs the operation described in any of the first to third embodiments, and the BIST circuit 650 outputs a BIST circuit enable signal. If 660 is enabled, B
When the IST write signal 632 is enabled, the BIST address data 622 and the small bit width (4 bit width) BI
ST write data 612 is generated, a write operation is performed on the memory, and when the BIST read signal 642 is enabled, BIST address data 622 is generated, a read operation is performed on the memory, and the read small bit width is read. (4 bit width) test read data 670 is determined whether it is the same as the data at the time of writing,
This is a test circuit that outputs an ST determination result signal 700 and is capable of self-diagnosing all memory areas based on a specific test flow.

When the BIST circuit enable signal 660 and the test data selection signal 100 are enabled and the test address enable signal 90 is disabled, the test write data switching circuit 610, address data switching circuit 620, write signal switching circuit 630, read signal The switching circuit 640 does not select the external test write data 611, the external address data 621, the external write signal 631, and the external read signal 641, respectively.
ST write data 612, BIST address data 62
2, BIST write signal 632, BIST read signal 6
42 is selected, and test write data 613, address data 623, write signal 633, and read signal 643 are respectively selected.
Is output. Therefore, the BIST write data 612, BIST address data 622, BIST write signal 632, and BIST read signal 642 generated by the BIST circuit 650 are stored in the parallel test circuit device 30 of the semiconductor memory device.
To 0, the test write data 613 and the address data 62
3, propagated as a write signal 633 and a read signal 643, the parallel test circuit device 300 of the semiconductor memory device performs the parallel read / write operation at the time of test read / write described in the first to third embodiments. By doing so, data can be read and written with a small bit width.

On the other hand, the BIST circuit enable signal 6
When 60 is disabled, the test write data switching circuit 610, the address data switching circuit 620,
The write signal switching circuit 630 and the read signal switching circuit 640 provide BIST write data 612 and BIS
T address data 622, BIST write signal 632,
Without selecting the BIST read signal 642, the external test write data 611, the external address data 621, the external write signal 631, and the external read signal 641 are selected, respectively.
Each of the test write data 613 and the address data 62
3, the write signal 633 and the read signal 643, the parallel test circuit device 300 of the semiconductor memory device
The parallel read / write operation at the time of test read / write with a small bit width described in the third to third embodiments,
The conventional test read / write operation with a small bit width and the normal read / write operation with a large bit width can be performed.

Note that 680 is multi-bit (16-bit) write data, and 690 is multi-bit (16-bit) read data. At the time of reading and writing data by the BIST circuit, the test circuit device incorporating the parallel test circuit device of the semiconductor memory device according to the first embodiment to the third embodiment may be used for the read / write inspection using the BIST circuit. The entire memory area can be inspected with a small bit width with the same number of accesses as the number of accesses for reading and writing with a multi-bit width. At the time of inspection, writing and reading data with a small bit width become the same data.
The configuration of the write pattern generator and the data comparator of the IST circuit can be the same as the configuration used at the time of reading and writing of the conventional memory, and the reading and writing can be performed with a small bit width. As compared with the above, the number of data lines can be reduced and the read / comparison circuit inside the BIST circuit can be simplified, and the area of the BIST circuit can be reduced.

In FIGS. 1 to 6, 2, 3,.
4 and 16 are the bit widths of each signal group, respectively.

[0045]

According to the parallel test circuit device of the semiconductor memory device according to the first aspect, it is possible to inspect the entire memory area with a small bit width with the same number of accesses as the number of accesses for reading and writing with a multi-bit width. In addition, reading and writing can be performed with all combinations of data values except for unique data values output when data to be read and written with a small bit width do not match, thereby improving inspection efficiency. In addition, the inspection time is m / q times shorter than the conventional inspection time using a test address divided into small bit widths, and if normal, the data value for reading and writing with a small bit width becomes the same.
A test pattern of a memory capable of reading and writing with a small bit width and capable of reading and writing with a large bit width can use a pattern equivalent to a read / write pattern for a conventional memory.

According to the parallel test circuit device for a semiconductor memory device according to the second aspect, in addition to the same effects as those of the first aspect, a small number of bits can be obtained even when there are a plurality of readable and writable memories with a multi-bit width having different bit configurations. Inspection by width becomes possible. In addition, what has been individually inspected in the past can be inspected in parallel with a small bit width, so the inspection time can be greatly reduced.If normal, the data value for reading and writing with a small bit width is the same, so the address configuration is the same Thus, a test pattern of a memory capable of reading and writing in a plurality of multi-bit widths having different bit configurations can be equivalent to a read / write pattern for a conventional memory.

According to the parallel test circuit device of the semiconductor memory device according to the third aspect, what has been individually tested in the past can be tested in parallel with a small bit width, so that the test time can be greatly reduced, If the read / write data value of the small bit width is the same, the test pattern of the memory that can read and write with multiple bit widths with different address configuration and bit configuration uses the same test pattern as the read / write pattern for the conventional memory it can. Other effects are the same as those of the second aspect. When comparing multi-bit width / small bit width data read in units of divided memory blocks, comparison is made while ignoring read data from a memory that specifies an address where each bit cannot be read or written for each data.

According to the test circuit device of the fourth aspect,
In addition to the same effects as those of claim 1, claim 2 or claim 3, since a multi-bit width data line and a multi-bit width reading circuit inside the BIST circuit are unnecessary,
The area of the inspection circuit in the semiconductor integrated circuit device does not increase, and the generation pattern of the BIST circuit and the data comparison circuit for the data to be read / written with a small bit width can be the same as the conventional read / write detection circuit for the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a parallel test circuit device of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a parallel read test circuit of the memory shown in FIG. 1;

FIG. 3 is a block diagram illustrating a parallel test circuit device of a semiconductor memory device according to a second embodiment;

FIG. 4 is a block diagram showing a parallel read test circuit of the memory shown in FIG. 1;

FIG. 5 is a block diagram showing a memory parallel read test circuit in a parallel test circuit device of a semiconductor memory device according to a third embodiment;

FIG. 6 is a block diagram of a test circuit device including a BIST circuit and a parallel test circuit device of a semiconductor memory device according to a fourth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Parallel read test circuit 11-14 ... Test data read circuit 20 ... Data comparison circuit 30 ... Judgment test data output circuit 41-44 ... Data comparison result signal 50 ... Match judgment circuit 51 ... Match judgment signal 61-64 ... Test read Memory data 71 to 74 Test read data 80 Test address 90 Test address enable signal 100 Test data selection signal 101 to 104 Divided memory block 110 Memory 111 Data read data 120 Data input selection circuit 121 4 bits Memory write data of width 130 Data output selection circuits 141-144 Write data 151-154 Read data 160 Address data 170 Write signals 180 Read signals 191-194 Test write data 200 Memory 20 1 to 204: divided memory block 210: memory 241 to 244: write data 251 to 254: read data 261 to 264: test read memory data 271 to 274: test read memory data 291: memory enable signal 292: memory enable signal 300 Test circuit device for semiconductor integrated device 301 Test circuit device for semiconductor integrated device 400 Parallel read test circuits 411 to 414 Test data read circuit 420 Data comparison circuit 430 Judgment test data output circuit 500 Parallel read test circuit 520 Data comparison circuit 530 ... Judgment test data output circuit 511-514 ... Test data read circuit 591 ... Address overflow signal 592 ... Address overflow signal 610 ... Test write data Switching circuit 611 ... External test write data 612 ... BIST write data 613 ... Test write data 620 ... Address data switching circuit 621 ... External address data 622 ... BIST address data 623 ... Address data 630 ... Write signal switching circuit 631 ... External write signal 632 ... BIST write signal 633 ... write signal 640 ... read signal switching circuit 641 ... external read signal 642 ... BIST read signal 643 ... read signal 650 ... BIST circuit 660 ... BIST circuit enable signal 670 ... test read data 680 ... write data 690 ... Read data 700 ... BIST judgment result signal

Claims (4)

[Claims] 1. A memory capable of reading and writing with a multi-bit width (m-bit width), and a plurality of divided memory blocks divided by the number of bits (q) to be read and written in parallel with a small bit width (q-bit width) during inspection. , One bit of a small bit width provided for each of the plurality of divided memory blocks is allocated, each bit of the small bit data is expanded for each of the divided memory blocks, and an m / q bit width is allocated for each of the divided memory blocks. Means for writing input data in the divided memory block, means for comparing each bit for each m / q bit width data read from the divided memory block provided for each of the divided memory blocks, and the divided memory Means for judging whether or not all the comparison results of the blocks match; Means for outputting a bit and outputting one bit of unique data in the case of a mismatch, a parallel test circuit device for a semiconductor memory device. 2. A memory which is readable and writable with a multi-bit width (m-bit width) and divided by the number of bits (q) to be read and written in parallel with a small bit width at the time of inspection; This memory is readable and writable in a multi-bit width (n-bit width) having the same address configuration and a different bit configuration as the first plurality of divided memory blocks. ), The second plurality of divided memory blocks,
Is allocated to each divided memory block of the plurality of divided memory blocks and the divided memory blocks of the second plurality of divided memory blocks, one bit having a small bit width is allocated, and each bit of the small bit data is extended for each divided memory block. Means for writing input data with a bit width of multi-bit width / small bit width for each of the divided memory blocks, and data of a multi-bit width / small bit width read from the divided memory blocks written by the means. Means for comparing each bit every time, means for judging whether the comparison results of the divided memory blocks all match, and, when all the results match, the representative 1
Means for outputting a bit and outputting one bit of unique data in the case of a mismatch, a parallel test circuit device for a semiconductor memory device. 3. The multi-bit width of the second plurality of memory blocks, which is different from the first plurality of divided memory blocks in address configuration and bit configuration, in place of the second plurality of divided memory blocks of claim 2. 3. The parallel test circuit device for a semiconductor memory device according to claim 2, wherein the memory is a readable / writable memory (n bits wide) and divided by the number of bits (q) to be read / written in parallel with a small bit width at the time of inspection. 4. A parallel test circuit device for a semiconductor memory device according to claim 1, 2 or 3, and a BIST circuit for reading / writing data from / to the parallel test circuit device of the semiconductor memory device. Test circuit equipment.