JP2002243801A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a self-test technique capable of providing a circuit for storing failure addresses detected by a self-test circuit of a built-in memory, avoiding the operation of the circuit from being interrupted every time failure is detected, and outputting accurate failure information in real time. SOLUTION: A multiplying circuit (120) for multiplying a clock signal (ϕ0) supplied from an external tester, etc., is provided. The self-test circuit inside a chip is operated by the multiplied clock signal (ϕ1). Serial-parallel conversion is performed on the results of determination by the self-test circuit to output the converted results.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is effective when applied to a self-test circuit for testing a memory circuit such as a RAM (random access memory) incorporated in a semiconductor integrated circuit. More particularly, the present invention relates to a self-test circuit for testing a memory circuit in a semiconductor integrated circuit in which an internal memory operates at a high frequency exceeding a processing capability of an external test device.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated and larger in scale, processors and system LSIs (large-scale semiconductor integrated circuits) having a built-in memory circuit such as a RAM.
Is provided. In such a semiconductor integrated circuit, whether the built-in memory circuit is a good product or a defective product is inspected, a redundant circuit is provided in the built-in memory circuit, and a defective memory cell is prepared in advance. It is well known that a defective memory cell is replaced with a replacement memory row or a replacement replacement memory column to repair defective bits and to improve the yield of chips.

[0003]

However, in the test of the memory circuit, the address of the memory cell, data to be written to the memory cell, a control signal for specifying read / write, read data for determining the test result, and the like are used. A means (for example, a device called a tester) for externally supplying or taking out a chip having a built-in memory circuit is required.
When developing an SI and testing it, the tester is a device manufactured using the conventional technology. Therefore, the tester is used to remove the memory circuit in the chip under test that operates at a higher frequency than its processing capability. It is difficult to inspect.

Therefore, for example, there is a method called a built-in self test (BIST) or an array built-in self test (ABIST) for embedding a circuit for realizing a test of a memory circuit in a chip in the chip (Japanese Patent Laid-Open No. H10-163873). No. 6-342040, Japanese Patent No. 2641413). There are various ways of implementing the built-in self-test circuit, but typical ones are a means for generating a test address, a means for generating test data to be written to a memory,
A means for generating an expected value for data read from the memory, a means for comparing the two data, a means for storing an address (failure address) of a memory cell having a mismatch as a result of the comparison, and a means for controlling these Consists of

When a built-in self-test circuit is realized by a tester on a chip under test operating at a high frequency exceeding its processing capability, the following problems can be considered. That is, even if the fault address detected by the built-in self-test circuit is output to the outside of the chip, the failure information output from the chip having a high operating frequency cannot be captured by an external tester having a low processing capability. It is. If a failure is detected by the self-test circuit, if only information indicating the failure is output to the outside, it becomes difficult to analyze the failure that has occurred, and redundancy cannot be relieved.

Accordingly, a circuit (for example, a register) for storing a defective address detected by the built-in self-test circuit
Inside the chip, read it out with an external tester after the test is completed, or temporarily stop the operation of the self-test circuit every time a defect is detected during test execution by the self-test circuit and output the detected defective address to the outside. Conceivable.

However, in a method of providing a circuit such as a register for storing a detected defective address in a chip, there is a restriction that the number of defective addresses cannot be stored in excess of the number of the installed registers. There is a problem that increasing the number of addresses increases circuit overhead. In the method in which the operation of the self-test circuit is temporarily stopped every time a defect is detected by the self-test circuit and a defective address is output to the outside, the test is interrupted each time a defect is detected. There is a problem that the time is greatly increased and the real-time property is impaired, so that accurate defect information cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem in a self-test circuit of a built-in memory incorporated in an ultra-high-speed semiconductor integrated circuit. The present invention provides a circuit for storing a detected defective address, It is an object of the present invention to provide a self-test technique capable of avoiding interruption of the operation of the circuit every time and outputting accurate defect information in real time.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a memory circuit, test pattern generating means for generating an address and data for testing the memory circuit, and comparison determining means for comparing data read from the memory circuit with expected value data for the data. And serial-parallel conversion means for converting a signal indicating a defect output from the comparison and determination means into a parallel signal in accordance with a ratio between the frequency of an internal clock and the frequency of an operation clock of an external test apparatus. did.

More specifically, a multiplying circuit for multiplying a clock signal supplied from an external tester or the like is provided, a self-test circuit in the chip is operated with the multiplied clock signal, and a result of the judgment by the self-test circuit is determined. A means for performing serial-parallel conversion is provided.

According to the above-mentioned means, since the result of the judgment by the self-test circuit is serial-parallel converted and output to the outside, the self-test circuit inside the chip is operated by an external test device operating at a frequency lower than the frequency of the internal clock Can be detected or captured.

Preferably, there is provided a selection means for selecting a signal converted by the serial-parallel conversion means and outputting the signal from a common external terminal. This makes it possible to reduce the number of external terminals for outputting the result of the judgment by the self-test circuit inside the chip.

A memory circuit; test pattern generating means for generating an address and data for testing the memory circuit; and comparison determining means for comparing data read from the memory circuit with expected value data for the data. And latch means for latching a signal indicating a defect output from the comparison and determination means, and controlling the latch timing in the latch means according to the ratio of the frequency of the internal clock to the frequency of the operation clock of the external test device. And latch timing control means for performing the operation.

According to the above-described means, the signal indicating the determination result can be expanded and output to the outside by latching the determination result by the self-test circuit by the latch circuit, so that the signal can be output at a frequency lower than the frequency of the internal clock. The judgment result by the self-test circuit can be detected or taken in by the operating external test device.

Preferably, the latch timing control means comprises a loop counter in which a plurality of flip-flops are connected in a loop, and the loop counter is capable of changing its initial value. Thus, it is possible to change the timing at which the latch means latches the signal indicating the failure output from the comparison and determination means only by changing the initial value of the loop counter.

Preferably, the first signal which can selectively input the fault signal output from the comparing / determining means or the output feedback signal of the last flip-flop of the loop counter to the first flip-flop of the loop counter. A logic circuit for forming a signal obtained by extending the defective signal by taking the logical sum of outputs of a plurality of flip-flops of the loop counter; and a logical signal output from the logic circuit or an output signal from the latch means. A second selecting means for selecting any one of them and outputting the selected signal to an external terminal.

According to the above means, the first selection means selects the fault signal output from the comparison / determination means, and the second selection means selects the output signal of the logic circuit, whereby the memory circuit has a fault. Is detected in a short time,
If there is a defect, the first selection means selects the output feedback signal of the last flip-flop of the loop counter, and the second selection means selects the output signal of the latch means. You will be able to know information.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of one embodiment of a self-test circuit for a memory circuit according to the present invention.

A plurality of memory circuits (RAM) are provided on the semiconductor chip 100 on which the self-test circuit of this embodiment is mounted.
102 is mounted. This embodiment is applied to, for example, a microprocessor chip, and each memory circuit includes, for example, an instruction cache, a data cache, a TAG cache in which a tag address in virtual storage is stored, according to the specifications of each microprocessor. It is used as a memory for storing a conversion table between a logical address and a physical address.

In FIG. 1, reference numeral 101 denotes a control circuit for controlling the entire self-test circuit, and 103 denotes a memory circuit 1
A test pattern generator (APG) 104 for generating addresses and data (including write data and expected value data) required for the test of 02 selects a memory circuit to be tested from a plurality of memory circuits 102 in the chip This is the test target selection circuit to be tested. In this embodiment, the plurality of memory circuits 102 inside the chip are
It is configured to be selected and tested in order according to the selection signal from the controller 04. The order of the test is determined by a command from the control circuit 101.

The control circuit 101 forms a control signal for the test pattern generator 103 and the like in accordance with a diagnostic control signal and a RAM test start signal inputted from the external terminals 141 and 142 and a value of an internal mode register. The generator 103 generates a test row address, a column address, a write enable signal, write data or expected value data, etc., according to the control signal from the control circuit 101 and the value of the mode register.

A selector circuit 106 for switching between a signal from a general logic circuit 105 for realizing the original function of the LSI and a test pattern from the test pattern generator 103 is provided at a stage preceding each memory circuit 102.
At the subsequent stage of 02, a comparison judgment circuit 107 for comparing read data from the memory circuit 102 with expected value data from the test pattern generator 103 is provided. The selector circuit 106 receives a normal logic signal supplied from a general logic circuit such as a processor (CPU) in the chip during a normal operation, and a test address signal A, generated by the pattern generator 103 during a memory test.
The write data Di and the write signal enable WE are selected and supplied to the memory circuit 102 to be tested.

Reference numeral 110 denotes a failure information editing circuit which edits the determination result from the comparison / determination circuit 107 provided corresponding to each test circuit, that is, failure information, and outputs it from a common external terminal 143. And a serial-parallel conversion circuit 111 for converting a determination result signal serially output from the CPU into a parallel signal, and an output selection circuit 112 for outputting an arbitrary result from the converted results. Output OU of serial-parallel conversion circuit 111
Since T0 to OUT3 are selected by the output selection circuit 112 and output from the output terminal 143, the number of external terminals can be reduced.

Further, in this embodiment, there is provided a multiplying circuit 120 for multiplying a clock signal φ0 having a frequency such as 200 MHz supplied from an external tester or the like to a clock signal φ1 such as 800 MHz.
The self test circuit is configured to be operated by the multiplied clock signal φ1. The serial-parallel conversion circuit 111 includes a clock multiplication circuit 120
Is configured to convert a serial signal into a parallel signal in units of 4 bits in accordance with the multiplication number "4" in.

FIG. 2A is a block diagram showing a configuration example of the serial-parallel conversion circuit 111. The serial-parallel conversion circuit 111 includes latch circuits LT1 and LT for latching a failure signal from the comparison determination circuit 107.
2, LT3, LT4, and these latch circuits LT1 to LT
And a loop counter LPC that generates enable signals EN1 to EN4 for permitting latching for each of T4. The loop counter LPC is configured such that four flip-flops FF1 to FF4 are connected in a loop, and a bit set to “1” in this loop circulates according to the clock φ1.

FIG. 2B shows an operation timing waveform of the serial-parallel conversion circuit 111 of FIG. When the high-level failure signal IN is input while the flip-flop FF1 of the loop counter LPC holds “1”, it is taken into the latch circuit LT1 and its output OU is output.
T0 changes to a high level. Then, this state is maintained while the data "1" held in the flip-flop FF1 makes one round of the loop counter LPC, that is, for four cycles. Further, when the cyclic data “1” is held in the third flip-flop FF3, the high-level failure signal I
When N is input, it is taken into the latch circuit LT1, and the output OUT0 changes to high level. And
The state is the data "1" held in the flip-flop FF3.
Is maintained only during one cycle of the loop counter LPC.

In the defect information editing circuit 110 shown in FIG. 1, the outputs OUT0 to OUT3 of the serial-parallel conversion circuit 111 shown in FIG. 2A are selected by the output selection circuit 112 and output from the output terminal 143. Even if the external tester cannot detect a defective signal such as 800 MHz in the chip output from the comparison / decision circuit 107, it does not detect the defective signal as shown in (b) to (e) of FIG. If the outputs OUT0 to OUT3 are doubled, they can be sufficiently detected. However, since the outputs OUT0 to OUT3 of the failure information editing circuit 110 cannot be output at the same time, it is necessary to repeat the same test four times by changing the selection state in the output selection circuit 112.

FIG. 3 is a block diagram showing another embodiment of the defect information editing circuit 110. The failure information editing circuit 110 of this embodiment includes a latch circuit LT0 for latching a failure signal from the comparison determination circuit 107, and an enable signal EN for permitting the latch circuit LT0 to latch.
0, an OR logic gate G0 to which the outputs of the flip-flops FF1 to FF4 of the loop counter LPC are input, and a failure signal from the comparison / decision circuit 107 to the first flip-flop FF1 or the last flip-flop. A selector SEL1 for selecting and supplying one of the feedback signals of the output of the flip-flop FF4;
And a selector SEL2 for selecting either the output of T0 or the output of the flip-flop FF4 of the last stage and outputting it to the output terminal 143.

The loop counter LPC includes four flip-flops FF1 to FF4 connected in a loop, similarly to the circuit of FIG. The difference from the circuit of FIG.
The loop counter LPC of the circuit shown in FIG. 3 is configured so that the initial state can be set from the control circuit 101. However, the initial state set is
One of the four flip-flops FF1 to FF4 is set to “1”, and the other three are set to “0”.

The selection states of the selectors SEL1 and SEL2 are related to each other. When the selector SEL1 selects the defective signal from the comparison / determination circuit 107, the selector SEL2 selects the output of the OR logic gate G0. , The selector SEL1 is the last stage flip-flop FF
4 is selected when the feedback signal of the output of the selector 4 is selected.
L2 selects the output of the latch circuit LT0.

Next, the operation of the embodiment shown in FIG. 3 will be described.
First, the selector SEL1 selects the defective signal from the comparison / determination circuit 107, and the selector SEL2 selects the OR logic gate G0.
The first operation mode for selecting the output is described. In this operation mode, the defect information editing circuit 110 can be regarded as a circuit as shown in FIG. In the circuit of FIG. 4A, the initial state of the loop counter LPC is set to “100”.
When a defect signal as shown in FIG. 4A is input by making “1” circulate as “0”, the output of the latch circuit LT0 becomes as shown in FIG. 4B. Similarly, the initial state of the loop counter LPC is set to “0100”, “00”.
As “10” and “0001” are cycled through “1”, FIG.
The output of the latch circuit LT0 when a defective signal as shown in (a) of FIG. 4B is input is shown in (c), (d), and (d) of FIG.
(E).

As is clear from the comparison between the waveform in FIG. 4B and the waveform in FIG. 2B, both are the same. Therefore,
In the embodiment of FIG. 3, the same test is performed four times with different initial states of the loop counter LPC, so that the same test can be performed without providing the output selection circuit 112 in the failure information editing circuit 110 of the embodiment of FIG. The result can be obtained.

Next, the selector SEL1 selects the feedback signal of the output of the flip-flop FF4 of the last stage and selects the selector S.
A second operation mode in which EL2 selects the output of latch circuit LT0 will be described. In this operation mode, the defect information editing circuit 110 can be regarded as a circuit as shown in FIG. In the circuit of FIG.
F1, FF2 and FF3 are flip-flops constituting the loop counter LPC in the embodiment of FIG.

FIG. 5B shows an operation timing waveform of the circuit of FIG. As shown in this figure, in this circuit, one cycle of the internal clock φ1 as the input signal IN (for example, 2.
5 ns), a failure signal corresponding to 5 nS) is input.
As shown in (b) of (B), it is expanded to four times, that is, 10 ns, and output from the OR logic gate G0. Therefore, even if the external tester cannot detect a defect signal such as 2.5 nS output from the comparison / determination circuit 107, it expands it four times as shown in FIG. 5B (b). A detected output OUT can be sufficiently detected. However, in this case, the timing of the defect signal is ambiguous, and accurate defect position information cannot be known.

As can be inferred from the above description, according to the failure information editing circuit 110 of the embodiment shown in FIG. 3, first, the selector SEL1 selects the feedback signal of the output of the last-stage flip-flop FF4, and the selector SEL2 latches. Circuit LT0
By performing the test in the second operation mode for selecting the output of the first operation mode and performing the test in the first operation mode only when a defect is detected as a result, the total test time can be shortened. Accurate defect information can be obtained.

In the embodiment of FIG. 3, a circuit configured to combine a circuit for detecting a defective signal based on a difference in the timing of the loop counter and a circuit for extending the defective signal four times has been described. A circuit having only the above function may be used. As a result, the circuit scale can be reduced. Further, even for a circuit having only a function of extending a defective signal by four times, a test performed while updating an address in the X direction and a test performed while updating an address in the Y direction are performed, and a result obtained from each test result is obtained. It is possible to know the exact defect position.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the serial-parallel conversion circuit in FIG. 1 is not limited to the configuration shown in FIG. 2 and may be any circuit having the same function.

The defect information editing circuit including the serial-parallel conversion circuit 111 and the output selection circuit 112 according to the first embodiment includes the first selector SEL1 and the OR logic gate according to the second embodiment (FIG. 3). It is also possible to adopt a configuration in which G0 and the second selector SEL2 are combined.

Further, in the above embodiment, the case where the frequency of the internal clock φ1 is four times the frequency of the external clock φ0 has been described, but it may be twice or eight times or more. Further, in the embodiment, the clock multiplication circuit is provided in the chip. However, instead of providing the clock multiplication circuit provided inside the chip, such a high frequency clock may be generated and supplied externally. good.

In the above description, a RAM which is a field of application which mainly uses the invention made by the present inventors as a background
And a case where the present invention is applied to a semiconductor integrated circuit having a built-in RAM test circuit has been described. However, the present invention is not limited to this, and may be applied to a semiconductor integrated circuit having a built-in other memory such as a ROM or EPROM. it can.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the semiconductor integrated circuit provided with the test circuit of the built-in memory according to the present invention, the test of the internal memory circuit can be performed in a relatively short time and the accurate defect information can be obtained in real time. it can. Further, since the self-test circuit of the present invention can be realized by a relatively small-scale circuit, an increase in chip size can be suppressed and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a self-test circuit of a memory circuit according to the present invention.

FIG. 2A is a block diagram illustrating a configuration example of a serial-parallel conversion circuit of a defect information editing circuit, and FIG. 2B is a waveform diagram illustrating timings of input / output signals thereof;

FIG. 3 is a block diagram showing another embodiment of the defect information editing circuit.

FIG. 4A shows a first operation mode in which a selector SEL1 of the failure information editing circuit of FIG. 3 selects a failure signal from a comparison determination circuit 107 and a selector SEL2 selects an output of an OR logic gate G0. FIG. 4B is an equivalent circuit diagram, and FIG.

FIG. 5A is a diagram illustrating a selector SEL1 of the failure information editing circuit of FIG. 3 which selects a feedback signal output from the flip-flop FF4 of the last stage, and a selector SEL2 of the defect information editing circuit illustrated in FIG.
An equivalent circuit diagram in a second operation mode for selecting the output of
(B) is a waveform diagram showing the timing of the input / output signal.

[Explanation of symbols]

 Reference Signs List 101 control circuit 102 memory array 103 test pattern generator (APG) 104 test target selection circuit 105 general logic circuit 106 selector circuit 107 comparison and judgment circuit 110 compressor 105 analyzer 106 compressor 107 test range selection register 110 failure information editing circuit 111 Serial-parallel conversion circuit 112 Output selection circuit 120 Clock multiplication circuit

Continued on the front page (72) Inventor Keiichi Kusoda 3-16-6 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shigeru Nakahara 3-16-6 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Takashi Kiba 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Co., Ltd. (72) Naomi Oshima Tokyo 5-22-1, Kamizuhoncho, Kodaira-shi F-term in Hitachi Ultra-SII Systems Co., Ltd. (Reference) 2G132 AA08 AB01 AG01 AH00 AH07 AK07 AK29 AL09 5B018 GA03 JA21 NA01 QA13 5L106 DD22 DD23 DD25 GG03

Claims (5)

[Claims] 1. A memory circuit, a test pattern generating means for generating an address and data for testing the memory circuit, and a comparison determining means for comparing data read from the memory circuit with expected value data for the data And serial-parallel conversion means for converting a signal indicating a defect output by the comparison / determination means into a parallel signal in accordance with a ratio between a frequency of an internal clock and a frequency of an operation clock of an external test apparatus. A semiconductor integrated circuit characterized by the above-mentioned. 2. The semiconductor integrated circuit according to claim 1, further comprising selection means for selecting a signal converted by said serial-parallel conversion means and outputting the signal from a common external terminal. 3. A memory circuit, test pattern generating means for generating an address and data for testing the memory circuit, and comparison determining means for comparing data read from the memory circuit with expected value data for the data. And latch means for latching a signal indicating a defect output from the comparison and determination means, and controlling the latch timing in the latch means according to the ratio of the frequency of the internal clock to the frequency of the operation clock of the external test device. And a latch timing control unit. 4. The latch timing control means is a loop counter in which a plurality of flip-flops are connected in a loop, and an initial value of the loop counter is changeable. 3. The semiconductor integrated circuit according to claim 1. 5. A first selecting means capable of selectively inputting the fault signal output from the comparing / determining means or the output feedback signal of the last flip-flop of the loop counter to the first flip-flop of the loop counter. A logic circuit for forming a signal obtained by extending the defective signal by taking the logical sum of outputs of a plurality of flip-flops of the loop counter; and outputting either the output signal of the logic circuit or the output signal of the latch means. 5. The semiconductor integrated circuit according to claim 4, further comprising: a second selection unit that can select and output to an external terminal.