JP2824853B2 - Pattern data writing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern data writing method, and more particularly, to a pattern generating apparatus for generating pattern data by accessing a pattern memory according to address information generated from a sequence generator. The present invention relates to a pattern data writing method of a pattern generator capable of partially updating pattern data stored in a pattern memory.

[Prior art] In a conventional IC tester, a separate pattern generator is provided for each test device such as a pattern generator for a memory test or a pattern generator for a logic test. Has an address circuit for accessing a pattern memory called a sequence pattern generator (SQPG) or a sequence generator as hardware for controlling the flow (sequence) of a pattern program.

In a test system for a recent VLSI (VLSI), both the memory and the logic are tested at the same time. Therefore, as shown in FIG. 2, the test pattern generator has a pattern memory 1 for memory and a pattern memory 2 for logic. And these pattern memories 1 and 2 are
Access is made by two SQPGs 3 to generate pattern data in the memory pattern memory 1 and the logic pattern memory 2, respectively, so that pattern data required for the test can be selected.

In such a pattern generator, it is required to generate a pattern independent of all pins for each test step. Each bit generates pattern data corresponding to a pin, and the number of pins and the word of the pattern data are generated. Some have a configuration in which the length corresponds.

[Problem to be Solved] By the way, when testing a semiconductor device such as a logic circuit such as a microprocessor or a gate array with a built-in ROM, an IC tester changes a pattern only for a specific small number of pins. It is required to generate many kinds of patterns. However, in a pattern generation device having a configuration in which the number of pins and the word length of the pattern data correspond to each other, since the pins and the bits of the pattern data are in a correspondence relationship, a pattern that changes only for a specific number of pins is generated. In this case, it is necessary to newly write pattern data including the other pins into the pattern memory. Therefore, it takes time to load new pattern data from the arithmetic processing unit (CPU) into the pattern memory, which reduces test efficiency.

For example, if the pins assigned to a certain pattern memory are 32 pins, and the input / output data bus takes a 32-bit pattern memory as an example, the number of pins to be focused on varies from 2 to 2, There are three, two in reality
Even if it is not necessary to rewrite the entire pattern data by changing the data of ~ 3 bits, 29 to 30 bits out of 32 bits of the data bus generate the same bit data without change, The remaining two or three bits are edited as updated new pattern data, and the new 32-bit pattern data is written to the pattern memory.

In such a process, a re-editing process for rewriting all 32 bits is required of the arithmetic processing unit, and by repeating such writing, the time required for the re-editing work becomes extremely long, and the inspection process efficiency is reduced. Will be.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and an object of the present invention is to provide a pattern data writing method capable of rewriting data of only a bit of interest in a short time.

[Means for Solving the Problems] The configuration of the pattern data writing method according to the present invention for achieving the above object is based on a pattern of n bits (n is an integer of 2 or more) output at once from a pattern memory. A read-back register for storing data, and n-bit pattern data received from the arithmetic processing unit in a bit-parallel manner on a first input side, and n-bit pattern data received from the read-back register on a second input side. In response to a selection control signal for selecting a bit position of one of the first and second input sides in parallel and outputting a bit of the first input side for a digit whose first input side is selected. A bit selector for outputting a second input side bit for a digit whose second input side is selected, and selection control in accordance with selection data set from the arithmetic processing unit And a selection control signal generation circuit for generating a signal, wherein the arithmetic processing unit sets the selection data in which the digit position to be updated of the pattern data is the first input side of the bit selector in the selection control signal generation circuit. The arithmetic processing unit accesses the pattern memory, stores the pattern data to be updated in the readback register, and sends the pattern data in which the bit corresponding to the digit position to be updated is the bit to be updated to the bit selector. Then, the output of the bit selector is written into the pattern memory.

[Operation] As described above, the read-back register connected to the bus line on the output side of the pattern memory and the bit selector for 2-input / 1-output selection that switches in bit units are provided, and the pattern data of the read-back register is converted in bit units. , And the bits are sent from the arithmetic processing unit for the specified digit position, so that the arithmetic processing unit only needs to generate update data only for the bits to be updated, Since the other bits are irrelevant, the process of re-editing the pattern data becomes unnecessary, and the processing time for updating the data in the pattern memory can be shortened.

As a result, the processing time for generating a pattern having a large number of test steps that change only for a specific small number of pins can be reduced, and the entire test processing time can be reduced.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram mainly showing a pattern generator of an IC tester according to an embodiment to which a pattern data writing method of the present invention is applied.

Reference numeral 4 denotes a pattern generation system, which includes a CPU 5 and an SQPG
The 32-bit bit selector 8 and the mask data register 9 are connected to each other via a 32-bit data bus 6, and the CPU 5 further supplies an address bus to the SQPG 7, the mask data register 9, and the pattern memory 11. Connected through 10.

The pattern memory 11 is connected to the bit selector 8 in a bit parallel manner via a write data register 12, and its output side is connected to the data bus 13. The data bus 13 is connected to a readback register 14 that receives 32-bit output pattern data in a bit parallel manner. The output of the readback register 14 is input to the bit selector 8.

The above circuits including the write data register 12 and the readback register 14 receive a write control signal, an enable signal, and a clock signal from the CPU 5 via a control bus, but this control bus is not shown. .

The SQPG 7 has an instruction memory as a main body and a selector, a program counter, and the like, as in the related art. This involves setting an address for accessing the pattern memory 11 in the program counter according to the data content of the instruction memory, thereby accessing the pattern memory 11 and reading the pattern data from the pattern memory 11, and generating the sequence of the generated pattern data. Control.

The pattern memory 11 is accessed by the SQPG 7 and generates, here, 32-bit pattern data from the accessed address in a bit-parallel manner and outputs it via a data bus 13 to a pin electronics circuit (not shown) or the like. To send to. This pattern memory 11 is usually composed of a plurality of memory blocks for storing pattern data. However, for simplicity of explanation, the pattern memory 11 is a pattern memory of only one block.

The bit selector 8 has two inputs (A, B) and one output (Y)
32 selectors 8 _0, 8 ₁ of, ... 8 have a _31, 2 ⁰ to the data bus 6 of the input 32-bit A-side of each selector, 2 ^1, ... in each digit position corresponding to that connected, the B-side inputs are connected so as to correspond to each digit position of the data bus 6 to the pattern data of 32-bit read-back register 14 Part 2 ^0, 2 ^1, ... called. The output Y is connected to the write data register 12 in a bit-parallel manner corresponding to each digit position of 32 bits.

Each selector 8 _0, 8 _1, ... 8 ₃₁ select terminal of (S) respectively receive one bit of the select signal from the mask data register 9 to the respective digit positions corresponding, each selector, for example, select terminal (S) When the bit at the digit position received is "0", the terminal A-Y is connected, and when the bit is "1", the terminal BY is connected. Therefore, 32-bit data is set in the mask data register 9, and data in which "1" is set corresponding to the digit position is set, so that the data at the bit position of "1" in the pattern data is set to the B terminal side. It is possible to select the bit to be updated by connecting the bit data to be updated to the A terminal side with the mask state in which the original bit data is kept as it is.

As a result, the masked bit position is not updated, and the bit becomes the original pattern data.
The bit is output to the terminal side, and the bit received from the data bus 6 is output to the Y terminal on the unmasked side (the bit position set to “0”).

Next, the operation will be described. First, the CPU 5 accesses the mask data register 9 via the address bus 10. Then, in this register, mask data (selection data for selecting a digit position) in which a bit portion not to be updated of the 32-bit data is set to “1” is stored. For example, when updating 3-bit data of 2 ¹ , 2 ² , and 2 ³ and masking the other bits to keep the bits of the original pattern data, “111... 1. Becomes 32-bit data.

Next, the address at which the pattern data to be updated is stored in the pattern memory 11 is designated, and the pattern memory 11 is accessed via the address bus 10. And CPU5
Applies an enable signal to the readback register 14, the pattern data read from the pattern memory 11 is set in the readback register 14.

Next, the CPU 5 determines the digit position where the mask data is “0”, in the above example, the digit of 2 ¹ , 2 ² , and 2 ³ that is “0” of “111... Then, the 32-bit data in which the bit data to be updated are written (there is no need to change the other bits) is sent to the data bus 6.

As a result, this data is stored in the A
Added to terminal. On the other hand, to the B terminal of the bit selector 8, pattern data read from a designated address is added via a readback register 14. Also, each selector 8 _0, 8 _1, digit position to the select terminal of ... 8 ₃₁ is updated as described above, e.g., 2 ^1, 2 ^2, 2 For ³ digit connect the A terminal and the Y terminal Others are supplied with a signal for connecting the B terminal and the Y terminal.

For this reason, only the digit position to be updated becomes a bit transmitted from the CPU 5 to the data bus 6, and the newly updated 32-bit pattern data in which the other bits are the original pattern data is output from the bit selector 8. . At this time, the CPU 5 writes the enable signal to the write data register 12
, The updated pattern data is set in the write data register 12.

Next, the CPU 5 changes the pattern memory 11 from the read state to the write state while keeping the address as it is. Therefore, the updated pattern data is stored in the write data register 12.
And written to the address accessed first.

As described above, the CPU 5 accesses the pattern memory 11 to read the pattern data before the update of the predetermined address and reads back the data in a certain cycle by the read-modify-write control that changes it to the write state at a certain timing. The pattern data before updating is stored in the register 12, and in the next cycle, the updated data is output from the CPU 5 onto the data bus 6 and the updated data is written to the original address in the pattern memory 11 simply by performing write control. Can be.

In this way, only the mask data is set in advance via the data bus 6, and thereafter, the state of the bit selector 8 is determined using this as the select data. The update data can be automatically switched in units of bits and updated, and overwriting can be easily performed without damaging bit data other than the data bits to be updated.

Therefore, the CPU 5 prepares only the bit data of the number to be updated after setting the mask data for the bit to be updated corresponding to the small number of pins of interest, and then sequentially updates the prepared bit data. The data of only the bit of interest can be rewritten simply by inserting it into the bit position to be updated corresponding to the address and outputting it on the data bus 6. That is, unlike the related art, it is not necessary to perform the process of re-editing together with the bit to be updated including the bit that does not update the 32-bit data.

As described above, in the embodiment, the mask data register 32 bits of data are set and each bit is directly added as a control bit to the bit selector.
The data set from the CPU does not need to be 32 bits, and the data to be set in the mask register may be any control data necessary to switch and set the digit position to be selected.

In addition, the selection may specify either the first input side or the second input side. This is because if one of them is determined, the other is eventually determined.

In the embodiment, the update data is stored at the same address without changing the designated address. However, the address for storing the updated pattern data may be a different address.

Further, in the embodiment, the write data register is provided, but this is not always necessary, and the pattern memory may directly receive the update data of the bit selector. Further, the mask data register may be any selection control signal generating circuit that receives such control data and generates a selection control signal capable of selecting a digit position.

In the embodiment, an example in which the pattern data output at one time is 32 bits is described. However, it is needless to say that the pattern data may be n-bit pattern data. The numbers do not have to correspond to all pins.

[Effects of the Invention] As can be understood from the above description, according to the present invention, a read-back register connected to the bus line on the output side of the pattern memory and a two-input-bit switching unit.
Since a bit selector for selecting one output is provided, the pattern data of the read-back register is designated in units of bits, and the designated digit position is set to a bit transmitted from the processing unit. Only needs to generate update data only for the bits to be updated, and the other bits are irrelevant, so that the process of re-editing the pattern data becomes unnecessary, and the data in the pattern memory is The processing time for updating can be shortened. As a result, the processing time for generating a pattern having a large number of test steps that change only for a specific small number of pins can be reduced, and the entire test processing time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram mainly showing a pattern generator of an IC tester according to one embodiment to which a pattern data writing method according to the present invention is applied, and FIG. 2 is a pattern generator of an IC tester for testing a logic and a memory. 3 is a general block diagram of a pattern generation portion in FIG. 1 ... pattern memory for memory, 2 ... pattern memory for logic, 3,7 ... sequence generator (SQPG), 5 ... CPU (arithmetic processing unit), 6,13 ... data bus, 6, 8 …… 32-bit selector, 9
...... Mask data register, 10 ... Address bus, 11 ... Pattern memory, 12 ... Write data register, 14 ... Readback register.

Claims (1)

(57) [Claims] 1. A pattern memory, a sequence generator for sequentially generating address information for accessing the pattern memory and accessing the pattern memory to generate pattern data, and accessing the pattern memory to store a pattern in the pattern memory. A pattern data generation system comprising an arithmetic processing unit for writing data; a readback register for storing n bits (n is an integer of 2 or more) of pattern data output at a time from the pattern memory; Receiving n-bit pattern data from the device on a first input side in a bit-parallel manner, receiving n-bit pattern data from the readback register on a second input side in a bit-parallel manner,
In response to a selection control signal for selecting one of the first and second input-side bit digit positions, the first input-side bit is output for the digit whose first input side is selected, and the second input-side bit is output. A bit selector that outputs a second input-side bit for a digit whose input side is selected, and a selection control signal generation circuit that generates the selection control signal in accordance with selection data set from the arithmetic processing unit The arithmetic processing unit sets the selection data, in which the digit position to be updated of the pattern data is the first input side of the bit selector, in the selection control signal generating circuit, and accesses the pattern memory to update the selection data. The target pattern data is stored in the read back register, and the bit data corresponding to the digit position to be updated is the bit to be updated. Pattern data writing method by sending Kuta and wherein the writing outputs of the bit selector in said pattern memory.