JPH03127232A - Pattern data writing system - Google Patents

Abstract

PURPOSE:To shorten the data update processing time of a pattern memory by designating the pattern data on a read-back register for each bit and turning this data into the bits received from an arithmetic processor in terms of the designated digit position. CONSTITUTION:A pattern generation system 4 consists of a CPU 5, the data buses 6 and 13, a sequence generator SQPG 7, a 32-bit selector 8, a mask data register 9, an address bus 10, a pattern memory 11, a write data register 12, and a read-back register 14. The pattern data on the register 14 is designated for each bit and turned into the bits sent from the CPU 5 in terms of the designated digit position. Thus the CPU 5 is just required to produce the update data for only the bit to be updated. Then such a process that re-edits the pattern data omitted and the processing time is shortened for update of the data on the memory 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pattern data writing method, and more specifically, to a pattern generation device that generates pattern data by accessing a pattern memory according to address information generated from a sequence generator. The present invention relates to a pattern data writing method for a pattern generator that can partially update pattern data stored in a pattern memory.

[Conventional sampling technique] In conventional IC testers, separate pattern generators are provided for each test device, such as a pattern generator for memory testing and a pattern generator for logic testing. Each pattern generator has an address circuit that accesses a pattern memory called a sequence pattern generator (SQPG) or sequence generator as hardware for controlling the flow (sequence) of a pattern program.

In addition, in the recent test systems for VLSI (VLSI), since both memory and logic are tested at the same time, the test pattern generation "AM" is divided into pattern memory 1 for memory and pattern memory 1 for logic, as shown in Figure 2. A pattern memory 2 is provided, and these pattern memories 1.2 are accessed by one 5QPG3 to generate pattern data in the pattern memory 1 for memory and the pattern memory 2 for logic, respectively, and generate the pattern data necessary for the test. Pattern data can be selected.

In such pattern generators, it has become necessary to generate independent patterns for all pins at each test step, and each bit generates pattern data corresponding to a pin, and the number of pins and pattern data l are Some words have a structure that corresponds to the word length.

[Problem to be solved] By the way, when testing semiconductor devices such as microprocessors with built-in ROM and logic circuits such as gate arrays, IC testers change patterns only for a specific decimal number of pins. It is required to generate many types of patterns. However, in a pattern generator configured such that the number of pins corresponds to the word length of the pattern data, a pattern that changes only for a specific decimal number of pins is generated because the pins and the bits of the pattern data correspond. In this case, it is necessary to newly write pattern data including other pins into the pattern memory. Therefore, it takes time to load new pattern data from the arithmetic processing unit (CPU) side to the pattern memory, which reduces test efficiency.

For example, if we take a pattern memory with 32 pins assigned to it and a 32-bit human output data bus, we can focus on the changing pattern and change the number of pins to 2 to 3. 3 bits, and in reality it is not necessary to rewrite the entire pattern data by changing data for 2 to 3 bits, but 29 to 30 bits out of 32 bits of the data bus Generate the same bit data without any changes, edit the remaining 2 to 3 bits as new pattern data, and perform 32 bits.
Write new pattern data of bits to pattern memory.

In such processing, the arithmetic processing unit is required to perform re-editing processing to rewrite all 32 bits, and by repeating such writing, the time required for re-editing work becomes extremely large, and the inspection processing efficiency is reduced. I will do it.

The present invention is intended to solve the problems of the prior art, and it is an object of the present invention to provide a pattern data 3-inclusive method that can rewrite data of only the bits of interest in a short time.

[Means for Solving the Problems] The configuration of the pattern data writing method of the present invention for achieving the f4-Ell purpose is to write n data for one minute (n is an integer of 2 or more) that is output from the pattern memory at a time. A readback register stores pattern data of 1 bits, and a first input side receives pattern data of n bits in parallel from the arithmetic processing unit, and a second input side receives pattern data of n bits from the readback register. bits on the first input side for the selected digit in response to a selection control signal that selects the bit digit position on either the first or second input side. and for the digit selected by the second input side, the second
The circuit is equipped with a bit selector that outputs bits on the input side of , and a selection control signal generation circuit that generates a selection control signal according to selection data set from an arithmetic processing unit. The arithmetic processing unit sets the selection data on the first input side of the bit selector in the selection control signal generation circuit, and the arithmetic processing unit accesses the pattern memory and stores the pattern data to be updated in the readback register. , the pattern data in which the bit corresponding to the digit position to be updated is the bit to be updated is sent to the bit selector, and the output of the bit selector is written into the pattern memory.

[Operation: In this way, a read bank register connected to the pass line on the output side of the pattern memory and a bit selector for selecting the output of the two-person car that switches to the bit it position are provided, and the pattern data of the read back register is read as a pick. H1i(j'
Since the specified digit F is specified by l, the bit to be sent from the arithmetic processing unit is set, so the arithmetic processing unit only needs to generate update data for the bit to be updated. , the remaining other bits are irrelevant, so there is no need for processing to re-edit the pattern data, and the processing time for updating data in the pattern memory can be shortened.

The result is a pattern with a large number of test steps that vary only for a small number of pins.
- The processing time for cases can be shortened, and the overall test processing time can be shortened.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram mainly showing a pattern generating device of an IC tester according to an embodiment of the present invention to which the pattern data writing method of the present invention is applied.

4 is a pattern generation system, which includes a CPU 5;
A bit selector 8 of 7.32 bits of QPG and a mask data register 9 are connected to each other via a data bus 6 of 32 pins. 10.

The pattern memory 11 is connected in bit parallel to the bit selector 8 via the write data register 12, and its output side is connected to the data bus 13. A readback register 14 that receives 32-bit output pattern data in bit parallel is connected to the data bus 13, and the output of the readback register 14 is input to the bit selector 8.

Write data register 12 and readback register 14
Each of the circuits described above receives write control signals, enable signals, clock signals, etc. from the CPU 5 via a control bus, but this control bus is not shown.

The 5QPG7 is mainly composed of an instruction memory as before, and has a built-in selector, program counter, etc. This sets the address for accessing the pattern memory 11 in the program counter according to the data contents of the instruction memory, and then accesses the pattern memory 11 and reads the pattern data from the pattern memory 11, thereby generating a sequence of pattern data. It is something to control.

The pattern memory 11 is accessed by this 5QPG7, and from the accessed address, here, 32
Bit pattern data is transmitted bit-parallel and sent to a pin electronics circuit (not shown) or the like via a data bus 13. The pattern memory 11 is normally composed of a plurality of memory blocks for storing pattern data, but for the sake of simplicity, the pattern memory 11 is shown as having only one block in the figure.

Bit selector 8 is 2-manpower (A, B) - 1iJ4-power (
32 selectors 8o, 8r, . . .
831 and the manpower on the A side of the valley selector is 32.
The 32-bit pattern data of the readback register 14 is connected to the bit data bus 6 in correspondence with each digit position, such as 2021, and so on.
, 21, . . .
are connected corresponding to each digit position. The output Y is connected to the write data register 12 in bit parallel corresponding to each digit position of 32 bits.

Each selector 8o, 8t*...831's select terminal -FC8) receives a 1-bit select signal corresponding to each digit position from the mask data register 9,
For example, each selector connects terminals A and Y when the bit in the digit position received by the select terminal (S) is "0", and connects terminals B and Y when it is '1'. By setting 32-bit data in the mask data register 9 and setting data with "1" set corresponding to that digit position, the data at the bit position of "1" in the pattern data is set as the B terminal side and the original data is set. It is possible to create a masked state in which the bit data remains as it is, and select the bit to be manually input by connecting to the A terminal side for the bit data to be updated.

As a result, the masked bit position is not updated and becomes the original pattern data, which is output to the Y terminal side, and the unmasked side (bit position set to "0") is transferred to the data bus 6. The bit received from is output to the Y terminal.

Next, to explain its operation, first, the CPU 5 accesses the mask data register 9 via the address bus IO. Then, mask data (selection data for selecting a digit position) in which bits of the 32-bit data that are not updated are set to "1" is stored in this register. For example, when updating the 3-bit data of 21.22.23 and masking the other bits to keep the bits of the original pattern data as they are, "111...1...
...tooooi'' 32-bit data.

Next, specify the address in the pattern memory 11 where the pattern data to be updated is stored, and send it to the address bus 10.
The pattern memory 11 is accessed via the . and,
The CPU 5 reads back the enable signal to the register 14.
In addition, the pattern data read from the pattern memory 11 is set in the readback register 14.

Next, the CPU 5 selects the digit position where the mask data is "O", in the previous example, "111...l...1000".
32-bit data in which bit data to be updated is written to digits 21 and 2223, which are "0" out of "1" (other bits can be anything, so do nothing)
is sent to the data bus 6.

As a result, this data is added to the A terminal of each digit of the bit selector 8. On the other hand, pattern data read from a designated address is applied to the B terminal of the bit selector 8 via the readback register 14. Also, each selector is 80v8! , . . . 831 select terminals indicate the digit positions to be updated as described above, for example, 21.
For the digit 22123, connect the A terminal and Y terminal,
The others are supplied with a signal that connects the B terminal and the Y terminal.

Because of this, only the digit position to be updated becomes the bit sent from the CPU 5 to the data bus 6, and the other bits become the original pattern data.Newly updated pattern data of 32 bits is output from the bit selector 8. .

At this time, when the CPU 5 applies an enable signal to the write data register 12, this updated pattern data is set in the write data register 12.

Next, the CPU 5 changes the pattern memory 11 from the read state to the write state, leaving the address unchanged. Therefore, the updated pattern data is supplied from the write data register 12 and written to the first accessed address.

In this way, the CPU 5 accesses the pattern memory 11 to read the pattern data before updating at a predetermined address, and changes it to the write state at a certain timing - the read is done in a certain cycle by the Domo Diff T write control. Store the pattern data before updating in the back register 12, and output the updated data from the CPU 5 onto the data bus 6 in the next cycle; The updated data can be loaded into the pattern memory 11 at the original address simply by performing 3-input control.

In this way, all you have to do is set the mask data in advance via the data bus 6, and then use this as select data to determine the state of the bit selector 8, so from the output data of the pattern memory 11 and the data bus 6 It is possible to automatically switch and update the update data at bit rli, and it is possible to overwrite fTi['- without damaging bit data other than the data bit to be updated.

Therefore, the CPU 5 only needs to set the mask data for the bits to be updated corresponding to a small number of pins of interest, and then prepare only the bit data for the number of bits to be updated to C10. What if I just push the data into the bit position to be updated corresponding to the address to be updated sequentially and output it on the data bus 6? It is possible to rewrite the data of only the bits that are targeted. That is, as before, 32
There is no need to perform ILT editing of the bit data, including the bits that are not updated, along with the bits that are updated.

As explained above, in the embodiment, 32-bit data is set in the mask data register and each bit is added as is to the bit selector as a control bit, but the data set by the CPU must be 32-bit. The data set in the mask register may be any control data necessary to switch and set the digit position to be selected.

Further, selection-it may specify either the first input side or the second input side. This is because if one of them is determined, the other will be determined as a result.

In the embodiment, updated data is stored at the same address without changing the specified address, but the updated pattern data may be stored at a different address.

Further, in the embodiment, a write data register is provided, but this need not necessarily be provided, and the pattern memory may directly receive update data of the bit selector. Further, the mask data register may be any selection control signal generation circuit that receives such control data and generates a selection control signal that allows selection of a digit position.

In the example, an example is given in which the pattern data to be output at - times is 32 bits, but it goes without saying that this can be as long as n bits of pattern data, where n is the device to be tested. It does not have to be a numerical value corresponding to all pins.

[Effects of the Invention] As can be understood from the above description, the present invention has a readback register connected to the pass line on the output side of the pattern memory and a two-person car 1 output selection switch that switches to the bit tri position. A bit selector is provided to specify the pattern data of the readback register bit by bit, and the specified digit position is set as the bit sent from the arithmetic processing unit, so the arithmetic processing unit can
You simply need to generate update data only for the bits to be updated, and the rest of the bits are irrelevant, so there is no need to edit the pattern data, and the data in the pattern memory The time between processing B and 'I for updating can be shortened. As a result, the processing PM time when generating a pattern having a large number of test steps that change only for a specific small number of pins can be shortened, and the overall test processing time can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a block diagram centered on a pattern generation device of an IC tester according to an embodiment to which the three pattern data writing methods of the present invention are applied, and Fig. 2 is a pattern generation device of an IC tester that tests logic and memory. FIG. 2 is a general block diagram of a pattern generation portion of the device. 1... Pattern memory for memory, 2... Pattern memory for logic, 3.7... Sequence generator (SQPG), 5... CPU (
arithmetic processing unit), 6.13... data bus 6.8... 32 focus selector, 9... mask data register, 10... address bus, 1 1... pattern memory, 12... Write data register, 14...Readback register. Patent appearance hole Hitachi Electronics Engineering Co., Ltd.

Claims (1)

[Claims] (1) A pattern memory, a sequence generator that sequentially generates address information to access this pattern memory and accesses this pattern memory to generate pattern data, and a sequence generator that accesses the pattern memory and generates pattern data in the pattern memory. In a pattern data generation system consisting of an arithmetic processing unit for writing, n bits (n
is an integer of 2 or more); a readback register that stores pattern data of n bits from the arithmetic processing device on a first input side in bit parallel;
A second input side receives n bits of pattern data from the readback register in bit parallel, and receives n bits of pattern data from the readback register in bit parallel in response to a selection control signal for selecting a bit digit position on either the first or second input side. a bit selector that outputs a bit on the first input side for a digit for which a first input side is selected, and outputs a bit for a second input side for a digit for which a second input side is selected; and the arithmetic processing device; a selection control signal generation circuit that generates the selection control signal in accordance with selection data set from the bit selector; The selection data to be updated is set in the selection control signal generation circuit, the pattern data to be updated is stored in the readback register by accessing the pattern memory, and the bit corresponding to the digit position to be updated is to be updated. A pattern data writing method characterized in that pattern data, which is a status bit, is sent to the bit selector and an output of the bit selector is written into the pattern memory.