JPH05204596A - Ring buffer device - Google Patents

Abstract

PURPOSE:To execute a ring buffer operation by using only a bank whose memory function is normal, in plural banks obtained by dividing a storage area of a buffer memory. CONSTITUTION:By a CPU 1, a memory check of each bank of a buffer memory 2 is executed, and the head address (pointer) of the bank whose memory function is normal is set to an address holding means 9. A write address generating means 11 and a read address generating means 12 read out cyclically the pointer of the held bank, designate the bank of the buffer memory 2, and generate an address in the bank.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a storage area of a buffer memory into a plurality of unit areas (hereinafter referred to as banks) and cyclically performs a series of processing for reading and writing data in each bank. Regarding a buffer device.

[0002]

2. Description of the Related Art A ring buffer device cyclically generates a buffer memory that stores data, a write address generation circuit that cyclically generates a write address to the buffer memory, and a read address of data in the buffer memory. A read address generation circuit,
A control unit (generally a CPU) for sequentially switching and controlling the outputs of these address generation circuits is provided.

A buffer memory used for storing image data having a relatively large amount of data is usually connected with a plurality of memory ICs (hereinafter referred to as memory chips) to secure a storage capacity. In such a large-capacity buffer memory, its storage area (sum of storage areas of each memory chip) is divided into a plurality of banks, and data is read from and written to each of the divided banks. Although the bank setting is arbitrary, in the following, for convenience of description, one bank corresponds to the storage area of one memory chip.

Therefore, the write address generation circuit sequentially generates the addresses in one bank, and when the generation of the final address in the bank is completed, outputs the bank select signal for selecting the next bank. To do.
By cyclically generating this bank select signal, each bank of the buffer memory is sequentially and repeatedly designated. The same applies to the read address generation circuit. These addresses and bank select signals are sequentially switched by a CPU read / write phase signal and output to the buffer memory.

[0005]

As described above, in a device in which each bank is repeatedly and sequentially selected by each address generation circuit, even if one bank (memory chip) fails for some reason, the failure occurs. As a result of selecting the selected bank, there is a problem that the ring buffer operation is interrupted because data cannot be read or written. Even though the remaining banks are normal, the buffer memory cannot be used as a ring buffer. In addition, it was necessary to replace the memory chip for recovery, so emergency measures could not be taken.

The present invention has been made in view of the above circumstances, and even when an abnormality occurs in a bank of the buffer memory, only the remaining normal banks are selectively used to perform the ring buffer operation. An object is to provide a ring buffer device that can continue.

[0007]

The present invention has the following constitution in order to achieve the above object. That is, according to the present invention, in the ring buffer device that divides the storage area of the buffer memory into a plurality of unit areas (banks) and cyclically reads and writes data to each bank, the memory function of each bank is normal. Means for detecting whether the memory function is normal, a means for holding the address of a bank whose memory function is normal, a means for cyclically reading the address of the held bank, and a data read / write operation for the read address And means for performing.

[0008]

According to the configuration of the present invention, the address of a bank having a normal memory function is held, the address of the bank is cyclically read, and the data is read from or written to the buffer memory. Even if there is a bank with an abnormal function, the ring buffer operation is continued without selecting that bank.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a ring buffer device according to this embodiment. The CPU 1 detects whether the memory function of each bank of the buffer memory 2 (usually, each bank is composed of memory chips) is normal or abnormal (this is called a memory check), and also to the buffer memory 2. It controls the reading and writing of data. A program for memory check is stored in advance in the ROM 3, and data for memory check is stored in advance in the RAM 4. A program in the ROM 3 starts up when the power of the apparatus is turned on, and the CPU 1 performs a memory check of the buffer memory 2 according to the program.

The input data holding unit 5 temporarily holds the data for memory check input to the buffer memory 2,
It is a kind of register that transfers the data to the input buffer 7 according to a control signal from the CPU 1. Similarly, the output data holding unit 6 is configured as a register that temporarily holds the memory check data output from the output buffer 8.

The address holding unit 9 is composed of a plurality of registers for holding the head address of each bank of the buffer memory 2 (hereinafter referred to as a pointer). The clock generation circuit 10 generates a basic clock signal CL for generating an address of the buffer memory 2 and a read / write phase signal RWP for controlling reading and writing of the buffer memory 2, so to speak, data between input / output devices. It can also be said to be an input / output control unit that controls the exchange of data. The pulse width, cycle, etc. of these signals are set by the CPU 1.

The write address generator 11 generates the address signal A in one bank based on the input of the basic clock signal CL, and outputs the bank select signal C _S for selecting each bank and the address holding unit 9. The output enable signal OE for instructing the operation is generated. One of the read address generators 12 also has the same function. These output signals from the address generator 11 and 12 (the address signal A, the bank select signal C _S, output enable signal OE) in response to the read write phase signal RWP from the clock generation circuit 10, whose output It can be switched. In FIG. 1, the read / write phase signal RWP is input to the address generators 11 and 12 for the sake of convenience. However, as shown in FIG. Input to the multiplexer).

The input device 13 and the output device 14 are external devices that input and output data using the buffer memory 2.
The input device 13 transfers the input data to the input buffer 7 when the read / write phase signal RWP is in the writable state, and one output device 14 is in the readable state of the read / write phase signal RWP. The data from the output buffer 8 is taken in. The output operation of the input buffer 7 and the output buffer 8 is also switched depending on the state of the read / write phase signal RWP. That is, the read / write phase signal RWP causes the input buffer 7
Is operating, the read / write phase signal RWP inverted by the inverter 15 is output to the output buffer 8.
Is given, it is inactive. The same applies to the opposite case.

Next, FIG. 3 showing the details of the address holding unit 9, the write address generating unit 11, and the read address generating unit 12.
The basic operation (ring buffer operation) of this ring buffer device will be described with reference to FIG. 3, register RA, registers R1 to R8, register RB
Corresponds to the address holding unit 9, the write counter 111, the coincidence circuit 112, the register P, the decoder 113, and the gate circuit 114 correspond to the write address generation unit 11, and the read counter 121, the coincidence circuit 122, the register P, the decoder 123, The gate circuit 124 corresponds to the read address generation unit 12.

The multiplexers mux1 to mux8 and the multiplexers MUX1 and MUX2 select and output the input signals from the respective constituent circuits of the write address generating section 11 described above when the read / write phase signal RWP is in the write state and read them. In the state, it has a function of selecting and outputting an input signal from each of the constituent circuits of the read address generating unit 12.

First, the storage area of the buffer memory 2 is shown in FIG.
It is assumed that the banks are divided into eight banks B1 to B8 as shown in FIG. The pointer of each bank is represented by 11 bits of A _{0 to} A ₁₀ , the upper 3 bits of A _{8 to} A ₁₀ are address data for designating the bank, and the lower 8 bits of A _{0 to} A ₇ are in one bank. Address data that specifies an address.

The CPU 1 sets the pointer of the bank to start writing in the register RA, and registers R1 to R
The pointer of the bank to be designated next is sequentially set to 8, and the pointer of the bank to start reading is set to the register RB. For example, when the pointers "0000 to 0" of the bank B1 are set in the registers RA and RB, the register R1
The contents of ~ R8 are as follows. Register R1 ... Bank B2 pointer "0010-
0 ”register R2 ... pointer of bank B3“ 0100-
0 "register R3 ... pointer of bank B4" 0110-
0 "register R4 ... pointer of bank B5" 1000 ...
0 ”register R5 ... pointer of bank B6“ 1010
0 ”register R6 ... Pointer“ 1100 to bank B7 ”
0 "Register R7 ... Bank B8 pointer" 1110 "
0 "register R8 ... pointer" 0000 to bank B1 "
0 ”

When writing data to the buffer memory 2, the CPU 1 writes the contents of the register RA into a write counter.
The read / write phase signal RWP of the clock generation circuit 10 is set to the write state. The write counter 111 counts up the content by “1” in response to the input of the basic clock signal CL, outputs the upper 3 bits A _{8 to} A ₁₀ to the decoder 113, and the lower 8 bits A ₀ to.
A ₇ is output to the matching circuit 112, and the multiplexer MU
Output to the address terminal of the buffer memory 2 via X2.

The decoder 113 decodes the upper 3 bits A _{8 to} A ₁₀ binary numbers into decimal numbers (0 to 7) and outputs signals from the data lines corresponding to the respective numbers. Since the read / write phase signal RWP is in the write state,
The eight data lines corresponding to "0 to 7" are connected to the output enable terminals of the registers R1 to R8 via the gate circuit 114 and the buffer memory 2
Connected to the bank select terminal of. That is, the output signal of the decoder 113 becomes the bank select signal C _S for selecting a bank, and the output enable signals OE1 to OE8 of the registers R1 to R8.

To make this more detailed, refer to FIG. When the upper 3 bits A _{8 to} A ₁₀ are “000”,
The signal (active "L") is output only from the data line D0 of the decoder 113, and is not output from the remaining data lines D1 to D7. The output signal from the data line D0 is applied to the memory chip M corresponding to the bank B1 of the buffer memory 2.
1 is selected and output to the gate circuit 114 as the output enable signal OE1 of the register R1.

Similarly, when the upper 3 bits A _{8 to} A ₁₀ are "001", a signal is output only from the data line D1 and the memory chip M1 corresponding to the bank B2 of the buffer memory 2 is selected. At the same time, the output enable signal OE2 of the register R2 is output to the gate circuit 114. When the upper 3 bits A ₈ to A ₁₀ is "111" is output signal only from the data line D7, together with the memory chip M8, which corresponds to the bank B8 of the buffer memory 2 is selected, output enable registers R8 The signal OE8 is output to the gate circuit 114.

The coincidence circuit 112 compares the lower 8 bits A _{0 to} A _{7 with} the data set in the register P. If the contents match, the gate circuit 114
To open. The register P stores the final address value of one bank in advance. In this example, the lower 8
Since bits A _{0 to} A ₇ specify addresses in one bank, 256 = “11111111” is set as the final value. In the following, for convenience, it describes the lower 8 bits A ₀ to A ₇ and the address A ₀ to A _7.

In summary of the above, addresses are generated by the ring buffer device of this embodiment as follows. When the write counter 111 pointer "0000-0" write start of the bank B1 is loaded, the decoder 113 decodes the upper three bits A ₈ to A ₁₀ that,
The bank select signal C _S designating the bank B1 of the buffer memory 2 is output, and the output enable signal OE1 of the register R1 is output to the gate circuit 114. The write counter 111 sequentially writes the input data from the input device 13 of FIG. 1 into the addresses A _{0 to} A ₇ of the bank B 1 which are counted up one by one, and when the addresses A _{0 to} A ₇ reach the final value, the gate is gated. Circuit 114 opens.
Then, the output enable signal OE1 is output to the register R1 and the pointer "0010 to 0" of the bank B2 set in the register R1 is loaded into the write counter 111.

The same applies to the decoder 113 in the bank B2.
The upper 3 bits A _{8 to} A ₁₀ of the pointer “0010 to 0” of No. 2 are decoded to output the bank select signal C _S designating the bank B2 of the buffer memory 2 and to gate the output enable signal OE2 of the register R2. circuit
Output to 114. Addresses A _{0 to} A of the bank B2 that are incremented by 1 by the basic clock signal CL
_{When 7} becomes the final value of bank B2 (= 512), the gate circuit
114 is opened, the output enable signal OE2 is output to the register R2, and the pointer "0100 to 0" of the bank B3 set in the register R2 indicates the write counter 11
Loaded to 1.

As described above, every time the addresses A _{0 to} A ₇ reach the final value of each bank, the pointers of the banks set in the registers R1 to R8 are sequentially read, and the next bank is designated. Click to be done. This operation is continued while the read / write phase signal RWP is in the write state, and the data from the input device 13 is written in the banks B1 to B8.

When the read / write phase signal RWP changes to the read state, the pointer of the read start bank B1 set in the register RB is read by the read counter 12.
Banks B1 to B loaded in sequence 1 and in the same operation as above
8 is selected and the data is read to the output device 14.

The above is the basic operation of the ring buffer device. The operation is similar to that of the conventional technique in that the banks B1 to B8 are cyclically selected, but there is a difference in that the pointers of the banks are set in the registers R1 to R8 and are read out (only in the conventional ring. Banks B1 to B8 are sequentially selected using a counter or the like). Therefore, a specific bank can be selected by appropriately selecting the reading of the registers R1 to R8. That is, by setting only the pointers of the banks having the normal memory function in the registers R1 to R8 and reading them sequentially, the ring buffer operation can be continued even if the abnormal banks exist. This processing will be described below.

First, when the power of this device is turned on,
The program in the ROM 3 shown in FIG. 1 starts up, and the CPU 1 carries out a memory check accordingly. At this time, the pointers of the banks as described above are set in the register RA, the registers R1 to R8, and the register RB, and the ring buffer operation is prepared. Further, it is assumed that the same amount of data as the storage capacity of one bank is stored in advance in the RAM 4 as memory check data. The content of this data is arbitrary.

The CPU 1 sets the data in the RAM 4 in the input data holding unit 5 and sets the cycle of the read / write phase signal RWP (repetition cycle between the write state and the read state) to the clock generation circuit 10. For example, as shown in FIG. 5, the bank select signal C _S is 256
It is set so that the write state and the read state are repeated each time × 8 times of output.

Next, an output enable signal is given to the input data holding section 5, the content is transferred to the input buffer 7, and the basic clock signal CL is supplied from the clock generation circuit 10.
And a read / write phase signal RWP. Then, the pointer of the bank B1 of the write start set in the register RA of FIG. 3 is loaded into the write counter 111. As a result, the above-mentioned ring buffer operation is performed, the banks B1 to B8 are sequentially designated, and the memory check data is written. In the memory check of this example, the same data will be sequentially written in the banks B1 to B8.

When the writing of data to the bank B8 is completed (when the bank select signal C _S is output 256 × 8 times), the read / write phase signal RWP changes to the read state. At this timing, the CPU 1 loads the read counter 121 of the read start bank B1 set in the register RB of FIG. As a result, the ring buffer operation is performed, the banks B1 to B8 are sequentially designated, and the memory check data is read.

The first read data of the bank B1 is temporarily held in the output data holding unit 6, fetched by the CPU 1 and compared with the data in the RAM 4. During this time, the next read data of the bank B2 is temporarily held in the output data holding unit 6. In this way, the CPU1
Compares the data in the RAM 4 with the data in the banks B1 to B8 in order, judges that the memory function of the bank is normal if both data match, and if they do not match, the memory of the bank It is determined that the memory function is abnormal.

Here, it is assumed that it is determined that the memory functions of the banks B2 and B5 are abnormal. CPU1
Changes the contents of register R1 in which the pointer of bank B2 is set and the contents of register R4 in which the pointer of bank B5 is set. That is, the pointer of the bank B3 selected next to the bank B2 is set in the register R1, and the pointer of the bank B6 selected next to the bank B5 is set in the register R4.

Here again, each register R1 to R8
The pointers of the banks that are set are listed below. * Register R1 ... Pointer of bank B3 “0100
~ 0 "register R2 ... Pointer" 0100 "of bank B3
~ 0 "Register R3 ... Pointer" 0110 "of bank B4
~ 0 "* Register R4 ... Bank B6 pointer" 1010 "
~ 0 "Register R5 ... Pointer" 1010 "of bank B6
~ 0 "Register R6 ... Pointer" 1100 "of bank B7
~ 0 "Register R7 ...- Pointer" 1110 "of bank B8
~ 0 "Register R8 ... Pointer" 0000 "of bank B1
~ 0 "

The mark "*" is attached to the register whose contents have been changed in this memory check. In this way, only the bank that is judged to have normal memory function,
It is set in registers R1 to R8.

The above is the memory check process. When the ring buffer operation described above is performed using the contents of the register set in this processing, the result is as follows (see FIGS. 3 and 4).

[0037] In a write operation, the pointer "0000-0" banks B1 to start writing from the register RA to the write counter 111 is loaded, the decoder 113 is a "000" the three most significant bits A ₈ to A ₁₀ 10 It is decoded into a base number and a signal is output from the data line D0 corresponding to "0".

This output signal selects the memory chip M1 corresponding to the bank B1 and is output to the gate circuit 114 as the output enable signal OE1 of the register R1. The write counter 111 is the basic clock signal C
With the generation of L, the addresses A _{0 to} A ₇ are incremented by one. Input device 13 is assigned to this address A _{0 to} A _7.
Input data from is written.

When the addresses A _{0 to} A ₇ reach the final value, the gate circuit 114 is opened to output the output enable signal OE.
1 is output to the register R1 and not the abnormal bank B2,
The pointer of the normal bank B3 set in the register R1 is loaded into the write counter 111.

The same applies to the decoder 113 in the bank B3.
Upper 3 bits of the pointer “0100 to 0” of A _{8 to} A ₁₀ “0
10 "is decoded and the bank B3 of the buffer memory 2 is decoded.
And output the output enable signal OE3 of the register R3 to the gate circuit 114. When the addresses A _{0 to} A ₇ which are counted up one by one by the write counter 111 reach the final value, the gate circuit 114 is opened and the output enable signal OE3 is transferred to the register R.
The pointer "0110-0" of the bank B4 which is output to the register 3 and is set in the register R3 is loaded into the write counter 111.

The decoder 113 decodes the upper 3 bits A _{8 to} A ₁₀ "011" of the pointer of the bank B4 to specify the bank B4 and outputs the output enable signal OE4 of the register R4. As a result, next, the bank B6 set in the register R4 is loaded into the write counter 111. In this way, register R
Output enable signals OE1, OE3, OE4, ... Of 1, R3, R4, R6, R7, R8 are sequentially output, and normal banks B1, B3, B4 ,.
Are selected in order. Note that bank selection is similarly performed when reading data. Therefore, even if there is a bank with an abnormal memory function, the ring buffer operation can be performed without any trouble.

In the above-described embodiments, the bank having the normal memory function is selected by using hardware, but this may be replaced by software. For example,
As a result of the memory check, the pointer of the bank determined to have the normal memory function is stored in the RAM 4,
The pointers stored in the RAM 4 are sequentially loaded into the write counter 111 or the read counter 121 according to the signals from the coincidence circuits 112 and 122. However, due to the access time to the RAM 4, the processing speed is slightly reduced as compared with the embodiment. Also, from the viewpoint of reliability, it is preferable to implement the ring buffer operation by hardware. Other examples for implementation in hardware are shown below as modified examples.

<Modification> In the above-described embodiment, the ring buffer operation is executed by using the write address generation unit 11 and the read address generation unit 12 even when the memory check is performed by the CPU 1. Therefore, the registers R1 to R8
The contents of is updated according to the result of the memory check. This modification omits the change of the contents of the registers R1 to R8. Therefore, the generation of the write address and the generation of the read address in the memory check are performed by the software processing by the CPU 1. This is because it is not necessary to perform the ring buffer operation as described above when the memory is checked.

First, the CPU 1 sequentially generates the addresses of the bank B1. That is, as shown in FIG. 2, addresses "0000-0" to "0001-
1 ”is generated, and the data stored in the RAM 4 is written at this address. After writing, bank B1
Data is read out and compared with the contents of the RAM 4 to perform a memory check. A memory check is similarly performed on the remaining banks B2 to B8.

As in the embodiment, as a result of the memory check,
It is assumed that it is determined that the memory functions of bank B2 and bank B5 are abnormal. The CPU 1 sets only the pointers of the banks having normal memory functions in the registers R1 to R8. That is, the contents of the registers R1 to R8 are as follows. Register R1 ... Pointer “0000 to Bank B1
0 ”register R2 ... pointer of bank B3“ 0100-
0 "register R3 ... pointer of bank B4" 0110-
0 "register R4 ... pointer of bank B6" 1010
0 "register R5 ... pointer of bank B7" 1100-
0 "Register R6 ... Bank B8 pointer" 1110 "
0 ”Register R7 ... Not used Register R8 ... Not used

Only the normal banks are cyclically selected using only the registers R1 to R6 to execute the ring buffer operation. The hardware configuration for that purpose is shown in FIG. It should be noted that only the configuration for generating the write address is shown in this figure, the configuration for generating the read address and the multiplexers mux1 to mux8, which switch between these configurations,
Illustration of the multiplexers MUX1 and MUX2 is omitted.

In FIG. 6, registers R1 to R8, a write counter 111, a coincidence circuit 112, a register P and a decoder 113.
Is a configuration circuit similar to that shown in FIG. However, the decoder 113 uses the upper 3 bits A of the bank pointer.
_It decodes _{8 to} A ₁₀ and outputs only the bank select signal C _S.

First, when the pointer of the bank B1 at the start of writing is loaded into the write counter 111 from the register RA (not shown), the decoder 113 is placed in the upper three positions.
By decoding the "000" bit A ₈ ~A _10, bank B
The bank select signal C _S designating 1 is output to the buffer memory 2.

The addresses A _{0 to} A ₇ counted up one by one by the write counter 111 are supplied to the buffer memory 2 and are also output to the coincidence circuit 112. The final values of the addresses A _{0 to} A ₇ are preset in the register P, and the coincidence circuit 112 outputs a signal when the output value of the write counter 111 reaches the final address value. The operation up to this point is the same as that of the apparatus of the embodiment.

The output signal of the coincidence circuit 112 is given to the shift register 60 and the counter 61. The output of the shift register 60 is connected to the output enable terminals of the registers R1 to R8, and the output is shifted every time a signal is given from the matching circuit 112.

On the other hand, the counter 61 counts the output signal from the matching circuit 112 and outputs the count value to another matching circuit 62 (hereinafter, this matching circuit 62 is referred to as a second matching circuit 62 for distinction). .. The second matching circuit 62 compares the count value with the contents of the register Q and, when they match, clears the shift register 60. Register Q contains CPU1
The number of normal banks is preset by. In this example, "6" is set as the number of normal banks.

Therefore, the address A _{0 of} one bank
When ~ A ₇ reaches the final value, output enable signals OE1 to OE8 are sequentially output from the shift register 60,
The pointers of the banks set in the registers R1 to R8 are sequentially loaded into the write counter 111. And
When the number of output signals of the coincidence circuit 112 becomes “6”, that is, when the output enable signals OE1 to OE6 are output, the second coincidence circuit 62 clears the shift register 60. Subsequently, when a signal is output from the coincidence circuit 112, the shift register 60 outputs the output enable signals OE1 to OE6 again.

In this way, only the output enable signals OE1 to OE6 of the registers R1 to R6 in which the pointers of the normal banks are set are sequentially output, and the output enable signals OE7 and 8 to the unused registers R7 and R8 are output. Is not output and only normal banks are cyclically selected.

[0054]

As is apparent from the above description, according to the ring buffer device of the present invention, the address of a bank having a normal memory function is retained, the address of the bank is cyclically read, and the buffer memory is Since data is read from and written to the ring memory, even if there is a bank having an abnormal memory function in the buffer memory, the ring buffer operation can be continued without selecting that bank. Therefore, it is possible to take a temporary action until the work of restoring the memory function is started, and it is possible to avoid the stop of the ring buffer device and the stop of the device for inputting / outputting data by using this ring buffer device. It is valid.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a ring buffer device according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing a bank of a buffer memory.

FIG. 3 is a block diagram showing a main part of a ring buffer device.

FIG. 4 is a block diagram showing in detail a part thereof.

FIG. 5 is a diagram showing a setting example of a read / write phase signal RWP.

FIG. 6 is a diagram showing a main part of a ring buffer device as a modified example.

[Explanation of symbols]

 1 ... CPU 2 ... Buffer memory 3 ... ROM 4 ... RAM 9 ... Address storage unit 11 ... Write address generation unit 12 ... Read address generation unit

Claims (1)

[Claims] 1. In a ring buffer device in which a storage area of a buffer memory is divided into a plurality of unit areas (banks) and data is read from and written to each bank cyclically, is the memory function of each bank normal? A means to detect whether it is abnormal, a means to hold the address of a bank with a normal memory function, a means to cyclically read the address of the held bank, and a data read / write operation to the read address. A ring buffer device comprising: a means for performing.