JPH01112449A - Speed converting memory device - Google Patents

Abstract

PURPOSE:To prevent data in a memory from being destroyed by sending a dummy a reading address, which is different from a reading address, to the memory when coincidence between a writing address and the reading address is detected. CONSTITUTION:The coincidence between the writing address and the reading address is detected by an address comparing means 10. In a switching means 6, the reading address is sent to a memory 1 as it is when it is detected that the addresses are different in the means 10. On the other hand, when it is detected that the addresses are coincident, a switching is executed so that the dummy reading address, which is different from the reading address, can be sent to the memory 1. Since this dummy reading address is different from the original reading address, difference between the writing address and the reading address is generated in the memory 1 and the data in the memory 1 can be prevented from being destroyed.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to prevent data in the memory from being destroyed even when a write address and a read address match, regarding a speed conversion memory device in which the write clock cycle and the read clock cycle are different. and an address comparison means for comparing the memory write address and the memory read address, and when the address comparison means detects that the above two addresses are different, the read address is sent as is to the memory, while the above both addresses are a switching means for switching to send a dummy read address different from the read address to the memory when a match is detected; and a switching means for switching to send a dummy read address different from the read address to the memory; The apparatus includes a selection means for selecting input data from the memory to be taken out as output data when it is detected that the addresses match.

[Industrial application field]

The present invention relates to a speed conversion memory device in which a write clock period and a read clock period are different.

In general, when a computer retransmits data sent with a clock of 3.4 MHz, for example, with a clock of 3.6 MHz, a speed conversion memory device is used. Therefore, some data is read out using a fast read clock that has a different cycle from the write clock, but since the read clock cycle is faster than the write clock cycle, the address in the memory is read at the same cycle as the clock. While reading, the write address and read address match, and in order to overtake the write address, the data that has been read once in the memory is read again, and if the memory device is left as it is, the data will be lost. The content of the data will be destroyed due to duplication, so
A memory device that can prevent this is required.

[Conventional technology]

FIG. 5 shows a conventional block diagram. An example of this is eg elastic store memory (ES). In the same figure, 1
is a memory, 2 is an input register, and 3 is an output register. In the figure, when writing, input data is stored in the input register 2 by the output clock, then sent to the memory 1, and written to the address specified by the output address by the write clock. Next, during reading, data is read from the address specified by the read address by a read clock with a cycle different from the write clock, and then stored in the output register 3 by a read clock, and taken out as output data. .

Here, the memory 1 is configured as shown in FIG. 6, and the write and read addresses sequentially specify the write and read addresses from OOO to 111.

In this way, data sent with a certain clock can be sent again with a faster clock.

[Problem that the invention seeks to solve]

In such a speed conversion memory device, the write clock is slower than the read clock, so the number of reads increases within the same time, and the write address and read address may coincide midway through and even overtake the read clock. In such a case, if the memory device is left as is, the data in the metering device will be destroyed. However,
The conventional device described above is not configured to prevent such data destruction, and therefore has the problem that accurate data cannot be retrieved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a speed conversion memory device in which data in the memory is not destroyed even when a write address and a read address match.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. In the figure, 1 is memory, 10 is the write address of memory 1 and memory 1
Address comparing means 6 compares the read address of the address with the read address of the address comparing means 10, when the address comparing means 10 detects that the two addresses are different, sends the read address as it is to the memory 1, and when the address comparing means 10 detects that the two addresses match, it sends the read address as it is to the memory 1; The switching means 7 switches to send a dummy read address different from the read address to the memory 1 when the read address is different from the read address. This selection means selects the input data of the memory 1 to be taken out as output data when it is detected that the addresses match.

[Effect]

In the present invention, the address comparing means 10 detects a match between the write address and the read address, and the switching means 6 switches the read address of the memory 1 to a gummy read address different from the original read address, and the memory 1 is automatically read. The data in the memory 1 is prevented from being destroyed by forcibly differentiating the write address and the read address.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the present invention, in which the same components as in FIG. 5 are given the same numbers. In the same figure,
Reference numeral 4 denotes an address/number configuration circuit which compares the write-in address and the read address and outputs an L level signal when they do not match, and an H level signal when they match. Reference numeral 5 designates a flip-flop which outputs each selection signal SEL which is at L level when the output of address/number configuration circuit 4 is always at L level, and at H level when the output is alternately between 1'' level and L level. do. An address comparison means 10 is constituted by the address-number configuration circuit 4 and the flip-flop 5.

6 is an exclusive OR gate (switching means) which outputs the read address as is when the selection signal SEL from the flip-flop 5 is at L level, and outputs a dummy read address with the opposite polarity of the read address when it is at H level. A7 is a selector (selection means) that outputs a selection signal SE
When L is at L level, output data from memory 1 is selected and taken out, while when it is at H level, output data from input register 2 is selected and taken out.

FIG. 3 shows a timing chart when the write address and read address are different, and FIG. 4 shows a timing chart when the two addresses match.

Next, the operation of the apparatus of the present invention will be explained with reference to FIGS. 2 to 4.

The input data (Fig. 3(A), Fig. 4(A)) is stored in the input register 2 by the write clock, then sent to the memory 1, and is written to the write address WA (Fig. 3(C), 4). The data is written to the address specified by the write clock (Figure 3 (B), Figure 4 (B)).
). Here, if the write address WA (FIG. 3(C)) and the read address RA (FIG. 3(D)) are different, an address mismatch is detected in the address-number construction circuit 4, and the L level signal (the 3 (E)) is taken out.

This L level signal sets the selection signal QSEL from the flip 70 tube 5 to the L level (FIG. 3(F)), so that the exclusive OR gate 6 outputs the read address as it is.

In memory 1, this read address RA (Fig. 3 (D))
Data D is read from the address specified by the clock. (FIG. 3(G)) is read out, then stored in the output register 3 by the read clock, and taken out as output data (FIG. 3(H)).

On the other hand, when the write address WA (FIG. 4(C)) and the read address RA (FIG. 4(D)) match, the address-number construction circuit 4 detects the address match, and the H
A signal in which level and L level exist alternately (Fig. 4 (E)
)) is retrieved.

This signal causes the selection signal S from the flip-flop 5 to be
EL is set to H level (Fig. 4 (F)), and as a result,
Exclusive OR gate 6 outputs a gummy read address having the opposite polarity of the read address. That is, when a match between both addresses is detected, the read address of the memory 1 is forcibly switched to the dummy read address.

Since this dummy read address is different from the original read address, the read address and read address in the memory 1 are different, thereby preventing data in the memory from being destroyed. - On the other hand, the H level selection signal SEL from the flip-flop 5 is supplied to the selector 7,
As a result, the selector 7 is switched to output the output data of the input register 2 instead of the output data of the memory 1 (FIG. 4 (G)), and the output data from the output register 3 (FIG. 4 (H)). ) is retrieved as

If the write address and read address match in this way, the write data to memory 1 and the read data from memory 1 are originally equal, so in the above configuration where the read data from memory 1 cannot be retrieved as output data, the memory The input data to 1 is used as output data as it is.

〔Effect of the invention〕

As described above, according to the present invention, when the write address and the read address match, the data in the memory is not destroyed and accurate data can be retrieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 and 4 are timing diagrams when the write address and read address are different and coincide, respectively. 5 is a conventional block diagram, and FIG. 6 is a configuration diagram of the memory 1. In the figure, 1 is a memory, 2 is an input register, 3 is an output register, 4 is an address-number configuration circuit, 5 is a flip 70 tube, 6 is an exclusive OR gate (switching means), and 7 is a selector (selection means). , 10 indicates one stage of address comparison. 1st Embodiment of the present invention Capro 120 7゛Ro-y2 diagram of the 2nd column 5 Figure Memory 1 Lecture-10 Volume 6!

Claims (1)

[Claims] Address comparison means (10) for comparing the write address of the memory (1) and the read address of the memory (1), and the address comparison means (10) are capable of determining whether the two addresses are different. When detected, the read address is sent as is to the memory (1), while the address comparison means (
switching means (6) for switching to send a dummy read address different from the read address to the memory (1) when it is detected in step 10) that the two addresses match;
When the address comparing means (10) detects that the two addresses are different, the output of the memory (1) is taken out as output data, while the address comparing means (10) detects that the two addresses are different. A speed conversion memory device characterized in that it comprises a selection means (7) for selecting the input data of the memory (1) to be taken out as output data when a match is detected.