JPH0136146B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing device that performs arithmetic operations based on data and image data read from a memory, and writes the results of the arithmetic operations back to the memory, and is particularly suitable for performing real-time processing. The present invention relates to an arithmetic processing device.

Arithmetic processing units that perform read-modify-eye-write processing are generally used for image processing, but in this case high-speed processing at television rates is required. Fig. 1 shows an example when used in an image processing device, and according to this, the grayscale image data (multilevel data) or binary image data read out from the image memory 3 is used for feature extraction. Device 2
The feature is extracted for each pixel, and the arithmetic processing unit 1 uses the extracted feature data and image data from the image memory 3 to perform various calculations such as accumulation. By performing various calculations, a grayscale histogram, the area of elements in an image, the center of gravity, etc. can be created or found.

However, in the arithmetic processing device according to the conventional technology, it is difficult to process the TV rate at high speed.
A drawback is that in some cases, the results of calculations cannot be written to memory.

This drawback will be explained in detail with reference to FIGS. 2 and 3 as follows.

That is, FIG. 2 shows a general configuration of an arithmetic processing device according to the prior art, and the feature data in FIG. It's getting old. Specifically, the feature data indicates a label number unique to the pattern. Characteristic data and image data are set in the address register 110 and data register 120, respectively, by the television rate pixel clock signal 151, but the image data is directly given to the arithmetic unit 150. On the other hand, if the feature data accumulation memory 100 as a RAM is accessed using feature data while the R/control signal 157 is in the read mode, the content corresponding to the feature data can be read from the address corresponding to the feature data. The data is read out to the arithmetic unit 150 via the bus 153, memory data register 130, and arithmetic unit input data bus 154, and is designed to be operated on with image data. The calculation result 155 output by the calculation unit 150 is sent to the buffer 14.
0, the memory write-only bus 156, and the memory data bus 153 to write to the address corresponding to the feature data in the feature data accumulation memory 100. Note that reference numeral 158 indicates a read data latch signal output from a memory control circuit (not shown) after the time required for reading has elapsed, and reference numeral 159 indicates a write data sending signal that is output during the time required for data writing. shows.

FIGS. 3a to 3g show the timing of input and output signals in the main parts. According to this, feature data is sequentially set in the address register 110 at the rising edge of the pixel clock signal 151 (see FIG. 3a), but it takes some time to complete setting. That is, after a time _t1 from the rise of the pixel clock signal 151, the characteristic data _ADDR1 is output from the address register 110 as an address signal 152 as shown in FIG. 3b.
As shown in FIG. 3, the contents corresponding to the address are read out onto the memory data bus 153 at a time t ₂ after the output of the address signal 152, and the contents are read out onto the arithmetic unit input data bus 154 after a time t ₃ . As shown in Figures c and d, as can be seen from this, reading takes as much time as t ₁ +t ₂ +t ₃ . Thereafter, the arithmetic operation described above is performed in the arithmetic unit 150, but it takes a lot of time to obtain the result. Figure 3 e shows that the calculation takes a long time _t4 to get the result.
Although it is shown that RESULT _i is obtained, it is clear that the result is further delayed by buffer 140. FIG. 3f shows that the result is output on the memory write-only bus 156 after a time _t5 after the result is obtained, and FIG. 3g shows that the result is output on the memory write-only bus 156. While R/
Although it is shown that the result is written into the feature data accumulation memory 100 by setting the W control signal 157 to the write mode, writing to the feature data accumulation memory 100 is extremely difficult. be. In order to perform writing reliably, the write data must be determined at times t ₆ and t ₇ before and after the point at which the R/control signal 157 changes from write mode to read mode. If writing must be performed within the time T (T; cycle of pixel clock signal 151 (approximately 167 ns)) - (t ₁ + t ₂ + t ₄ + t ₅ ) and the calculation requires a lot of time, write It becomes impossible to guarantee time. In some cases, it becomes impossible to write the calculation results. In order to eliminate such problems, it is possible to use a high-speed computing unit, but
In this case, a new problem arises in that the device cannot be constructed at low cost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an arithmetic processing device that can reliably write data without requiring a high-speed operation unit.

For this purpose, the present invention is arranged so that the reading, calculation and writing are not performed within one period of the pixel clock signal, but are performed during two periods of the pixel clock signal. It is. That is, reading is performed in the first half of one cycle of the pixel clock signal, calculation is performed from the second half of that cycle to the first half of the next cycle, and writing of the calculation result is performed in the second half of the next cycle. Of course, in parallel with the above reading and writing, calculations related to the other two feature data are performed, and writing and reading related to the other two feature data are sequentially performed in parallel with the above calculations. When configured for processing in this manner, data writing can be performed reliably even without the need for a high-speed operation arithmetic unit.

The present invention will be explained below with reference to FIGS. 4 to 9.

First, FIG. 4 shows the overall configuration of the device according to the present invention as functional blocks. According to this, the entire system includes a feature data accumulation memory (section) 100, an address division section 200, an address comparison section 300, an arithmetic section 500, and a data control section 400.
Of these, the feature data accumulation memory 100 is similar to the conventional one, but the R/control signal is the pixel clock signal 151. As a result, the feature data accumulation memory 100 is placed in the read mode during the first half of the clock cycle and in the write mode during the second half of the clock cycle. Further, the address dividing unit 200 takes in feature data that can be updated in synchronization with the pixel clock signal 151, and uses the current feature data as a read address signal in the first half of the clock cycle, and uses the current feature data as the read address signal in the second half of the cycle. Feature data 1
This is for outputting a read address signal related to the immediately preceding feature data as a write address signal. Furthermore, the address comparison unit 300 is provided in consideration of the case where the same feature data is continuously input, and compares the current feature data with the immediately previous one, and converts the calculation result into a feature based on the comparison result. It is designed to control whether or not to input data to the arithmetic unit 500 in place of the read data from the data accumulation memory 100. When different feature data are input sequentially, the calculation results are written to the feature data accumulation memory 100 via the data control unit 400, but when the same feature data are input sequentially, the calculation results are written correctly before the calculation results are obtained. In order to prevent this, when a matching result is obtained, the calculation result is sent to the calculation unit 500 via the data control unit 400.
The image data is returned to the original image data and calculated. Note that the detailed configuration of the above-mentioned components will be described later.

FIGS. 5a and 5b show processing modes according to the prior art and those according to the present invention. As shown 2
Although clock cycles are shown, conventionally, reading, calculation, and writing of characteristic data 1 and 2 are performed within each clock cycle T. However, according to the present invention, reading is performed in the first half of the clock cycle,
The calculation between the read contents and the image data is performed from the second half of the clock cycle to the first half of the next clock cycle. The calculation results are written into the feature data accumulation memory in the second half of the next clock cycle.
The figure shows processing mainly for feature data b, but as can be seen from the figure, the feature is that feature data a and b are also processed in parallel to the processing of feature data b. When processing is performed pixel by pixel in image units as shown in Figure 5b, focusing on the continuity of processing, the calculation time can be set close to the maximum clock cycle. This makes it possible to perform sufficient real-time processing even when using an arithmetic unit with a slow operating speed.

Although the outline of the present invention is as described above, it will be explained in more detail with reference to the drawings starting from FIG. 6 as follows.

That is, FIG. 6 shows a detailed configuration of an example of what is shown in FIG. According to this, the characteristic data as an address signal is shifted by the address division section 200 using the pixel clock signal 151 as a shift pulse. Latch circuit 210, 220
functions as a shift register, but if there is a relationship as shown in the figure, the latch circuit 21
From 0, the address signal 211 of the current feature data is
Further, the address signal 221 of the immediately previous feature data is obtained from the latch circuit 220. Here, when the pixel clock signal 151 controls the selector 230 as a clock pulse with a duty ratio of 50%, the address signal 211 is used in the first half of the clock cycle, and the address signal 221 is used in the second half of the clock cycle to control the feature data accumulation memory 1.
This will be obtained as the address signal 231 for 00. On the other hand, since the R/control signal is the pixel clock signal 151 itself, the feature data accumulation memory 100 is placed in the read mode during the first half of the clock cycle and in the write mode during the second half of the clock cycle. By the way, since the address signal 211 appears again as the address signal 231 in the second half of the next clock cycle, it is basically processed as shown in FIG. 5b. However, an exception is when the same feature data is input continuously. As already mentioned, in such a case, the same address is accessed for reading in the first half of the current clock cycle before the operation result for the content read in the first half of the previous clock cycle has been written. This is because the content read out is the one before the update, and is not the correct one. In order to avoid this problem, an address comparison section is provided, and depending on the comparison result, it is controlled whether or not the calculation result is input to the calculation section.

First, a case in which the same feature data is not input continuously will be described with reference to FIGS. 7a to 7j.

In FIG. 7, a and b represent the pixel clock signal and its inverted signal, and c and d represent the address signal 211,
221 is shown over three clock cycles. If the address signals 211 and 221 change as shown, the address signal 231 will change as shown in e of the figure. If we pay attention to the characteristic data ADDR _i outputted as the address signal 231 in the first half of the clock cycle T _o , the corresponding read data DATA _i is outputted onto the memory data bus 411 and sent to the latch circuit 410 as shown in FIG. It is starting to be retained. A latch signal 51, which is an inverted signal of the pixel clock signal 151, converts the pixel clock signal 151 to an inverter 50.
As shown in FIG. 7g, DATA _i is given to the arithmetic unit 520 from the latter half of the clock period _T0 to the first half of the clock period T0 ₊₁ . be. on the other hand,
Since the image data for DATA _i is latched by the latch circuit 510 by the latch signal 51, DATA _i and the image data are eventually input to the arithmetic unit 520 at the same timing and arithmetic operations are performed. The result of the operation RESULT _i
is the arithmetic unit output bus 5 at the timing shown in FIG. 7h.
21, but if this is latched to the latch circuit 530 by the latch signal 51,
RESULT _i is the clock period as shown in Figure 7 i.
It is held in the latch circuit 530 from the latter half of T o ₊₁ to the first half of clock cycle T _o+2 .

In order for RESULT _i to be reliably latched in the latch circuit 530, RESULT _i must be determined before a time T _sp from the rising edge of the latch signal 51, but the size of the time t _sp is different from that in the case of a TTL element. Even if it is, it will only take several nanoseconds at most, so the calculation can be performed within approximately one clock cycle. RESULT _i held in the latch circuit 530 in this way is sent to the data control unit 400 via the operation result bus 531, but as shown in FIG. Since the data is output onto the memory write-only bus 401 via the memory, it can be written to the address ADDR _i in the feature data accumulation memory 100 with a large margin of time. The above is an explanation of the feature data of ADDR _i , but the situation is exactly the same for other feature data, so no further explanation is required.

Next, a case where the same feature data is input continuously will be explained with reference to FIGS. 8a to 8m. In Fig. 8, a to e correspond to Fig. 7 a to e, respectively, but in this example, the feature data ADDR i is used in the first half of the clock period T _o (not shown), and the feature data ADDR _i is used in the latter half. It is assumed that ADDR _i - ₁ is output as the address signal 231. In this case, if ADDR _i and ADDR _{i+1 are} the same, then the 8th
A comparison result signal related to address matching is obtained as shown in FIG. That is, the address signal 211 in the immediately preceding clock cycle is always sent to the latch circuit 3 by the latch signal 51 as shown in FIG. 8h.
10, and the held address signal 311 is compared with the address signal 231 by a comparator 320. Since what is output as the address signal 231 in the first half of the clock cycle T _o+1 is ADDR _i+1 , a comparison result signal 321 related to address coincidence is obtained in the clock cycle T _o+1 . The comparison result signal 321 is held in the D-type flip-flop 330 for one clock period by the latch signal 51.
31 and inverter 340, the latch circuit 41
0, if you control the buffer 420,
The output of DATA _i+1 from the lattice circuit 410 is prohibited, and instead, RESULT _i is input to the arithmetic unit 520 via the buffer 420. That is, although DATA _i+1 is read out from the feature data accumulation memory 100 as shown in FIG. Figure 8g shows the situation. However, instead, RESULT _i output on the calculation result bus 531 is input to the calculation unit 520 via the buffer 420 and the buffer output bus 413. This results in
A calculation is performed between RESULT _i and the image data, and the calculation result RESULT _i+1 is a buffer of 400
The data is written to the address ADDR _i+1 in the feature data accumulation memory 100 via. Note that FIG. 8 k to l show the calculation results on the calculation result bus 531, buffer output bus 413, and arithmetic unit output bus 521, respectively.

The above is a case where two pieces of the same feature data are consecutive, but it is clear that the same process is performed when three or more pieces of the same feature data are consecutive, and no further explanation is required.

Finally, the detailed structure of the device according to the present invention in another example will be explained with reference to FIG. FIG. 9 shows its configuration, and the only difference in the configuration from that shown in FIG. 6 is the address dividing section 20.
0, and therefore only that part is shown in detail. In the device shown in Figure 6, two types of address signals are switched and outputted using a selector, but in this example, two types of address signals are switched and outputted using a latch circuit with output control. be. That is, the latch circuits 210, 250
are the latch circuits 210 and 2 in FIG.
20, the output from the latch circuit 250 is controlled by the state of the pixel clock signal 151. In this example, the signal is output when the signal is at a low level. What is output thereby is the address signal in the second half of the clock cycle, but the first half is by the latch circuit 240 with output control. The contents latched by the latch circuit 240 are the same as those of the latch circuit 210, but the contents are output while the state of the pixel clock signal 151 is at a high level, that is, when the latch signal 51
only while it is in a low level state. Even when configured in this way, it functions in the same way.

As described above, in the present invention, the read operation from the memory, the write operation to the memory, and the arithmetic operation in the arithmetic unit are performed in parallel. Therefore, in the case of the present invention, it is sufficient to perform calculations within approximately one clock cycle, and there is an effect that data can be written reliably without using a high-speed operation unit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of application of an arithmetic processing device that performs read-modify-eye-write processing to an image processing device, and FIG. 2 and FIG. FIG. 4 is a diagram showing the overall configuration of the arithmetic processing device according to the present invention, and FIGS. Figure 6 is a diagram showing a comparison with that related to Figure 4.
Diagrams showing the configuration shown in the figures in detail, Figures 7a-
8a to 8m are diagrams showing the timing of input/output signals in the main parts thereof, and FIG. 9 is a diagram showing another detailed configuration example of the apparatus according to the present invention. 100...Feature data cumulative memory (part), 200
...address division section, 300...address comparison section, 4
00...Data control unit, 500...Calculation unit.

Claims (1)

[Claims] 1. Read modifier eye write processing in which calculation is performed for each pixel between multivalued or binary image data and data read out from memory, and the result of the calculation is written to the memory. It temporarily holds the address signal corresponding to the input image data at the rate of the pixel clock, and uses the address signal in the first half of the current pixel clock cycle and one pixel clock earlier in the second half of the current pixel clock cycle. There is an address dividing section that outputs the address signal output in the first half of the clock cycle as an address signal related to access, and the address is accessed based on the address signal from the dividing section, and the read mode and write mode are set in the first half and second half of each pixel clock cycle, respectively. and an address comparison unit that compares the address signal output from the address division unit in the first half of the clock cycle one pixel clock ago with the address signal output from the address division unit in the first half of the current pixel clock cycle. and an operation for calculating the image data and data corresponding to the address signal read from the memory section for each pixel, and writing the result of the calculation to the memory in the latter half of the clock cycle one clock later. and a data control unit that causes the calculation result output from the calculation unit to be input to the calculation unit in place of the read data from the memory when the comparison result signal from the address comparison unit is related to a match. An arithmetic processing device characterized by the following configuration.