SU886000A1 - Device for interrupt processing - Google Patents

Description

(54) DEVICE FOR TREATMENT INTERRUPTIONS

The invention relates to the construction of interrupt processing in multiprogram computers and can be used in general-purpose and specialized computers. An interrupt handling device is known, which contains registers, memory blocks, control block, switch 1. A disadvantage of the known device is the high cost of the equipment. The closest in technical essence and the achieved result to the proposed is an interrupt handling device containing an interrupt latch register, program state word registers, control unit, operational and local memory 2. However, in this device for some types of interrupts you cannot To create commands that precede the command that caused the interruption. The purpose of the invention is to expand the functional capabilities of the device by defining the commands preceding the one on which the interruption occurred. sting. The goal is achieved by the fact that the interrupt handling device in DP contains the interrupted latching register, control unit, switch, two program state word registers, main memory unit, main memory address register, main memory information register, local memory unit local memory address register, local memory information register, the device input group is connected to the interrupt latch register information inputs group, the first bit output of the interrupt latch register is It is connected to the first input of the control unit, the first output of the control unit is connected to the input of the main memory unit and the information input of the main memory address register, the second output of the control unit is connected to the first input of the switch, the third output of the control unit is connected to the front side of the internal memory block and with the first information input of the local memory address register, the fourth output of the control unit is connected to the first information inputs of the first and second registers of the program status word, the bit output register The RAM information is connected to the second input of the switch, the first output of the switch is connected to the information input of the RAM information register, the third input of the switch is connected to the discharge output of the local memory information register, the second output of the switch is connected to the second information input of the first word register the state of the program, the first bit of the first register of the word of the state of the program is connected to the fourth input of the switch, the first bit output of the second register of the word of the state of The diagrams are connected to the fifth switch of the switch, the second information input of the second register of the state word of the program is connected to the third output of the switch, the second bit output of the first register of the program state word is connected to the second input of the control unit, the group of inputs of the device is connected to the group of information inputs of the first register program state words, a buffer register, a shift register, a word number counter, a transition flag register, three delay elements, two AND elements and two OR elements, with a group The device inputs are connected to a group of inputs of the first element OR, the output of the first element OR is connected to the first information input of the transition indication register, the second bit output of the register of interrupt latch is connected to the first information input of the shift register, the first output of the control unit is connected to the first input of the first And with the input of the first delay element; the fourth output of the control unit is connected to the second information input of the transition flag register; the second bit output of the second register of the word with one program is connected to the second information input 4 of the shift register, the third bit output of the second register of the program state word is connected to the first information input of the buffer register, the bit output of the buffer register is connected to the information input of the local memory information register, the group of the bit outputs of the register the transition flag is connected to the input group of the second OR element, the bit output of the transition flag register is connected to the third information input of the shift register, the bit output of the register The shift region is connected to the sixth input of the switch, the output of the second element OR is connected to the second input of the first element AND and the first input of the second element AND, the output of the first element AND is connected to the second input of the local memory block, the output of the first delay element is connected to the input of the second element of the delay and with the second input of the second element I, the output of the second element I connected with the input of the counter of the word number, the output of the counter of the number of the word connected with the second information input of the register of the local memory address and with the seventh input of the comm ator, the output of the second delay element is connected to the control input of the shift register, to the second information input of the buffer register and to the input of the third delay element, the output of the third delay element is connected to the third information input of the transition flag register, the first bit output of the register of interruption latch is connected to the third information input buffer register. The block diagram of the device shown in the drawing. The device contains a group of device inputs 1, interrupt latch register 2, control block 3, switch 4, program state word register 5, program state word register 6, main memory block 7, main memory address register 8, operational information register 9 data, local memory block 10, local memory information register 11, local memory register 12 addresses, transition flag register 13, shift register 14, buffer register 15, OR elements 16 and 17, AND 18 element, word 19 counter, elements 20 and 21. delay, the element And 22, the element 23 h Derzhko.

A group of inputs 1 is a logic circuit that detects the occurrence of an interruption condition and generates a signal to set the unit to the corresponding register bit 2. Register 2 stores an interrupt indication in one group or another during the interrupt processing time. The state of this register is analyzed by block 3. By its state, the address is determined by the RAM (SP) for the old and new words of the program state. Block 3 is implemented in firmware and contains a permanent memory, a constant memory address register, constant memory information t erHCTp, an additional permanent memory information register, and microcontrollers.

The device works as follows.

In the selection of commands, the signal Read I9 on from the first output of block 3 pushes nl ttepBM input of the element 18. If the Teuetdie takes the interruption of the previous 1p # | ajzdg to interrupt, turn it is 6vot & the transition command, then in register 13, the first bit is equal to one, then yy. the output of the element OR 17 forms a lsf & a signal, as a result, at the output of the element 18, a signal appears that sends a copy of register 15 to register 11 and writes to block 10.

At this time, the register 15 stores the address of the preceding command and the counter 19 contains the address of the command to be selected. Thus, if the executed command causes a violation of the natural sequence of komatsd, then its address is recorded in block 10 in versus cm4 if there is no entry in block 10

Then the delayed signal from the output of the delay element 20 is passed to the input of the element And 22 and, under appropriate conditions, increases the value of the counter 19 by the unit. The signal from the output of the delay element 20 is fed to the input of the delay element 21. The signal delayed by delay element 21 copies the state of the register counter 6 onto register 15, and also registers the register 14. In register 14, the shift is performed by four bits, while the code of the length of the command from register 6 is shifted to the lower bits; register 13 and a sign of interruption from the register 2.

When selecting a command that received control after a violation of the natural sequence of commands, the command address is memorized as described above.

When executing commands that violate the natural sequence of commands, the unit is set to one unit of the first bit of register 13. When executing transfer commands, as well as teams connected and changing registers 5 and 6, the setting of peS 13 produces signals that are controlled by the register operation 6. Such a construction of the device makes it possible to avoid writing addresses of instruction commands of conditional jumps in cases when the Q jump does not occur. When interrupted, the register 13 is set to the output of the SHSh 16 element.

When the interrupt request signal arrives at the device input, the control unit generates fixed addresses in register 8 according to the type of interrupt, sends the contents of registers 5 and 6 to switch 4, and records 0 information to the RAM memory. After completion of writing the old word of the program state, the control unit organizes sequential reading and writing of the contents of the local memory cells (W) into the fixed OP cells. Then, the register 14 and the counter 19 are written. Finally, a new program word is read from the fixed cells and transferred to the registers 5 and 6 through the switch.

As already noted, when the interrupt command is executed, the interrupt signals through the OR element 16 are set to 1 for the first digit of the register 13. During the entire processing time for the interrupt, the state of the register 15 remains unchanged, the address of the command on which the interrupt occurred is stored. Therefore, when a command is started to be sampled at the address set in register 6, the address of the command that caused the interrupt is written to block 10. After the recording is done, register 15 is filled

Claims (2)

M is the address of the command that received the control, which is recorded in block 10 when selecting the next command. Such a sequence of actions in the processing of an interrupt can be changed if from the output of register 5 to the input of block 3 an indication is received of the mode Interrupt processing. It is set in register 5 when switching to a program for processing software interrupts as well as interrupts from computer control circuits. If there is an indication of the Processing Interrupt memory mode, the state of the local memory cells does not occur in the SP cells. This avoids the corruption of information about the addresses of the transition instructions that are stored in the fixed cells of the SP. Thus, as a result of processing the interrupt, the old status word, the program, the length of the commands immediately preceding the one that caused the crashes, the transition signs, the word number counter defining the address of the last MP cell to which record In addition, if the interruption does not occur in the interrupt processing program, the addresses of the commands that transmitted and received control are recorded in the fixed cells of the SP. Otherwise, this information is recorded only in block 10. The application of the invention allows to expand the functionality of the device by defining the commands preceding the interruption. Claims Interrupt handling device containing an interrupt latch register, control block, switch | two program state word registers, main memory block, main memory address register, main memory information register, local memory block, address register local memory, the local memory information register, the group of inputs of the device is connected to the group of information inputs of the register of fixation of interruptions, the first bit output of the register of fixation of interrupts is connected to the first input the control unit, the first output of the control unit is connected to the input of the RAM unit 08 and the information input of the RAM address register, the second output of the control unit is connected to the switch input, the third output of the control unit is connected to the first input of the local memory unit and the first information input of the local memory address register, the fourth output of the control unit is connected to the first information inputs of the first and second registers of the program state word, the bit output of the information register op The operational memory is connected to the second input of the switch, the first output of the switch is connected to the information input of the memory information register, the third input of the switch is connected to the razor output of the local memory information register, and the third output of the switch is connected to the second information state register , the first bit output of the first register of the program state word is connected to the fourth input of the switch; the first bit output of the second register of the program state word is the second information input of the second register of the program state word is connected to the third switch output, the second bit output of the first register of the program state word is connected to the second input of the control unit, the device input group is connected to the group of information inputs of the first register state of the program, characterized in that, in order to expand the functionality of the device by defining the commands preceding the one on which the interruption occurred, the additional It contains a buffer register, a shift register, a word number counter, a transition flag register, three delay elements, two AND elements and two OR elements, the device input group is connected to the input element group of the first OR element, the output of the first element W1I is connected to the first information input of the register the transition sign, the second bit output of the interrupt register is connected to the first information input of the shift register, the first output of the control unit is connected to the first input of the first element I and to the input of the first element beyond the fourth output of the second register of the program state word is connected to the second information input of the shift register, the third bit output of the second register of the state program word 4y is connected to the first information input the house of the buffer register, the bit output of the buffer register is connected to the information input of the local memory information register, the group of the bit outputs of the register of the transition flag is connected to g the input of the second element OR, the bit output of the transition flag register is connected to the third information input of the shift register, the bit output of the shift register is connected to the sixth input of the switch, the output of the second OR element is connected to the second input of the first AND element and the first input of the second element And, the output of the first element And is connected to the second input of the local memory block, the output of the first delay element is connected to the input of the second delay element and to the second input of the second 010 element And, the output of the second element i And connect It is connected to the input of the word number counter, the output of the word number counter is connected to the second information input of the local memory address register and the seventh input of the switch, the output of the second delay element is connected to the control input of the shift register, to the second information input of the buffer register and to the third element delay, the output of the third delay element is connected to the third information input of the transition flag register; the first bit output of the interrupt latch register is connected to the third information form input House buffer register. Sources of information taken into account in the examination of 1. Electronic computer EU-YuZO.Ed. A.M. Larionov. M., Statistics, 1977, p.57. 2. Kagan B.M., Kanevsky M.M. Digital computers and system. M., Energie, 1974, p.484 (prototype).