SU1541617A1 - Device for debugging microprogram units - Google Patents

Abstract

The invention relates to computing and can be used in devices for microprogram debugging, functional testing and diagnostics of hardware of microprogrammable devices (MPU). The purpose of the invention is to expand the field of application due to the possibility of sharing the memory blocks of the firmware of the debugging device and the firmware block being debugged. The device contains a computer 1, a conjugation block 2, an address register 3, a control block 4, multiplexers 5.8 and 10, a trace memory block 6, a microprogram address address memory block 7, a microprogram initial address memory block 9, a memory block 11 These microprograms, the block of elements And 12. Transforming the virtual address of a microinstruction using the dynamic loading mechanism allows emulating microprograms exceeding the amount of physical memory of the emulator. The address translation block contains an indication of the placement of the firmware in the emulator RAM or in the MPU ROM, which allows placing the debugged part of the firmware in the emulator RAM and using the firmware from the MPU ROM and thereby saving the real-time mode for the firmware that exceeds the RAM capacity of the emulator. 3 il.

Description

The invention relates to computer technology and can be used in debugging devices for micro 20 programs and for verifying the operability and diagnostics of microprocessor device hardware.

The purpose of the invention is the expansion of the field of application due to the possibility of sharing device memory 25, device debugging and debugging firmware

FIG. 1 shows the functions; The opal Q scheme of the debugging device, in FIG. 2 - functional control circuit; Fig. 3 is a functional scheme of an interface with a computer;

The device for debugging (Fig. 1) contains a computer 1, a conjugation block 2, an address register 3, a control block 4, a multiplexer 5, a trace memory block 6, an address translation memory block 7} a multiplexer 8, a memory block 9 ddal firmware addresses, multiplexer 10, microprogram memory block 11, I block 12, device sync input 13, device logical conditions 14, second device information 15 inputs, device second information outputs 16, device mode output 17 , third information inputs 18 devices

va, the output 19 of the device stop sign, the first information inputs 20 of the device, the first information outputs 21 of the device. Positions 22-48 designate the inputs and outputs of the device units.

Interface unit 2 (Fig. 2) contains a decoder 49, a HE 50 element, AND 51-54 elements, registers 55-57, and And 58 and 59 element blocks. The control unit

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(Fig. 3) contains a bus 60 stop signs, a block of elements And 61, a register 62, blocks of elements And 63 and 64, a decoder 65, an element And 66, a trigger 67, an element And 68, a comparison circuit 69, a block 70 of comparison circuits, an element OR 71, trigger 72, element AND 73, counter 74, element AND 75, counter 76, elements AND 77 and OR 78.

The device works as follows.

The debugging device replaces the firmware ROM of the device being debugged with its own RAM and controls the MPU sync generator. The firmware being debugged (or the firmware for debugging the hardware of the MPU) is located in memory block 11. The firmware is loaded by computer 1 byte. For this, the byte address is fed through interface block 2 to address register 3 and then through multiplexer 8 to the address inputs of the block. 11 memories. The control of multiplexer 8 is provided by a signal 36 coming from control unit 4. The signal 27 coming from the control output of block 2 records information into block 11. When the firmware is executed, the address information to block 11 is received through a group of information inputs of the multiplexer 8, which is connected to block 7 of the address translation memory

Consider the operation of block 7 of the memory address conversion memory. Block 7 converts a virtual address into a physical one, since it is intended to have a physical memory of a smaller size than a virtual memory. Virtual and physical addresses have different

Format. Let the virtual address have the following structure: the address bits from the 1st to the Kth provide the addressing inside the page, from K + the 1st to the Nth - number of the virtual memory page. The address conversion memory unit 7 converts only the page numbers, leaving bits 1 through K without changes.

Thus, the physical address has the structure: the address bits from 1 to K provide addressing inside the page, from K + 1-ro to the M-th number of the physical memory page. Address conversion is performed by submitting the virtual page number to the address inputs of the RAM and reading the physical page numbers with the status information from the RAM outputs. The status information contains the following data: the first bit is a sign of the placement of the page (in RAM or in ROM, MPU); the second is a request for servicing and stopping a firmware run for all virtual pages that are not allowed to work, and for pages that are not loaded in device block 11, bits 3 and 3 (M-K + 3) will indicate the number of the physical page . When initialized in block 7, all virtual pages are indicated as unloaded.

Before executing the firmware, the operator is doing the initial memory markup, i.e. rolls the type of each virtual memory page. The type of page determines where this page is located: in RAM, ROM, or prohibited for work. When placing a page in block 11, two options are possible: the page is permanently placed (resident page) or loaded on demand (non-resident page). The memory of the control computer stores the types of virtual pages and their priorities for the loader program. To record the status information and the number of the physical page in the memory address conversion block 7, the computer sets the address to the address register 3, the address is transmitted to the address inputs of the block 7 via multiplexer 5, the control input

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Unit 4 controls the debugging device circuitry. To set up the hardware and software of the MPU, it is necessary to provide control over the execution of the firmware. This debugging device implements the following functions: starting the program from the current or specified address, running the firmware in continuous or step-by-step mode, stopping the execution at the request of the operator, specifying the address, number of executed microcommands, based on physical signals (logical conditions), cycling a certain part of the microprogram. Firmware regatta are derived from a combination of device functions.

The run control (execution) of the microprogram is based on the synchronous generator control of the adjusted MPU (Fig. 3). The output of the And 77 element allows / prohibits the operation of the synchrometer. Control of the firmware run is performed using control register 62. At the inputs of element 77, control signals are received: from the output of the address conversion RAM unit 7 (signal 45), from the output of the trigger 72, which provides step-by-step operation, from the fourth output of the control register 62 the work enable signal from the computer, from the output of the I 73 element, which is the signal for stopping the work from the stop circuitry under conditions (by address, number of microinstructions, physical signals (logical conditions)).

The signal from the fifth output of register 62 to the first input of element 66 controls the enable / disable step-by-step operation of the device. If this signal is set to the logical 1 state, then the sync signal passes through element 66 to the input of the trigger 72, sets the trigger 72 to the MPU synchronous generator prohibiting state (the logical O state) and stops the microprogram execution. If this signal is set to the logical O state, then element 66 prohibits the passage of a sync signal to the thrng30 input.

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Secondly, it is connected to the output 33 of block 3, - ra 72 and a step-by-step stop, if necessary, the information is transmitted via the data bus 28 of the block 2 of the interface with the computer block 1, the signal 35 controls the writing to the block 7.

There is no firmware change. In this control scheme, the functions of stopping the execution of the firmware at a given address, the total 1541617, are implemented.

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Unit 4 controls the debugging device circuitry. To set up the hardware and software of the MPU, it is necessary to provide control over the execution of the firmware. This debugging device implements the following functions: starting the program from the current or specified address, running the firmware in continuous or step-by-step mode, stopping the execution at the request of the operator, specifying the address, number of executed microcommands, based on physical signals (logical conditions), cycling a certain part of the microprogram. Firmware regatta are derived from a combination of device functions.

The run control (execution) of the microprogram is based on the synchronous generator control of the adjusted MPU (Fig. 3). The output element And 77 permits / prohibits the operation of the synchro-5 generator. Control of the firmware run is performed using control register 62. At the inputs of element 77, control signals are received: from the output of the address conversion RAM unit 7 (signal 45), from the output of the trigger 72, which provides step-by-step operation, from the fourth output of the control register 62 the work enable signal from the computer, from the output of the I 73 element, which is the signal for stopping the work from the stop circuitry under conditions (by address, number of microinstructions, physical signals (logical conditions)).

The signal from the fifth output of register 62 to the first input of element 66 controls the enable / disable step-by-step operation of the device. If this signal is set to the logical 1 state, then the sync signal passes through element 66 to the input of the trigger 72, sets the trigger 72 to the MPU synchronous generator prohibiting state (the logical O state) and stops the microprogram execution. If this signal is set to the logical O state, then element 66 prohibits the passage of a sync signal to the input terminal.

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There is no firmware change. This control scheme implements the functions of stopping the execution of the firmware at a given address, the quality of the provided instructions, according to the user's physical signals.

At the initial moment of the firmware execution, the state of the circuit of the CPU being adjusted is indefinite, and stopping conditions may occur that prevent the microprogram from starting. Therefore, to perform the first step, it is necessary to prohibit the operation of the stop circuitry under conditions prior to the appearance of the first clock signal. This provides the trigger 67 of the prohibition of the operation of the stop circuit. The logical signal O from the output of the trigger 67 is fed to the input of the element And 73, prohibiting the passage of the stop signal according to the conditions connected to the second input of the element And 73. The clock signal 13 is fed to

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is connected to the second input of the element And 73. The output of the element And 73 is connected to one of the inputs of the element And 77, which manages the sync generator of the developed MPU. Periodic polling of the blocks 61 and 63 of the control computer device determines the moment and the reason for the stop of the microprogram execution. The computer confirms the stop of the run by switching the signal level 79. Block 61 is used to transfer information from the device to the control computer over the mill 28. Block 64 provides the reading of the firmware address in the computer unit. The decoder 65 is a distributor of read and write gating pulses. On the information inputs 29 decoder 65

the second input of the trigger 67 and set-, the address enters and block 3 connects the trigger 67 to the state of logical 1, allowing the operation of the stop circuit under conditions. The stop function at the specified address is provided by the comparison circuit 69, the first group of inputs of which is connected 25 register 62, where the stop address is specified, and the second group of inputs is connected to bus 15, to which the firmware address is received. The enable / disable signal for stopping a run through the comparison scheme is fed to the first input of element 75. If this signal is set to logical 1, then element 75 passes the t-needle,

neither with the computer unit 1, but the control input of the decoder 65 receives a write or read signal from block 2. The decoder 65 produces signals: 33 - writes to the 3 address register, 35 - writes to the 7 address conversion memory, 38 - records in memory block 9, the initial addresses, 39 - readings from block 6 of the route RAM.

The outputs 34, 36 and 37 of control register 62 are used to switch multiplexers 5, 8 and 10, which provide the transmission of addresses for address conversion memory unit 7, microprogram memory unit 1 and initial firmware address memory unit 9.

from the comparison circuit 69, otherwise it prohibits the passage,

The stop function by the number of microinstructions performed is provided by a counter 74, to the subtracting input of which a clock signal is fed from the developed MPU. The information inputs of the counter 74 are connected to the register 62 and provide the setting of the initial state of the counter.

The comparison circuit unit 70 provides the input to the counter 76, reducing the address

halt the execution of the firmware for the specified signal levels. The first and second groups of information inputs of the comparison circuits of block 70 are connected to a register 62, ensuring the trigger levels and trigger enable signals (mask) are fixed. The third group of inputs is connected directly to the inputs of 14 physical signals (logical conditions).

The outputs of the comparison circuit 69, the counter 74 of the number of microinstructions performed and the block 70 are connected to the inputs of the element OR 78, the output of which

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neither with the computer unit 1, but the control input of the decoder 65 receives a write or read signal from unit 2. The decoder 65 produces signals: 33 - writes to the 3 address register, 35 - writes to the 7 address conversion memory, 38 - writes to memory block 9 is the start of addresses, 39 is read from the track RAM block 6.

The outputs 34, 36 and 37 of control register 62 are used to switch multiplexers 5, 8 and 10, which provide the transmission of addresses for address conversion memory unit 7, microprogram memory unit 1 and initial firmware address memory unit 9.

The counter 76 generates an address for controlling the trace memory block 6. A counter's counting input via an OR 71 clock signal increases the address by one during the execution of each microinstruction. The read signal of memory block 6 is fed to subtract 0

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after each data read. From the output of the decoder 65, signals are generated to restore the contents of counter 76 after reading the trace RAM.

The modes of operation of the device (continuous or step-by-step, with a run from the current or a given address, with a stop at an address or after a certain number of times, with the possibility of continuing to run or looping part of the firmware after stopping) are determined by various combinations of methods of starting and stopping execution

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firmware. Consider the operation of the device in various ways to start and stop the execution of the firmware.

When the firmware is started from the current firmware address, the control program sets the corresponding control register bit 62, and the signal 79 is fed to the inputs of the And 77 cell. If the remaining inputs of the And 77 cell are in the logical 1 state (i.e. with the current firmware address loaded into block 11, the step-by-step execution of microinstructions stop is not set according to the conditions), then the signal from the output of element I 77 arriving at the control inputs of the clock generator of the T1PU being debugged allows it to work. The MPU processor starts to execute micro-instructions. The higher bits of the firmware address (from K + 1-ro to YY), which determine the virtual page number, through multiplexer 5 arrive at the address inputs of the address conversion memory unit 7. From the outputs of block 7, the number of the corresponding physical page is read out and, through multiplexer 8, together with the lower bits (1 to K) of the firmware address providing addressing inside the page, are fed to the address inputs of block 11. If the page to which is addressed, loaded into block 11, then from block 7 to the inputs of elements 4 of block 12, a signal 44 is received, allowing the micro-instruction to be passed to the execution in the debugged MPU.

If during the execution of a microprogram, a page appears in the ROM and MPU, then the signal 44 from the output of block 7, which enters the inputs of block 12, the outputs of block 1 2 are switched to a high-impedance state, i.e. microinstructions are not allowed to pass from block 11 to the debugged MPU, while the debugging MPU receives the signal 17 for enabling the ROM, and the processor of the debugged MPU executes microinstructions placed in the ROM of the debugged MPU.

If during the execution of the firmware a reversal to the forbidden page occurs, then from the output of the block 7, the signal 45 to stop the microprogram run arrives at the element AND 77, the signal from the output of which prohibits the synchronizer of the debugging MPU. One thing

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temporarily, the signal 45 through the interface 2 enters the computer 1 and establishes a request 26 to interrupt the stop processing. The interrupt service program instructs the operator to access a banned memory page.

If during the execution of the firmware a page appears to be loaded, then from the output of block 7 the signal 45 stops the firmware run to the element 77, the signal from the output of which prohibits the operation of the synchronizer of the MPU being debugged. At the same time, the signal 45 through the interface 2 enters the computer and establishes a request to interrupt the stop processing. The interrupt processing program removes the signal 79, prohibiting further firmware execution, checks the cause of the shutdown, determines which of the physical pages is not currently loaded, or if there is none, the least used page is determined by the environment of the non-resident memory pages, its physical value is calculated the address and download are in place of the least used page. The interrupt service program downloads the firmware byte-by-byte. The byte address is fed through computer interface unit 2 to address register 3 and is recorded therein by a signal 33 received from the distributor of the write pulses of the decoder 65. This address then goes to the address inputs of the unit 11 via the multiplexer 8 address A multiplexer input 36 of the output signal of the control register 62, in which the interrupt processing program sets the corresponding bit. A microstructure byte record arriving over a bi-directional data bus 28 of the computer interface unit 2 The data inputs of block 11 are transmitted via a recording signal from the control output of block 2.

Next, the interrupt service program corrects the status of the pages in the address translation memory block 7: the deleted page is marked unloaded, and the physical address is indicated for the newly loaded page. The status of the pages is corrected by the write signal 35 in block 7, coming from the decoder 65.

The new status of the corresponding page arriving via the data bus 28 of the computer interface 2 to the data inputs of block 7 is performed at the address set in the address register 3 and transmitted through multiplexer 5 to the address inputs of block 7.

After this, the interrupt processing program sets the corresponding bit in the register 62 and switches the multiplexer 5 with the help of the signal 34, while the address of the new page is sent to the address inputs of the block 7. Since the corresponding bit in the status of this page is cleared, the signal 45 is removed. Setting the signal 79 leads to the start of the synchro-generator and the continuation of the firmware.

The operation of the device at the start of the firmware from the specified address is similar to the operation at the start from the current address, except that the unconditional jump instruction written in block 11 is preliminarily executed. The control program records the specified start address in the microconstruction of the unconditional jump, sets the address of the microinstruction in register 3 unconditional transition, switches multiplexer 8 to transfer the address from register 3 to the PA address inputs of block 11e, then the emulator goes to step mode and Execute a one mikroinstruktsigo. Further execution of the firmware occurs as when starting from the current address.

In the step-by-step mode of operation of the device, the control program sets the corresponding bit in register 62, and the trigger t 72 is set on the front of the signal 79 from the output of the register 62. The signal 79 and the enable signal from the output of the trigger 72 arrive at the inputs of the And 77 element, enabling the synchro generator MPU.

From the generator of the MPU, the clock signal 13 is fed to the input of the element AND 66. The signal coming from the output of the register 62 to the first input of the element AND 66 and controlling the resolution-prohibition of the step-by-step operation of the emulator is set by the control program to the state of logic I, and Element And 66 skips the sync signal 13 to the trigger trigger 72, setting the trigger 72 to the disabled state.

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you're a sync generator. The signal from the output of the trigger 72 is fed to the input element And 77 and stops the execution of the firmware. If the step mode is not set, i.e. the signal from the fifth output of the register 62 prohibits the passage of the sync signal to the input of the trigger 72 through the element 66, a step-by-step stop does not occur when the microprogram is executed.

This control scheme implements the functions of stopping the execution of the firmware at a given address, the number of executed microinstructions, and the physical signals from the debugged MPU.

To perform the first step, the operation of the stop circuitry is prohibited according to the conditions before the occurrence of the first clock signal. The firmware execution signal 79 by the front sets trigger 67 to disable the stop circuit operation. The signal from the output of the trigger 67 is fed to the input of the element And 73, prohibiting the passage of a stop signal according to the conditions of the element 73 connected to the second input of the element 73. The clock signal 13 is fed to the second input of the trigger 67 and sets it to the state of the logical unit, allowing the element And 73 to pass the signal stop conditional on the output of the element OR 78 to the input element AND 77.

If a stop at a given address is set, then register 62 before starting the firmware is recorded the specified stop address and a bit is set, the signal from the output of which allows the signal from the output of the comparison circuit 69 to pass through the AND 75 element. If during the execution of the firmware it is determined that stop, set in register 63, coincided with the firmware address received via bus 15 from the MPU being debugged, the signal from the output of the comparator 69 through the open elements AND 75, OR 78 and AND 73 enters the input element And 77, si cash output which disables the clock of MPU.

If the stop is set according to the number of microinstructions performed, then before the start of the firmware execution, the register 62 records the specified number of microinstructions to the counter 74. During the execution of the firmware for each clock signal13

At 13, coming from the debugging MFD to the subtracting input of the counter 74, one is subtracted from the specified number. When the contents of the counter are set equal to zero, the signal from the output of the counter 74 through the open elements OR 78 and AND 73 goes to the input of the element AND 77, the signal from the output of which turns off the MPC synchronous generator.

If a stop by a physical signal is set, then before starting the firmware execution, register 62 records the logical level of the signal to be stopped, and sets the bit, the signal from the output of which allows one of the comparison circuits of block 70 to operate.

block 70 establishes that the logical 20 strokes of the debugging device, the second signal level specified in the formation inputs of the register which connects to the 62, coincides with the physical level with the information inputs of the signal unit 14 coming from the debugging route, the first inputs of the element MPU, the signal from the outputs of block 70 through the open elements OR 78 and AND 73 enters the input element And 77, the signal from the output of which disables the synchronous generator of the MPU.

Claims (1)

Invention Formula A device for debugging firmware blocks containing a gateway, an address register, first and second The second block with the first inputs of the comparison circuit and the first information inputs of the third multiplexer, the outputs of which are connected to the address inputs of the address conversion memory block, the outputs of which are connected to the first information inputs of the second multiplexer, the outputs of which are connected with the address inputs of the microprogram memory, the outputs of which are connected to the first inputs of the elements AND of the first block, the second inputs of which are connected to the second output of the address conversion memory block, the third output of which th connected to the output device debugging mode, 35 multiplexers, microprogram memory unit, initial address memory block, trace memory block, the device’s address inputs for connecting to the output outputs of a debugging electronic computer, informational third inputs of which are connected to the first element inputs The keys to the mine data of the debugging computer, the output of the input flag, the output of the output flag and the interrupt input of the device for connection to the control bus of the debugging electronic computer are connected respectively to the information inputs, the first information inputs / outputs, the first and second control inputs the output output of the interface unit, the first information inputs of the debugging device are connected to the first information inputs of the first multiplexer, the outputs of which are It is connected to the address inputs of the memory of initial addresses, the outputs of which are connected to the first 1617 14 formation outputs of the debugging device, characterized in that, in order to expand the application area due to the possibility of sharing the memory blocks of the firmware of the debugging device and the debugging microprogramming unit, the debugging device further comprises a third multiplexer, an address translation memory block, a decoder, a register and the first the fourth blocks of the elements And, the first and second elements of OR, the first to the fifth elements of the AND, the first and second triggers, the first and second counters, the comparison circuit, the block comparison circuits, the outputs of the elements And the first block are connected to the second information points The second block, with the first inputs of the comparison circuit and the first information inputs of the third multiplexer, the outputs of which are connected to the address of the memory block of address conversions, the outputs of which are connected to the first information inputs of the second multiplexer, the outputs of which are connected to the address the inputs of the firmware memory module, the outputs of which are connected to the first inputs of the elements AND of the first block, the second inputs of which are connected to the second output of the address conversion memory block, the third output of which o is connected to the output of the debug device mode, third information inputs of which are connected to the first inputs of the elements And the third block, the outputs of the elements of the second, third and fourth blocks are combined and connected to the information inputs of the register, with the information inputs of the memory of the initial addresses, with the outputs of the memory block of the route, with the information inputs of the microprogram memory, with the information inputs of the address register , with the information inputs of the memory of the memory address and the second inputs-outputs of the interface, the second and third control outputs of which are connected respectively to the recording control input of the mic program memory and with the gate of the decoder, the information inputs of which are connected to the information 15 the outputs of the interface block, the fourth control output of which is connected to the first inputs of the elements of the fourth and second inputs of the elements of the third block, and the first output of the decoder is connected to the subtractive input of the first counter and the trace control input of the memory block whose address inputs connected to the outputs of the first counter, the summing input of which is connected to the output of the first OR element, the first input of which is connected to the first inputs of the first the first and second elements of which are connected by matching the recording of the trace memory block with the installation input to the first trigger and the synchronous input of the debugging device, the inputs of the logical conditions of which are connected to the first information inputs of the block comparison circuits, the second information inputs and the enable inputs of the block comparison circuits are connected respectively to the outputs of the first and second register groups, the outputs of the third group of which are connected to the second information inputs of the comparison circuit whose output is dinene with the first input of the third element And, the second input of which is connected to the first output of the register, from the second to the seventh outputs of the decoder are connected respectively to the control inputs by writing the address register, the address translation unit and the memory of the initial addresses, with the second gcode of the first element OR, with the synchronous input The second counter and the register entry input, the eighth output of the decoder is connected to the second inputs of the AND elements of the second block, the outputs of the fourth register group are connected to the information inputs of the second counter, 20 25 thirty 35 40 with the output of the second trigger and the inverse output of the fifth element AND, the first and second inputs of which are connected respectively to the outputs of the first trigger and the second element OR, the first and second inputs of which are connected respectively to the output of equality to zero of the second counter and the output of the element AND, the remaining inputs of the third the OR element is connected to the outputs of the block comparison circuits, the output of the zero counter of the counter, the outputs of the third and fourth elements AND, and the outputs of the block comparison circuits are combined and connected to the second inputs of the And the fourth, the output of the second element And is connected to the subtracting DtHM input of the second counter, a quarter of the output of the address conversion memory block is connected to the fourth input of the fourth And element and to the third control input of the interface block, the outputs of the address register are connected to the second information part of the first , the second and third multiplexers, the output of the first element And is connected to the installation input of the second trigger. sixteen the second to the sixth register outputs are connected to the control inputs of the first, second and third multiplexers and to the second inputs of the first and second And elements, the seventh output of the register is connected to the first input of the fourth And element and to the synchronous inputs of the first and second registers, whose information inputs are connected respectively to buses logical zero and unit debugging device, the output of the sign of the stop of which is connected to the output of the fourth element And, the second and 0 five 0 five 0 with the output of the second trigger and the inverse output of the fifth element AND, the first and second inputs of which are connected respectively to the outputs of the first trigger and the second element OR, the first and second inputs of which are connected respectively to the output of equality to zero of the second counter and the output of the element AND, the remaining inputs of the third the OR element is connected to the outputs of the block comparison circuits, the output of the zero counter of the counter, the outputs of the third and fourth elements AND, and the outputs of the block comparison circuits are combined and connected to the second inputs of the And the fourth, the output of the second element And is connected to the subtracting DtHM input of the second counter, a quarter of the output of the address conversion memory block is connected to the fourth input of the fourth And element and to the third control input of the interface block, the outputs of the address register are connected to the second information part of the first , the second and third multiplexers, the output of the first element And is connected to the installation input of the second trigger.