SU1275457A1 - Microprogram processor - Google Patents

Abstract

The invention relates to the field of computing and can be used in digital computers with firmware control. The purpose of the invention -: increase speed. The firmware contains a data storage unit, a depotfrater, an address register, an operation unit, a microprogram memory unit, an address generation and call indication unit, a micro-command switch, a micro-command register, a control block, a buffer-memory block, a data switch, a command register, and a switch. The goal is achieved by a specified set of features. (L I 3. p. F-ly, 8 ill. With 1C ate 4i cd vj

Description

The invention relates to computing and can be used in digital computers with firmware control. The aim of the invention is to increase speed. FIG. 1 shows a block diagram of the firmware processor} in FIG. 2 - functional diagram of the buffer memory block; pas figs. 3 shows a block diagram of the formation of the address of microinstructions and the sign of circulation; 4 is a diagram of the operating unit; in fig. 5 is a control block diagram; in fig. 6 shows the format of microcommands in FIG. 7. —the algorithm for the execution of microprograms and the formation of addresses of microcommands; 8, time diagrams of the operation of the microprocessor processor. A microprocessor processor (FIG. Contains a data memory block 1, a decoder 2, an address register 3 containing the high part 4 and the low hour 5, which includes the low bit 6 of the address register, an operational block 7, a microprogram memory block 8, block 9 generating micro-command addresses and access indicia, micro-command switch 10, micro-command register II containing address 12 and operational 13 parts and bit 14 of transition flag, control block 15, buffer memory block 16, data switch 17 and command register 18 containing bit d 19 signs of transition and a switch 20. A processor command code input 21 is connected to the fifth information input of the microcommand address and address indication block 9. The buffer memory block 16 (FIG. 2) contains a memory drive 22 whose width is equal to twice the frequency - block 1 of data memory, so psh from the accumulator 23 senior word and accumulator 24 junior words, switch 25 addresses, first 26, second 27, third 28 and fourth 29 elements And, element OR 30 and element OR 31, Inputs 32 of block 16 are the first synchronization input, input 33 is the information input of the block 16, inputs 34 and 35, respectively, the first and second address inputs of block 16, inputs 36 and 37, respectively, the third and second synchronization inputs of block 6, outputs 38 and 39, respectively, the second and first inputs of block 16, Block 9 forming the microinstruction address and Reversal feature (FIG. 3) contains the micro-command address register 40, consisting of the upper 41 and lower 42 fields of the address, the decoder 43 of the upper part of the micro-commands address, multiplexer node 44, consisting of n groups of 45 OR elements, the HE 46 element, first 47, second 48, third 49, fourth 50 and p one 51 groups of elements AND (n elements AND in a group), the outputs of which are connected to the inputs of the corresponding elements of the groups OR 45, the first inputs of the elements AND AND the first 47, the second 48, the third 49, the fourth and the fifth, 51 groups are connected respectively to the first 52, second 53, third 54, fourth 55 and 56 information inputs of the multiplexer node are the corresponding inputs of block 9. The second inputs of the AND elements of the first 47, second 48, third 49 and fourth 50 groups are connected, respectively, lines 57-60, to the first control input 61 nodes 44 multiplexers, which is The first control input of block 9. The third inputs of elements AND of the fourth group 50 and the second inputs of elements And fifth of group 51 are connected respectively to the second 62 and third 63 control inputs of the node 44 of the multiplexers and are the second and third control inputs of block 9, Input register 40 address microinstructions connected to the outputs of the elements of OR group 45, which are the outputs of the node 44 multiplexers. The output of the register of the microcommand address 40 is connected to the address output 64 of the block 9, the Output 65 of the reference sign of the block 9 is connected to the output of the decoder 43 of the older part of the address of the microcompress. The input element HE 46 is connected to the third control input 63 of the node 44 multiplexers. The output element NOT 46 is connected to the third inputs of the elements And the first 47, the second 48 and the third 49 groups and the fourth inputs of the elements And the fourth group 50, Operational unit 7 (figure 4) contains the node 66 of the first registers, the node 67 of the second registers, the switch 68, an adder 69, an operation feature generating unit 70, a shifter 71, and a data register 72. The output of the daylight register 72 is connected to the first information output 73 of block 7, the second information output 74 of which is connected to the inputs of data register 72, first register node 66, second register register 67, and shifter 71 output. The second input of switch 68 is connected to information input 75 of the block 7 processing. Input 76 of the operation code of block 7 is connected to the control inputs of nodes 66 and 67 of the first and second registers, adder 69, switch 68, shifter 71, data register 72, and operation indication form 70. The output of the operation characteristic generating unit 70 is connected to the output 77 of the operation indication of the operation unit 7. The control unit 15 (Fig. 5) is: holds the clock signal generator 78, the OR element 79, the AND elements 80-84 and the trigger 85. The first output clock signal generator 78 is connected by line phase I to the first input of the element OR 79. The second output of clock signal generator 78 is connected by line 2 to the second input of the element OR 79, first inputs of the AND 82 and 83 elements and line 86 to the sixth 32 and seventh 87 block outputs 15. The third generator output 78 clock signals connect the line is not Phase 3 with the first inputs of the And 80, 81 and 84 elements and with the synchronous input of the trigger 85. The output of the OR element 79 and the outputs of the And 80 and 81 elements are connected, respectively, by lines 88, 89 and 90 to the third output 76 of the block 15. The controllers; addressing signals of nodes 66 and 67 of the first and second registers are received respectively via buses 91 and 92 to the third output 76 of block 15 from the corresponding fields of the operating part 13 of the register of 11 micro-commands received at input 93 of block 15. Control signals by adder 69, by the shifter 71, the switch 68 and the feature generating unit 70 are received respectively via buses 94 and 95 and lines 96 and 97 to the third output 76 of unit 15 of the respective. the fields of the operating part 13 of the register of 11 micro-commands arriving at the input 93 of the block 15. The second inputs of the elements are AND 80 and 81. are connected respectively by lines 98 and 99 to the input 93 of the block 15. The second input of the element And 82 is connected by line 100 to the input 93 and the fifth output 101 of the block 15. The information input of the trigger 85 is connected by a line 102 to the input 93 of the block 15. The second inputs of the elements And 83 and 84 are connected respectively -; with the wires 103 and 104 to the input 93 of the block 15. The output of the element And 82 is connected by a line 105 s the sixth output 32. block 15. The output of the trigger 85 is connected by line 106 to the fourth 107 and sixth 32 outputs block 15. The outputs of the elements 83 and 84 are connected respectively to the second 108 and first 109 outputs of block 15. The control signals from block 9 of the address generation of microcommands and the indication of circulation are received via lines 57-60 to the eighth output 61 of block 15 from the corresponding fields of the operating section 13 register 11 microinstructions, arriving at the input 93 of the block 15. The microprogram processor operates as follows. In the case of a time point, the next micro-command enters the register of the 11 micro-instructions. Its operational part 13 is fed to the input of control unit 15, which generates a set of signals that control the operation of data storage units 1, microprogram memory 8, buffer memory 16, address register 3, operation unit 7, and microcommand address generation unit 9 and reference sign and register 18 commands. The address part 12 of the microcommand enters the input of the block 9 for forming the address of the microinstructions and the sign of circulation, which forms the address of the next microcommand taking into account the signs of the branches received on the condition bus from the processing unit 7. When generating the initial addresses of the microprograms, the code is also supplied to the microinstructions address generation unit 9. The actions of the command word are from the register of 18 commands and the address from the younger part 5 of the register is 3 addresses. Depending on the generated code of the address of the next microcommand, which is analyzed by the block 9 of the addressing of the microcommands: and the sign of the access, the call occurs for block 8. of the microprogrammed packet, or via the second address block for block 16 of the buffer memory. In the peBOM case, the read information is fed to the micro-command register 11 /, from the microprogram memory block 8 through the first information input of the micro-command switch 10 by the inverse value of the signal at the entrance of the micro-command address generation and address sign. In the second case, the micro-command is read from the buffer memory block 16 and is fed to the micro-command register 11 via the second and third information inputs of the switch 10 by the direct value of the signal at the output of the indication of the block 9.

After the microinstruction has been written to the microinstruction register I1 in the operational unit 7 and other units of the microprocessor processor, the specified microcommand operations are executed and the transition sign 14 is analyzed. The state Logical zero of this bit means that the next micro-command will be executed, the address of which is formed in block 9. At the same time, as in the previous case, at the address formed in block 9, the next micro-command is accessed either by block 8 memory, or to block 16 buffer-memory.

The state of the logical unit of the 14th sign of the transition of the register of 11 micro-commands means that the command whose address is specified by the address 12 part of the register of the micro-commands 12 will be executed. In this case, the address of the command from the address part 12 of the micro-command register 11 is transferred via the switch 20 to a specific register of register 66 and 67 allocated for the instruction counter, and in block 9 of the formation of the micro-command address the fixed address of the micro-command common to all commands is sent from input 21 processor. This microinstruction is the first microinstruction of the instruction selection and sets the command to access the memory, whose address is sent to this microinstruction from the instruction counter, located in operation block 7, to the address 3 register. At the input 21, a CTynaqt constant from the processor ping power source, which are sources of zero and single logical signals.

The switch 20 at the zero value of the signal at its control input commutes information from its first information input to its output, and at a single signal value at its control input, information from its second information input. The decoder 2 analyzes the address and, depending on its value, accesses the data memory block 1 or the first address input to the buffer memory block 16. In this connection, the command is counted accordingly either from the output of the data memory block 1 or from the output of the buffer memory block 16 via the switch 17 to the command register 18. The switch 17 is controlled by signals at its first and second control inputs. If there is a single signal at the second control input of switch 17, the latter transmits information from the output of data memory block 1. If there is a zero signal at the second control input of the switch 17, the latter transmits an even or odd Tin from the buffer memory block 16, depending on the signal state at the first control input of the switch 17, determining parity or odd parity of the block 16 of the buffer memory ti

When reading a command from block I. Of data in the bit 19 of the transition flag, a zero is written. The read command is executed under the control of micro-instructions that are stored in block 8 of the firmware memory. When a microcommand is read from microprogram memory block 8, zero is written to bit 14 of the transition flag. At the end of the command, the computed address of the next command is transferred from the operation unit 7 to the address register 3. Then, the bit is analyzed by the control signal from control block I5 in block 9. d 19 signs of transition. The state Logical .nol of this bit means that the next command will be executed, the address of which is located on the register of 3 addresses. In this case, in block 9, the address of the first micro-command of the sample is received, coming from the address part 12 of the register of 11 micro-commands. The first micro7 sampling command is then executed to set the memory to be recalled for the instruction. After that, the command is sampled and tested as in the previous case. When executing the command, if the current microcommand specifies the need to request data or an ordinary command word, which is determined by control unit 15, the address from the corresponding register of the operational unit 7 is fed to the address register 3 and then to the decimator 2, which, depending on the value of the address, allows access to the data block 1 or the first address input to the buffer memory block 16 Through the switch 17, the read information is received t to the command register 18, if the next command word is read, or to the operation unit 7, if the data is being read under the control of the control unit 15. The state of the logical unit of bit 19 of the transition flag analyzed by the control signal from the control unit 15 at the end of the command execution means that the next one will be executed by a micro-instruction equivalent to a command or group of commands. In this case, the address of the micro-command is transferred from the register 3 adjpeca to the block 9 of the formation of the address of the micro-commands and the sign of the call. During the execution of this microcommand, bit 14 of the transition flag is analyzed, and the operation of the microprocessor processor occurs in a similar case. Thus, in block I of the data memory is stored arrays of data and programs of the basic command system. The firmware of the basic system of commands stores block 8 of firmware memory. The buffer memory block 16 contains both data and programs as well as microprograms containing one or some set of microinstructions designed to accelerate the execution of a certain algorithm. The buffer memory block 16 has a common addressing system both with block 1 of the data memory and with unit 8 firmware. When accessing the first address input, the buffer memory block 16 is an extension of the address space of the data memory block 1, and when accessing the second address input, continues the address space 57 of the microprogram memory block 8. At that, the firmware download, like any other information In-block 16 of the buffer memory is performed when accessing the first address input. Since the volume of the buffer storage unit 16 is small compared with the total data storage capacity, it can be made as a semipro vodal storage device by its high speed, equal to the speed of the microprogram memory 8. When accessing the second address input from the buffer memory block I6, a double word is read, which allows you to select the microcommand width and microprogram memory block 8, which is equal to twice the data memory block 1. The buffer memory block 16 (FIG. 2) can operate in three modes: the mode of recording data, commands, or micro-instructions; reading mode data or commands; micro-command reading mode, Buffer memory block 16 in write mode is possible only at the first address input 34 in case decoder 2 determines that the memory address belongs to the buffer memory block 16. At the same time, the unit signal level from the output of the decimator 2 is supplied to the third synchronization input 36 of the buffer memory block 16, allowing the address from the first address input 34 of the block 16 to pass through the switch 25 to the input of the accumulator 22 and pass the memory access signal (read or write) arriving from the sixth output of the control unit 15 to the first input 32 of the synchronization block 16 and then through elements 28 and OR 31 to the sample input of the accumulator 22. The recording signal then passes from the sixth output of the control unit 15 to the first input 32 of the synchronization block a 16. through the element AND 26 to the input of the write strobe of the accumulator 24 low word or through the element AND 27 to the input of the record strobe of the accumulator 23 high word, depending on the parity of the address received from the control output of the switch 25. At its single value, the element And 26, and at zero - element 27. Thus, if there is a recording signal, if the specified address belongs to the buffer memory block 16, information from information input 33 is recorded at the address specified at the first address input J, and the recording is For in the words of the older drive 23, Peabo in the drive 24 of the low word, depending on the discharge of parity address.

The operation of block 16 in the mode of reading data or commands is as follows. In case the decoder 2 determines that the memory address belongs to block 16, the unit signal level at the third synchronization input 36 of block 16 resolves the address from the first address input 34 of block 16 through switch 25 to the input of accumulator 22, and also allows passing the circulation signal from the first synchronization input 32 of block 16 through elements AND 28 and OR 31 to sample input of accumulator 22. At outputs 38 and 39 of accumulator -22, read information appears.

The read mode of the micro-instructions from the buffer memory block 16 is executed when the decoder 43 of the block 9 determines that the micro-command address formed on register 40 belongs to the buffer memory block 16. At the same time, the unit signal level from the output 65 of the decoder 43 enters the second synchronization input 37 of the block 16, allowing the address of the microinstruction to pass from the second address input 35 of the block 16 through the switch 25 to the input of the accumulator 22 and passing the signal of the selection of microcommands passing from the sixth output of the block 15. control to the first input 32 of synchronization of the block 16 and further through the element AND 29 and OR 31 to the input of the sample of the accumulator 22i. At the outputs 38 and 39 of the accumulator 22, a read-out microinstruction appears,

The block of formation of the address of microinstructions and the sign of reversal (Fig. 3) works as follows.

Under control of the signals at the control inputs 61-63, the poop (the receipt of the micro-command address in the micro-register register 40 via the group of 45 OR elements from the second 53, third 54, fourth 55 and fifth 56 information inputs or through the first 52 and third 54 information inputs, the Single signal level at the third control input 63 allows the formation of the address of micro-commands from the fifth information input 56, prohibiting at the same time (-the address from the other directions through the element NOT 46 ff; the descriptor 43 implements a content analysis of the high part 41 of microinstruction address register 40 and if it corresponds to the address belonging to the block buffer memory 16, the unit generates a signal on output 65 feature handling, C vschaets address output 64 the contents of register 40 of microinstruction addresses.

Operational unit 7 (Fig. 4) works as follows.

Depending on the execution of the microcommand, under the influence of control signals at the input 76 of the operation code, the block performs arithmetic operations on the adder 69 on one or two operands coming from nodes 66 and 67 of the first and second registers or from information input 75, produces signs of the result in the feature generation unit 70, shifts the result of the arithmetic logic operation on the shifter 71, writes the result of the operation to the nodes 66 and 67 of the first and second registers, or to the data register 72, the result of operations It is also outputted via the second information output 74 of block 7 to the address register 3. In the microcommands for the transition to the software control level (which has a unit transition time, 14), the register of nodes 66 and 67 is the command counter, and the remaining nodes (switch 68, adder 69, shifter 71) are configured from input 76 of the operation code so as to pass information from the information input 75 of block 7 through the switch 68, the adder 69 and the shifter 71 to the input of the nodes 66 and 67 to record it. From the first information output 73 of block 7, the contents of the data register 72 are output, and from the output 77, the sign of the result of the operation - the signs of the result of the operation,

Claims (2)

The control unit 15 (FIG. 5) controls the operation of other processor units. A clock signal generator 78 synchronizes the proposed device. At the output of the element OR 79, a sampling strobe of the nodes 66 and 67 of the first and second registers is generated. The strobe entry in these registers on line 89 is generated at the output of the element And 80 in the presence of an OXY level signal on line 98 and the clock signal. Phase 3 .. At the output of the element And 81, a page is written to write data register 72 when there is a high signal level line 99 and the occurrence of the sync signal Phase 3 At the output of the element And 82 you generate a signal to write to block 6 of the buffer memory in the presence of a high level signal on the line 100 and the appearance of the signal of the phase 2. At the output of the element And 83, a strobe is written in 3 addresses if you have Low signal level on line 10 and the appearance of a clock signal Phase 2. At the output of the element I 84, you produce strobe writing to the command register 18 in the presence of a high signal level on line 104 and the occurrence of a clock signal. Phase 3. At the output of a trigger 85, a memory access signal is generated in the presence of a high signal level on the line 102 and a synchronization signal. Phase 3. The purpose of the micro-command format fields (Fig. 6) is as follows. Field P1 defines the address of the register of the node 66 of the first registers, field P2 - the function of the adder 69. The field PZ defines the entry in the data register 72, the field P4 defines the entry in the register 3 addresses. Field P5 defines micro-operations for accessing the memory. Field A6 controls the switch 68. Field A8 allows the analysis of bit 19 of the switch register 18 command. Field P9 defines the entry in the register of 18 commands. Field P10 specifies the address of the register of the node 67 of the second registers, field P11 - the type of shift on the shifter 71. Field P12 defines the record of signs in node 70. Field P13 specifies the address part 12 of the microcommand register 11, field P14 - bit 14 of the register transition sign 1 microinstructions. Timing diagrams (Fig. 8) and the algorithm for the formation of addresses and the execution of microprograms (Fig. 7) IL1 illustrate the execution of a microinstruction sequence — a microinstruction command. FIG. 7 the following abbreviations are accepted: ICE - micro-command with the number O, MK (N + I) - micro-command with the number (N + I) RAM - register of the micro-command SSC - command counter J RK - command register; RA - register. Address. In the proposed microprocessor processor, the user can access the microprogram microprogram level of control, and the time spent on switching from one level of control to another is reduced. The possibility of a fast transition from one control level to another allows the flexibility to use the advantages of both control levels at different stages of the algorithm, and the ability to replace a command or several commands with an equivalent micro-command leads to an increase in the speed of the device. The use of microprograms in the body of work and level programs significantly improves system performance due to the absence of sampling cycles, decoding of commands and modification of the command counter, high operational density of microinstructions, which allows several operations to be performed in parallel, in the proposed technical solution, one microcommand can be executed operations (transfer, arithmetic operation, shift, memory access, setting signs and checking conditions), as well as the possibility of branch-organization group. The proposed microprocessor processor provides the programmer with an additional command language of ef-. The effective language of microinstructions provides a simple mechanism for moving from one language to another. Claim 1. A microprogram processor comprising a data storage unit, a decoder, an address register, an operation block, a microprogram memory block, an address and microgroup address generation unit, a micro-command switch, a micro-command register, a control block, a buffer memory block, a data switch and a command register, the first and second outputs of the control unit are connected respectively to the inputs, records of the command register and the address register, the third output of the control unit is connected to the input of the operation code of the operating unit the block, the fourth and fifth 13 outputs of the control unit are connected respectively to the first synchronization input and the write-read input of the data storage unit, the output of the control unit is connected to the first synchronization input of the buffer memory unit, the seventh and eighth outputs of the control unit are connected respectively with the read input of the microprogram memory block and with the first control input of the block of formation of the microOp address and command of the access sign, the first information output of the operating block is connected to the information inputs the SECOND information output of the operation unit is connected to the information input of the address register, the output of the result indication of the operation of the operation unit is connected to the first information M input of the microcommand address generation unit and the access indication, the output of the higher bits of the address register is connected to the decoder's input, the output of the first low-order bit of the address register is connected to the first control input of the data switch, the output of the lower-order bits (where m is the block address address data memory) of the address register is connected to the address input of the data memory block and the first address input of the buffer memory block, the second and third information inputs of the microcommand address generation unit and the sign of the connection connection, respectively, with the output of the command register field operation and the field output the address of the next microcommand of the register of microinstructions, the address output of the block of formation of the address of the micro commands and the access sign are connected to the address input of the memory microprogram block and with the second address input of the buffer pa block The mi, output with the access sign of the microinstructor address generation unit and the access sign is connected to the control input of the microinstruction switch and to the second synchronization input of the buffer memory block, the third synchronization input of which is connected to the second synchronization input of the data storage unit, with the second control input the data switch and with the output of the decoder the output of the data storage unit is connected to the first information input of the data commutator, the output of which is 571 from the information register-1 input of the command register, the output of the block the microprogram memory is connected to the first information input of the micro-switches switch, the second information input of which is connected to the first output of the buffer memory block and the second information input of the data switch, the third information input of the micro-switches switch is connected to the second information input of the buffer memory block and the third information input The data switch, the output of the micro-command switch is connected to the information input of the micro-register register, the output of the operation field of which is connected to the input of the control unit, characterized in that, in order to increase speed, a switch is inserted into it, while the output of the sign, the command register transition is connected to the second control input of the micro-command address generation unit and the reference sign, the fourth information input of the address register, the third control of the micro-command addressing and addressing unit is controlled by the output of the sign of the transition of the micro-command register and to the control input of the switch; the first and second information inputs The switches are connected respectively to the output of the data switch and to the output of the address field of the next microcommand register of microcommands, the fifth information input of the microcommand address generation unit and the access sign is the input of the processor command code, the output of the switch is connected to the information input of the operating unit. 2. Processor according to claim 1, characterized in that the microcommand address and access sign generation unit contains the microinstruction address register, the decoder of the older microcommand address and the multiplexer node of the microinstruction address code, the first, second and third control addresses, the multiplexer node inputs are the first, second and third control inputs of the block, the first second, third, fourth and fifth information inputs of the multiplexer node are respectively the first, second, third, fourth and fifth information and 5–127 block inputs, the output of the multiplexer node is connected to the information input of the micro-address register, the high-order bits of the micro-address register are connected to the decoder input of the high-end micro address command, the micro-commands address register output, the high-end address decoder output microinstructions is the way out. sign of circulation unit. 7fy / 73 f 77 70 VU2 R / L jy 52 78 88 38 tjSJ 8s 76 39 38 53 100 WZ 90. 97 ml i06 Ml fJ3 3 58 9i 9Ts- 90 i08 iOO 102 96 57 SB 59 60 iOS 109 61 1I FIG. five iuB.S 103 92 95 97 Stf 63