SU741269A1 - Microprogramme processor - Google Patents

Description

The invention relates to computing and can be used in digital computers.

A device is known that implements an asynchronous connection between a slower RAM and a faster processor 1.

The disadvantage of this device 10 is that after the process accesses its RAM. the action is blocked for the time equal to the time for retrieving data from the memory, i.e. Simultaneous parallel 5 operation of the RAM and the processor is possible only in the second half of the RAM cycle.

The closest in technical essence is a microcryptal 20 processor comprising an operational memory, local memory, a circuit for performing arithmetic operations, an apparatus for generating addresses, an apparatus for exchanging data, and a microprogram control unit 25. In this processor, in order to increase the speed, asynchronous operation of the RAM and processor 2 is also organized. The disadvantage of this processor is also the blocking of its operation for a time equal to the time of data sampling from. memory

The purpose of the invention is to increase the speed of the processor.

This goal is achieved by the fact that the processor containing the buffer memory, the arithmetic logic unit; in, the register word number 1, the data register, the data dir, the element sampler, the delay element, the memory block, the microprogram memory, the decoder (microinstructions, register of the current cycle, processor blocking block, eight elements And, the arithmetic-logic device input-output is connected to the output-input of the buffer memory, the output of the micro-instructions decoder is connected to the first inputs of the first, second, third, fourth, of the sixth, seventh And elements, the first input of the buffer memory and the first input of the arithmetic logic unit, the first output of the memory block is connected to the first input of the eighth And element, the output of which is connected to the first input of the data register.

the output of which is connected to the first input of the memory unit and the first input of the data switch, whose output is connected to the second input of the buffer memory and the second input of the arithmetic logic unit, the second output of the memory unit is connected to the second input of the eighth And element and the first input of the blocking block a processor, whose output is connected to the microinstructor decoder's input and a first cycle register input for the current cycle, the output of which is connected to the microprogram memory input, the output of which is connected to the second input of the microrogram decoder The command and the second register of the current cycle, the first output of the arithmetic logic unit is connected to the second input of the first element AND whose output is connected to the second data register, the outputs of the fifth, sixth and seventh AND elements are connected to the inputs of the memory word register, the output of which connected to the second input of the memory block, the output of the delay element is connected to the input of the block for the collection of elements And, the output of which is connected to the third input of the first element And, the current address address counter is entered, the logical conditions check block s, n counters and n registers, the blocking signal shaper, with the first outputs n of the meters connected to the second inputs of the fifth, seventh and seventh elements of the And, respectively, the first outputs of the n registers connected to the second inputs of the second, third and fourth elements respectively The second outputs of the n counters and the n registers are connected to the corresponding input “1 and the arithmetic-lotus device, the second output of which is connected to the first input of the logical conditions check unit whose output is connected to the third inputs 1 In addition, the sixth and seventh elements And, the first output of the arithmetic-logical device is connected to the input and counter counters and the first inputs and registers; the outputs of the second, third and fourth elements And are connected to the inputs of the current address counter, the output of which is connected to the second input the logical condition checker, the input of the delay element, the second input of the data switch and the second inputs n of the registers, and the output of the register of the current cycle is connected to the input of the blocking signal generator, the output of which is connected to the second th processor input blocking unit.

The drawing is a diagram of the microporpatviMHoro processor.

The microprogram processor circuit consists of memory block 1, arithmetic logic unit 2,

data exchange unit 3, address unit 4, buffer data storage 5, and firmware control unit 6. The operational memory 1 is connected with the data communication unit 3 by input information buses 7, output information buses 8, memory control word buses 9 and tires

10 control of memory, and

with block 6 of firmware control of memory monitoring buses 10. The data exchange unit 3 contains a data register 11, a memory word register 12, a current address counter 13 connected to the data switch 14 and through delay element 15 and the element selection block 16 AND to the input elements 17 AND of the register

11 data, and also contains a block 18 for determining the moment of accessing the RAM (logical conditions check unit) associated with input 36. With an arithmetic logic unit 2 and a current address counter 13, and with output with input elements AND. memory The data exchange unit 3 is connected with an arithmetic logic unit 2 and data buffer memory 5, output HfcJMH. Information-ashes 19 and input information buses 20, Address unit 4 contains a counter

21 command addresses and counters 22 and 23 of the addresses of the operands (p-tchikov) associated with the output of the arithmetic unit 2, and also contains registers 24, 25 and 26, byte numbers (n registers), respectively, to the address of the command and the addresses of the operands. The buffer memory of the d-5 data is connected with the arithmetic logic unit 2 input and radar information buses. Firmware management block 6 contains .page 27 of the current cycle, firmware memory 28, decoder 29 microcommands, blocker 30 of the blocking signals and block 31 of the processor block — elements 32, 33, 34, 35, 17, 37, 38, 39 I.

The microprocessor processor is designed to perform arithmetic and logical operations on data located as a fixed or variable length in a -teratival memory 1. The usual process of performing an operation in a microprogrammed processor involves selecting a memory from a single address or the addresses of the two operands, the execution of the desired operation in the arithmetic logic unit and the placement of the result in the RAM to the address of one of the operands, the smallest addressable data unit is Bytes The prescribed set operation is performed by the arithmetic logic unit 2, and the processing

fields are byte-byte, and their length is determined by the command. In one processor cycle, a single data processing operation can be performed having a length of 1 byte.

The RAM cycle can be conditionally divided into four equal parts, which differ in the processes that occur in the memory, i.e. into parts corresponding to different states of memory. In the state O, a control word is taken in RAM that defines the data address and the nature of the operation. In state 1, the memory operation is determined by the operation: in a read operation, data is sampled, in a write operation, the data to be stored in the memory is received. State 2 and 3 determine the regeneration of the read information or the recording of the information received in state 1. Thus, the data to be written must be prepared by the processor before the memory reaches state 1 and in the read operation. the data can be used by the processor no earlier than the memory reaches state 2, i.e. after the sampling time Tg. The duration of the RAM cycle in the proposed firmware processor is 2.5 µs, the processor cycle time is 0.625 µs, i.e. one-fourth of the RAM cycle.

Hardware is provided in the firmware program, which allows partially or fully combining the data processing cycles of the processor with the RAM cycles, which leads to an increase in processor speed. The combination is achieved due to the fact that the processor organizes the selection and placement of data in the memory by groups during byte processing, which allows the processing of the current sample to organize in advance the access to the main memory in order to read or write data that will be required after the processing is completed. current sample. The exchange between the RAM and the rest of the firmware processor takes place in 8-byte words.

The main organization of this exchange is the division of the current address of the data byte or the current address of the command into two parts: the physical address of the memory word and the number of the byte in the memory word, the physical address of the word being the high-order bits of the byte address, and the byte numbers in the word - The minor bits of the byte esrres. The physical address of the word and the number of the byte can be changed independently of each other during processing.

Data exchange with RAM and processing takes place in the proposed microprogram processor as follows. If you need to ") read or write data in register 12, the word forms a control word containing the physical address of the 8-byte memory word, the request for accessing the main memory,

o Memory operation code and other data, and transmitted to memory block 1 via bus 9 control words. In a read operation, at the end of the sampling time Td, which corresponds to state 5 of memory 2, memory monitoring signals 10 allow writing an 8-byte word from the information bus 8 of memory to data register 11 via elements 32 I. If in the control

If the word 0 indicates the write operation, after receiving the control word, which corresponds to the state of memory 1, the operational memory receives through the input information buses a 7–8 GB word generated in advance in the data register 11.

The current addresses of the instruction and operands are stored in the address block 4 in such a way that the physical address

The 0 words of the memory to which the bytes of the instruction or operands belong, contain E counters 21, 22, 23, respectively, and the byte numbers are in registers 24, 25 and 26. If a word corresponding to the physical address in the counters 21 is selected in data register 11, 22 or 23, the value of the byte number is rewritten under the control of microinstructions from the register 24, 25 or 26 through the elements 33, 34

0 or 35 And in the counter 13 of the current address; the desired byte appears at the output of the data switch 14 and can be used by the arithmetic logic unit 2. A sequential change of the physical address is performed under the control of microcommands directly in the counters 21 and 22 or 23, and the transition to non-consecutive words is carried out

0 by measuring addresses in the arithmetic unit 2, for which the outputs of counters 21, 22, 23 and registers 24, 25 and 26 are connected to the inputs of arithmetic logic unit 2. And the outputs of counters with output buses 20 arithmetic logic unit 2.

The current addressing of data within a word is performed by the counter 13 of the current address, the contents

Which can be sequentially changed under the control of micro-commands in the direction of increase or decrease. After sampling the required number of data bytes, the current value of the counter 13 can be returned under the microcommand control to the register 24, 25 or 26 byte numbers. Processing after one of the operands is usually placed partially or fully in the buffer data memory 5. At the same time the required number of memory accesses is performed and sequential swapping of data bytes via bus 19 from data coder 14 to buffer 5. Thus, a sufficient stock of data is created for processing without accessing operations memory of this operand. Next, data from the field, another operand is stored in the same way, but the data is transferred by byte through bus 19 to the input of arithmetic logic unit 2. At the same time, byte-by-byte sampling of another operand from the buffer memory 5 and formation of the result byte takes place. The result should normally be placed in RAM. The accumulation of the result occurs in the data register 11 at the location of the used bytes of the source data under the control of the current address counter13 as follows. The value of the counter 13, in accordance with which the output of the data switch 14 is formed, enters through the delay element 15 to the block 16 of sampling elements I. The delay element 15 ensures the delay of the counter 13 of the current address by one processor cycle. Thus, when the new value of the counter 13 is selected, the next byte of the initial data on the block 16 of the sample of elements is And the previous value of the byte number on the output buses of the arithmetic logic unit 2 has the result of processing the previous byte. This result is recorded under the control of micro-instructions in the data register 11 via the elements 17 And to the place determined by the AND sample selector 18, which decrypts the delayed value of the byte number. The current value of the byte number in the counter 13 is also used to determine the moment of the formation of the control word of the memory, which means the moment of accessing the memory, as the control word contains the request; to perform a memory operation If the current value of the byte number in the 13 NB counter is processed in the right-hand data field, or when the data field is processed from left to right in the NB 1, the last byte in the word is processed, and to continue the operation without pausing in the next cycle the processor needs to: in the data register 11, new data is received, or the data register 11 is released from the result by the beginning of the next cycle. To do this, it is necessary to form a request for accessing the RAM before the processor finishes processing the last byte in the word. If the data field ends within a given memory word, then the no address for retrieving data is not required, i.e., the time when a request to execute a memory operation is formed depends on the current length of the processed field. The formation of the control word is determined by the circuit 18 for determining the moment of accessing the RAM, which generates control signals as a function of the current value of the byte number NB and the current value of the length of the field L, The current value of the length of the field indicating at each time the number of data bytes processing in this operation, is formed during processing in the arithmetic logic unit 2 and is transmitted to the circuit 18 for determining the moment of accessing the RAM through the bus 36 of the current field length. Scheme 18 can test several different ratios of the byte number and length, depending on the operation to be performed. For example, when processing the bytes of the field from left to right, the ratio of type (HB 5) may be broken. () + (NB 6) .- () + f (NB 7), where the + sign indicates a logical addition. If the circuit 18 has generated a control signal, then the required control word is formed in the memory word register 12, and the physical address of the next memory word is written by the control command of microcommands through elements 37, 38 or 39 and from the required counter (21, 22 or 23) Thereafter, the memory operation is considered initiated, and the contents of the counters 21, 22, or 23 can be changed by the processor to prepare the next call. From the above relation between the byte number and the current floor length, it is clear that the order has increased. Memory operation In this case, it can be generated during processor processing byte 5, byte 6 or byte 7 of the current data word. If a request to perform a memory operation is made during processing of byte 5, then the first half of the memory cycle (Tg) is used by the processor to process bytes 6 and 7, and after sampling and receiving data from the new memory word in register 11 during memory status 2, the processing of byte O begins, followed by words without stopping the processor, In this case

the processor operates simultaneously and in parallel with the memory block during the entire cycle — i.e. a complete overlap of the RAM cycle by the processor cycles. Accessing the memory block during processing by the processor byte 6 or byte 7 is possible when the processing of the specified field begins with these bytes. However, in these cases, it is only possible to partially overlap the memory cycle with the processor cycles, since the processor does not have a current data supply for two processor cycles corresponding to the random access memory sampling time (Tg), and its operation must be blocked until a new data word is received from the memory. i.e. until memory reaches state 2.

The blocking of the action of the processor is performed in the block B of the firmware control.

Firmware control unit 6 contains a permanent memory 28 for storing firmware, according to which processor operations are performed. The current cycle number of the processor is stored in the register 27 of the current cycle and is at the same time the address of the permanent memory 28, which is the word microcommand of this cycle. The word extracted from pam 28 is decrypted on the decoders of 29 microinstructions, the outputs of which form the signal to control the microoperations gates. The lock block determination circuit 30 generates a signal when 27 numbers of such cycles appear in the current processor cycle register, in which the result of the next operational memory operation is required. The processor blocking unit 31, in the presence of a signal from the Shaper 30, analyzes the state of the RAM by signals received via the memory monitoring buses 10. If the memory is in state 2, which means that the previous 8-byte result word is being completed in RAM, or the new 8-byte DATA word is terminated, the processor's action is not blocked, i.e. the microprogram of the processor continues without delay. If the memory has not reached state 2, the blocking circuit generates signals that block the output of micro-commands and the change of the cycle number. Thus, the processor is in the idle state as long as the state 2 of the RAM is set.

The invention is applicable to computers having high-speed arithmetic logic devices and low-speed RAM.

In the proposed microprocessor processor, during its implementation, the size of the data portion for exchanging with the RAM and the ratio between the duration of the RAM cycle of the long processor can be modified, which will lead to a change in the size of the counter 13 and registers 24, 25, 26, and a change in the register size 11 data, block 16 of the sample, as well as to the choice of another volume of buffer data memory 5.

The reduction in the execution time of the operations is in the range of 1.6 to 2 times for various operations.

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Claims (1)

Invention Formula Firmware processor containing buffer memory, arithmetic logic unit, memory word register, data register, data switch, AND blocker, delay element, memory block, microprogram memory, de0 microcoder encoder, current cycle register, processor lock block , BocisMb elements And, with the input-output of the arithmetic-logical device connected to the output-input of the buffer memory, the output of the decoder 5 microinstructions are connected to the first inputs of the first, second, third, fourth, fifth, sixth, seventh And elements, the first input of the buffer memory and the first input of the arithmetic logic unit, the first output of the memory block is connected to the first input of the eighth element And, the output of which is connected to the first input of the data register, the output of which 5 is connected to the first input of the memory block and the first input of the data switch, which is connected to the second input of the buffer memory and the second input of the arithmetic logic unit, the second output of the memory block is connected to the second input of the eighth And element and the first input of the processor lock block, the output of which is connected to the first input of the decryption of the microinstructor racer and the first input of the register of the current cycle, the output of which is connected to the memory input of the microprograms, the output of which is connected to the second input of the decoder 0 microinstructions and the second input register: current cycle, the first output of the arithmetic-logic device is connected to the second input of the first element And, the output of which is connected to 5 second input of the data register, output- (