SU1111150A1 - Interface for linking two computers - Google Patents

Abstract

DEVICE FOR DOING MATCHING TWO COMPUTATIONAL MACHINES, containing a shift register, the input of the serial code of which is the information input of the device, two groups of AND elements, pulse counter, AND element, the first input of which is connected to the input signal of the device record, and the output with the first input of the OR element , and the first register, the information output of which is the code output of the device number, the output of the parallel code of the shift register is connected to the first inputs of the corresponding AND elements of the first group, distinguishing In order to expand the field of application of the device, a second register and a pulse shaper are entered into it, the information inputs and the recording signals of the first and second registers are connected respectively to the code input of the number and the recording signal input of the device, the sampling inputs of the first and second registers and the second input of the element And form the address input of the device, the read input of the first / register is the input of the read signal of the device, the group of outputs is connected to the first inputs of the corresponding elements in the second group, and the group of inputs to the outputs of the corresponding elements of the first group, the second inputs of the elements of the first and second groups are connected to the output of the OR element, and the third inputs are respectively the first and second outputs of the second register, the clock input of the shift register is connected to the input sync pulses of the device and through a pulse counter to the input of the pulse former, the input of the parallel code to the outputs of elements AND of the second group, and the output of the sequential code is the information output of the device the pulse clock is connected to the second input of the OR element and the start output of the device, the output element and I is the output of the device interrupt, and the third input is connected to the corresponding bit bus of the code input of the device number.

Description

1 The invention relates to computer technology and can be used in computer complexes built on universal and specialized computer machines (VM). The devices for interfacing two VMs are known, which contain two information registers, a command register, a command register, a node, a formation unit: addresses, two exchange state fixation nodes, a switch, driver-receiver units and transmitter drivers, a status register, a formation node ready signal, malicious OR and synchronization node tl. The disadvantage of these devices is the high hardware costs. The closest to the proposed technical entity is an interface device containing a shift register connected by an output to the inputs of the first and second counters, the output of which is the output of the device request signal, the first, second and third groups the outputs are connected, respectively, to the information inputs of the AND elements of the first group and the groups of inputs of the RAM and the decoder, the first and second outputs connected to the control inputs The first and second groups of elements whose outputs through the OR elements of the first group are connected to the first input of the adder, the second input of which is connected to the output of the base address register, and the output to the first inputs of the OR elements of the second group, the second inputs of which form the address input of the device, and the output connected to the address input of the RAM, the information output of which is the information output of the device, the sample input is connected to the output of the OR element, and the write / read input to the trigger output, the first and second inputs OR gate connected respectively to the outputs of the shift register and the AND gate, the first and second rows are connected WMOs sootvetstv.enno device with read pulses trigger input and output, the inputs of which are connected respectively to the output of the second counter and the input completion signal C2.3 device. The disadvantages of this device is the limited scope, since the device provides information transfer only in one direction: from a specialized VM to a universal digital computer. The purpose of the invention is to expand the scope of the device. The goal is achieved in that the device containing the shift register, the input of the serial code of which is the information input of the device, two groups of elements AND, the pulse counter, element AND, the first input of which is connected to the input of the device recording signal and the output to the first input the OR element, and the first register, the information output of which is the code output of the device number, the output of the parallel code of the shift register is connected to the first inputs of the corresponding AND elements of the first group, the second p are entered the gist and pulse shaper, the information inputs and inputs of the first and second registers recording signal are connected respectively to the code input of the number and the recording signal of the device, the sampling inputs of the first and second registers and the second input of the And element form the address input of the device, the read input of the first register is the input signal of the reading device, a group of outputs connected to the first inputs of the corresponding elements And the second group, and a group of inputs to the outputs of the corresponding elements And the first group, the second inputs of the elements of the first and second groups are connected to the output of the OR element, and the third inputs are respectively with the first and second outputs of the second register, the clock input of the shift register is connected to the input of the device clock and, through a pulse counter, to the input of the pulse former, the parallel code input is to the outputs of the elements of the second group, and the output of the serial code is the information output of the device; the output of the pulse shaper is connected to the second input of the OR element and the start output of the device; This And is the interrupt output of the device, and the third input is connected to the corresponding bit bus of the code input of the device number.

FIG. 1 is a block diagram of the device; in fig. 2 - time diagram of the device during the transmission of information; on fig.Z and And - the algorithm of the device when recording and reading information.

The device contains (1) the shift register 1, the elements of the second group 2, the elements of the first group 3, the element 4, the pulse counter 5, the pulse generator 6, the element OR 7, the first 8 and second 9 registers, the input bus 10 clock pulses ., buses 11 and 12 of information input and output of the device, bus 13 of the output of the device interrupt, bus 14 of the code inputs and outputs of the device number, bus 15 of the read signal of the device, bus 16 of the start output, bus 17 of the write signal of the device, bus 18, 19 and 20 address input device, output 21 and input 22. interrupting the first 23rd and second 24 digital computers.

A digital computer (DVR 24 provides the following when transmitting information: bus 10 transmits a continuous series of clock pulses, bus 11 sends accompanying information. The information represents an array of words greater than or equal to one sixteen bit word, i.e. each word is sixteen I will give

The timing diagram for the transmission of information has the form shown in FIG. 2, i.e. the coincidence of the clock pulses on the bus 10 and the pulse on the bus 11 means the presence of a logical 1, and if there is only a clock pulse on the bus 10 - O.

Digital computer 24, when receiving information, transmits only clock pulses over bus 10, and digital array 23 transmits an array, greater than or equal to one word, with a serial code through an information exchange device.

In both cases, the number of supplied clock pulses on bus 10 is equal to the number of transmitted words multiplied by the word width.

The exchange of information between two computers is carried out as follows.

The transmitting digital computer (23 or 24) generates the interrupt signal of the direct digital computer and after a period of time (preliminarily agreed and laid) the first in the algorithm) the digital computer 24 transmits the sync pulse. Bus 10 and information on bus I1, if it is transmitting, or sending clock pulses on bus 10 and receiving information on bus 12, if it is receiving. The number of words transmitted is transmitted by a separate sending of one word.

Register 9 can be in two states: Record state, in which it is prepared for opening

the elements are 2 and the reading state, in which the elements of the CI are prepared for opening.

Register 9 is converted to another state by DV 23

information from the bus 18

(since the access occurs to the register 9, from the bus 14 and using the control signal from the bus 17.

The recording from the digital computer 23 to the register 8 is made according to the information received from the buses 19, 14 and 17.

Reading from register 8 to digital computer 23 is carried out on bus 14, if available

information (i.e., single signals on buses 19 and 15.

The device works as follows.

If it is necessary to transmit information from the digital computer 23 to the digital computer 24, then it is necessary to give a signal to the bus 17 and select the address on the bus 19 ... In this case, using buses, 14, one word is written in register 8.

This word means the following: the information recorded in the first digit means what will be received or transmitted, the information (or O, respectively), and the value

the remaining bits are determined by the number of words transmitted.

If there are signals in 17 and 18 and units in the first section of the 14 width, the register 9 forms a signal that prepares the elements for opening 2. And the signal from the output of the element. OR 7 provides the opening of the elements AND 2, thereby ensuring the rewriting of information from register 8 to register 1.

The PC 23, after transmitting the interrupt signal, enters a stop state.

If there are signals on the bus 20, on the bus 17 and the units in the first discharge on the bus 14. at the output of the element 4, an interrupt signal is generated for the digital computer 24.5

CVM 24, after processing the interrupt signal, transmits on bus 10 sixteen for the sixteen bit word of clock pulses, which provide the rewriting of information from registry 1 to CVM 24. Clock pulses are counted by counter 5, in addition, each clock pulse is a shift pulse for register I .

The counter 5 is reset to zero after counting sixteen pulses.

condition. When the sixteenth sync pulse arrives at counter 5, they are given a signal to shaper 6, which, in turn, generates a signal on bus 16 for starting CMV 23.

For the operation of the digital computer 23, the digital computer 24 generates a signal at the output 21, which is fed to the input 22 of the digital computer 23.

Further operation of the device is similar to that described.

The device operation algorithms for recording and reading information in the digital computer 24 are shown in FIG. 3 and 4.

Thus, the device provides for the exchange of information between two digital computers.

lIlUHuW

Ш1на11 (} 2)

/ 1odi (B3i Address Worness / (i-l) 2S

I start) I

Interrupt bZifReading information 3 -YADU 25

Mffucb information in 8

ffc / naffOS 23

/ 7acK device, domain inormation

Not

(. ((onyets) //z.J

Issue pr rmbanie

gtusk i / cmpaiJcmiSa

CvumbtSffHUQ or S

Record i / H oDHauuij 6 tschiki OSh 23

(

R $ 2tt

Stop 23 (/ H df Haifue6

Tl

Not

Kwtt j

Fy

Claims (1)

A DEVICE FOR PAIRING TWO COMPUTING MACHINES, containing a shift register, the input of the serial code of which is the information input of the device, two groups of elements And, a pulse counter, element And, the first input of which is connected to the input of the device's recording signal, and the output - with the first input of the OR element, and the first, a register, the information output of which is the code output of the number of the device, the output of the parallel code of the shift register is connected to the first inputs of the corresponding elements of the first group, characterized in that o, in order to expand the scope of the device, a second register and a pulse shaper are introduced into it, and the information inputs and inputs of the recording signal of the first and second registers are connected respectively to the code input of the number and the input of the recording signal of the device, the sampling inputs of the first ή second registers and second the input of the And element forms the address input of the device, the read input of the first, the register is the input of the read signal of the device, the group of outputs is connected to the first inputs of the corresponding elements And the second group s, and the group of inputs is to the outputs of the corresponding elements of the first group, the second inputs of the elements of the first and second groups are connected to the output of the OR element, and the third inputs are respectively the first and second outputs of the second register, the clock input of the shift register is connected to the input of the clock pulses devices and 'through the pulse counter - to the input of the pulse former, the input of the parallel code - to the outputs of the elements of the second group, and the output of the serial code is the information output of the device, the output of the pulse former Inonii to a second input of the OR gate and the output of the start-up element and the output device is an output interrupt, and a third input coupled to a corresponding bit line code chisl'a input device. SU „..1111150 1 and