SU962899A1 - Device for interfacing digital computer with peripheral units - Google Patents

Description

The invention relates to computing and can be used & ano in information measurement systems in which the interconnection of devices is carried out through a common bus, a mini-bus. A device for interfacing a digital computer with an external drive is known, comprising a control unit, a shift register, a time synchronization unit, a counter, a time interval converter into a code, a division unit G1. However, this device controls the information and the cycle of its grammes in the process of counting and recording information on an external drive with the participation of a digital computer, which reduces the effective speed of the latter. The closest to the proposed technical essence and the achieved result is a device for interfacing a digital computer with peripheral devices, comprising a block of communication signal amplifiers with a digital computer, a block of communication signal amplifiers with peripheral devices, an address decryption unit, a switch, an interrupt issuer, a block even, the interrupt resolution trigger, the IC scheme. However, in the known device there is no possibility of organizing asynchronous information transfer when working with synchronous external drives, which reduces the exchange rate when working with synchronous peripherals. The purpose of the invention is to increase the exchange rate when working with synchronous peripheral devices and increase noise immunity. The goal is achieved in that the device for interfacing a digital computer with peripheral devices, comprising a control word storage unit, the first information output of which is connected to the information input of the switch, an address decoder, the first output of which is connected to the first trigger input of the exchange control unit, an interrupt unit, a parity generation unit, an amplifier unit, and an AND element, the second output of the address decoder being connected to the first input of the AND element and to the control input torus, the third and fourth outputs of the address decoder are connected to the synchronization input of the interrupt unit and the address input of the control word storage unit, the second and third information outputs of which are connected respectively to the information input of the parity generation unit and allowing the output of the block interrupt is connected to the first sign-in input of the switch, the output of which is connected to the second input of the amplifier unit. The first master output of the exchange control unit is connected to the control input of the control word storage unit, the output of the operation end of the exchange control block, the output of the AND element, the output of the interrupt block, the address of the address decoder, the reset input of the exchange control block allowing the input of the interrupt block, the first information input of the control word storage block are connected respectively to the third - fifth inputs and the first. fourth outputs of the amplifier unit, the input-output of which is connected to the first input-output of the device, have been introduced the session control block, the cyclic control register, re: his Tr addresses and a buffer memory block; 1 the first to fourth information inputs of the session control block are connected to the outputs of the cyclic ring, the buffer memory block, the address register and the parity shaping block, respectively; the first to fourth information outputs of the session control block are connected corresponding to the information input of the cyclic control register, with the information input of the cyclic control register, with the information input of the buffer memory block, with the second information input the control word storage unit, the first, second, and third gating outputs of the session control unit are connected to the control inputs of the cyclic control register, the address register and the buffer memory unit, respectively, specifying the output of the session control unit connected to the first control input the parity shaping unit and with the shift input of the control word storage unit, the demand output of the session control unit yv is connected to the second by the switch sign input and to the second start of the control unit and exchange, the output of the end of the operation of the session control block is connected to the interrogation block interrogation block, the exchange control block and the third indicative switch input, the output of the exchange direction of the session control block is connected to the second control gate of the parity and the mode input the exchange control unit, the second and third setting outputs of which are connected respectively to the reset input and the ready input of the communication session control unit, the error output and the input-output of which are connected respectively naturally with the input of the element And with the second move-out device. The session control block contains the memory of the micro-commands, the micro-address address register, the micro-commands register / micro-commands decoder, the first and second switches, the shift register, the counter, the super-fast memory address register ti, super-fast memory, pulse distributor, condition selector, four-elements AND, two elements AND, a transceiver node 1-dhi amplifiers, with the output of the first switch connected to the information / M inputs of the shift register, the counter over The first memory of the condition selector is connected to the first inputs of the first and second And elements, to the second information input of the microcommand address register and to the information input of the address register of the ultra-fast memory, to the second input of the second Element And with the second gating output of the block, the second output of the condition selector, the first attribute output of the second switch and the first output of the micro-command decoder are connected respectively to the first, second and third The inputs of the pulse distributor, the first output of which is connected to the control input of the microcommand decoder, the second output of the pulse distributor is connected to the control inputs of the microcommand register, the microcommand address register, register: address, super memory, counter, shift register and super memory, output the micro-command address register is connected to the micro-command memory input, the output of which is connected to the micro-register register information input and to the first information input of the first switchboard, the third and fourth information inputs of which are connected to the outputs of the super-operative memory, counter and shift register, respectively. The first output of the micro-command register is connected to the first information input of the micro-command decoder and to the control input of the first switch, the second and third outputs of the micro-command register are connected to the second information inputs, respectively, of a micro-command decoder and a micro-command address register; the second output of the micro-command decoder is connected to the input of the second switch, The indicative output of which is connected to the first inputs of the third and fourth elements I, the second outputs are connected respectively to the first and second outputs of node 1; the receiving amplifiers, the first, second and third information outputs and the information output of the second switch are connected to the first, second, the third information output of the unit and with the first input-output node of the transceiver amplifier, the third output of which is connected to the first input of the condition selector, the second, third and fourth outputs of the selector and the conditions are connected respectively to the first, second and third information inputs of the block, the first node of transceiver amplifiers is connected to the second input of the first element AND whose output and output of the second 31 element AND through the first element OR are connected to the first gate output of the block, the outputs of the third and fourth elements And through the second element OR are connected to the third gate output of the block, the output of the register of the address of the super-operative Ps1m-te is connected to the address input of the super-operative memory,% group of inputs-outputs of the block The second group of inputs and outputs of the transceiver amplifier unit, the fourth and fourth outputs, and the second, third, fourth inputs of the transceiver amplifier unit are connected respectively with the errors of the block, the exchange direction of the block, the end of the block operation, the block requirement, with the output of the block, with the fourth information output of the block, with the reset input of the block, with the readiness input of the block and with the fourth information input of the block.

FIG. 1 shows a block diagram of the device; in fig. 2 is the same, of the session control block, in FIG. 3 - the same, the control unit of the exchange; in fig. 4 is the same as the second switch of the session control unit; in fig. 5 - microinstructions formats.

The device for interfacing digital computational meoiins with grit peripherals (Fig. I) contains block 1 of amplifiers j block 2 interrupts 1, decoder 3 addresses, block 4 of storing control words, switch 5, block b of exchange control, as part of interrupt block 7 trigger and an interrupt address shaping node 8, then the device comprises a parity shaping unit 9, an AND element 10, a session control block 11, a cyclic control register 12, an address register 13, a buffer memory block 14, inputs and amplifiers block, the fourth entrance 15, thirds th input 16, first output 17, second output, 18, fifth input 19, third output 20, fourth output 21, first input .22 / second input 23,

session control inputs and outputs: ibki output 24, reset output 25, readiness input 26, exchange direction output 27, operation end output 28, demand output 29, fourth information input 30, output 31, fourth information output 32, first 33, second 34, third 35, fourth 36 outputs of the address decoder, first 37 and second 38 information outputs of the control word storage unit, output 39 of the trigger of the interrupt unit, specifying the output 40 of the exchange control unit, first input-output 41 of the device, inputs and output control block session in connection:

5 troupe 42 inputs and outputs, the first gate output 43, the first information output 44, the first information input 45, the second and third information inputs 46 and 47,

0 the second gate output 48, the second information output 49, the third gate output 50, the third information output 51 and the second group 52 of the device's input-output.

five

The session control block (Fig. 2) contains the memory of 53 micro-instructions, the register 54 of the micro-instructions, the register 55 of the address of the super-memory, the super-operative memory 56, the decoder .57

About microinstructions, counter 58, register 59. addresses of microcommands, first switch b6, shift register 61, second switch 62, condition selector 63, distributor 64 pulses, outputs 65 -

5 67 registers of microO1 $ command, outputs 68 69 of the micro-command decoder, inputs 70-72 and outputs 73, 74 of the pulse distributor, elements OR 75 and 76, elements AND 77-80, node .81 receiving-trans-.

0 giving amplifiers, information outputs of the second switch: first 82, second 83, first characteristic output 84, third information output 85, input / output 86, second characteristic output 87, input 88.

five

The exchange control block (Fig. 3) contains elements AND 89, 90 and 91, elements HE 92 and 93, elements OR 94 and 95, trigger 96, element OR 97, elements HE 98 and 99, delay element 100, elements AND 101 and 102, element OR 103.

The second switchboard (Fig. 4) contains the groups of elements AND 104-108, element5 109.

The device works as follows.

The program exchange of information between the main memory of the digital computer and peripheral devices is carried out under the control of the digital computer program. When operating in software mode, the device uses two registers of the 4 command and state register and a data register that are addressed from the common bus side. Programmatically, you can download and read information from addressable registers. Any of them are addressed as follows. The processor places a register address on the address line, and a read or write code on the operation code line. If a recording is being made, the data line connected to the output 21 generates loading information. After that, a common bus synchronization signal is set. Block 3 decryption-. It enters the address and operation code of the common bus coming into it from output 17 of the block; 1, and sets the corresponding signal to the registers access output 36. Recording information to the register of block 4 comes from output 21 of block 1, when information is received, from the register of the block comes parallel to a group of input-outputs41 through input 22 of block 1 and through switch 5 and input 23 of block 1. Block 3 signals block 6 to complete the operation on output 33, after block 6 it generates a response clock signal to the group of inputs-inputs 41 from input 16 of block 1. Process op received in this signal, completes the operation for a common bus or minishine. I If a call is made to the register of the peripheral device., Block 3 decrypts the address of this peripheral device, received from output 17 of block 1, and a signal from output 33. starts the block, 6. Block 6 uses a signal from output 40 to enable entry into the register unit 4 commands of the peripheral number and function code. In this case, the block 6, by the control signal, which arrives at the input 26 of the block 11, informs the peripheral device about the readiness of the received information for transmission to the peripheral devices. The register of commands and states and the register of peripheral devices are implemented on a common wavelength; .shift register. .Direction. The transfer of information between the interface device and the peripheral devices is determined by the signal Direction coming from the output 27 of the unit 1.1. The single value of the 1 direction signal means the transfer of information from the interface device, zero - to the device interface. Peripheral device wives. Single signal value End of operation, coming from output 28, block 11 indicates that the peripheral device is not working and is waiting for a command from the processor. Digital computer To transfer the command code stored in the register of block 4 to the peripheral device it is necessary that the signal Direction from the output 27 of the block 11 is one and the signal End of the operation from the output 28 of the block 11 is also single. The peripheral device, in response to a signal. The control received at input 26 of block 11 generates a pulse signal Shift, from output 31 of block 11, which converts the information recorded in the parallel code into the shift register of block 4 into a serial one. Serial information from output 38 of block 4, passage through block 9 of parity, enters input 30 of block 11 and further to a peripheral device that generates 8 Shift signals from output 31 of block 11 to fully receive the command code and parity for the JCOHT control information . Receivedbyte of the command code and checking the accuracy of its transmission, the control unit 11 decrypts the command code. If the command Buffer loading is set, then block 11 proceeds to the execution of the firmware corresponding to the algorithm for executing the command. In this case, block 11 enters the transmitted number of information bits into the address register 13, generates a zero signal at output 49 and an pulse signal at output 48, after which block 11 sets a zero signal. End operation at output 28 and generates a single signal Requirement-. output 29, which enters the exchange control unit 6. By signal from output 40, block -6 allows parallel loading of data lines. information received at the output 21 of block 1 and into the register of block 4, and by the control signal - arriving at input 26 of block il, this block is informed about the readiness of the information to be transmitted, the signal of the data at input 30 of block 11 transmits the high bit of the data byte. Block 11 in response to the appearance of a signal. The control generates a pulse signal at output 50 and rewrites the most significant byte from output 51 to block 14 of the buffer memory at the address specified by address register 13. Then, block 11 changes the contents of address register 13 by one, generating a single signal at output 49 and a pulse signal at output 48. The pulse signal Shift from output 31 of block 11 shifts the information in the shift register of control word storage block 4. On the signal line now the next bit of the data byte is transferred, which is written to the buffer memory block 14 by a pulse signal from the output 50 of block 11 at the address increased by one. By forming another 5 Shift signals and alternately changing the contents of the address register 13, block 11 records the transmitted data byte in the buffer memory block 14. Then block 11 generates a single signal Requirement, which from output 29 enters block 6 of the control unit. Signal from output 40 of block 6 allows parallel loading of information from output 21 of block 1 into register 4 via data lines, and the control signal, from input 26 to block 11, indicates readiness to transmit the next byte. The steps to rewrite the next data byte in the buffer memory block 14 are the same as described above. The last byte transmission unit 11 determines by the appearance of a signal RUPD overflow from the address register 13, which enters unit 11 on input 47. Having determined the transmission of the last byte, unit 11 sets a single signal to End operation on output 28.

If the command Record of a sector is set by the command code, then in block 11 only 2 data bytes (track number, sector number) are transmitted. Then block 11 sets the zero signal to the end of the operation and generates control signals for the external drive to find the target track and the desired sector, while running the corresponding firmware. When a given area is found on the carrier, block 11 writes a code combination of the byte signals of the address data marker and organizes a bitwise copying of information from block 14 to the external storage device with the required recording frequency. In this case, block 11 enters the address register 13 with the return input the transmitted number of information bits to form a zero signal at output 49 and a pulse signal at output 48, thereby setting the starting address of the buffer memory block 14. A bit of information recorded at the starting address of the buffer memory is entered through block 11 at input 46 and then into cyclic control register 12 from output 44 with a pulse signal from output 43 and written to the external device carrier in combination with a clock signal through a group of inputs outputs 52 of block 11. Then block 11 changes to one the contents of register 13 of the address, forming a single signal at output 49 and pulse c, ignal at output 48. The information wit recorded at the previously selected address is entered into the cyclic control register 12 and writing is acting on the recording medium to those described above. The last rewritten bit of information from the buffer memory to the cyclic control register 12 and to the storage medium is detected by block 11 by a signal overflow RLVOP at input 47. Then block 11 writes bit by bit in combination with the clock signals to the storage medium the contents of the cyclic 12 register. control, which is fed to the input 45, generates 16 pulses from the output

43 and a zero signal from output 44. After this, block 11 generates a signal. End of operation - at output 28.

If the Sector Read command is specified by the command code, then 2 more bytes of information (track number, sector number) are transmitted to block 11 from the digital computer. After that, block 11 sets the zero signal. End of operation and generates control signals for the external drive to find the specified track and the desired sector. When an address data marker of a given sector is detected, the reproduced information from the carrier is fed into block 11 through a group of inputs / outputs 52 and is written to the cyclic control register 12 from output 44 with a pulse signal from output 43 and pulse buffer from output 51 from the output of .50 to the address specified by the address register 13. Preliminarily, block 11 returns to the initial state 0 a register 12 of cyclic control, specifying a single signal from the output

44 and pulse output 43, and the register 13, addresses, forming a zero

output 49 and pulse

5 output 48, specifying the number of bits of information that will be transmitted from the carrier. Block 11 then changes the contents of address register 13, generates a single signal at output 49 and a pulse signal at output 48, and writes the next bit, information from the carrier to cyclic control register 12 and to buffer memory block 14. If the last bit of information is recorded, then ,. detecting a signal RUPOL overflow, block 11 generates 16 pulses at output 43 and zero, the signal at output 44 bit checks for the presence of a zero signal at input 45. If only a zero value of the signal at input 45 is detected, then block 11 generates a signal. End of operation output 28. If a single value is detected

5 signals at the input 45 of at least one bit at the output of the cyclic control register 12 (discrepancy of the read information during playback with the information of two bytes read during recording and recorded on the carrier), then block 11 generates a signal. End of operation at the output 28 and the error exit 24.

When executing the command Unload

5 of the buffer, block 11 sets a zero signal. The end of the operation at output 2 enters the address 13 into register 13; the number of information bits under the transmitted transmission is CODE; forming a zero signal at output 49 and a pulse signal at output 48. Then, block 11 generates a zero signal. 27 and 8 pulse signals Shift at output 31, which transform the serial information received through the input 46 of block 11 from the buffer memory unit 14, from the cell specified by address register 13 and entering the shift register of block 4 from the output Ode 32 to Parallel. Then, block 11 generates a single signal. Requirement at output 28, which via switch 5 is fed to input 23, Formed - information from the shift register of block 4 by a parallel input is fed to input 22 of block 1 by four bits and four bits to input 23 through switch 5 in a digital computer via data lines. At the output 3 of the block 3 address decryption generates a zero signal, which allows the transfer of information from the shift register of block 4 to output 35 and further to the switch 5. Having formed the next byte in the shift register of block 4 in the same way, block 11 plays a single signal , at: output 29, if it is necessary to transmit another byte, or a single signal. The end of the operation at the output, it detected a single signal. Overrunning of the OPERA at output 47. In the automatic request processing mode, the device operates as follows. The interrupt enable trigger 7 is programmed from a digital computer by a signal from the output 20 of block 1 when a synchronizing signal is detected from the output 35 of the address decoding block 3. At. receiving an interrupt request from, output 28 of block 11, the interrupt address generation node 8 generates an interrupt vector memory address of the digital computer that stores the initial address of the service program of the request. After determining the highest priority request and the corresponding interrupt vector, node 8 performs an operation of interrupting the DVM program. As a result, the interrupt vector is transmitted from block 2 to input 19 of block 1 and further to the processor. The resetting of the peripheral devices is performed by the Reset signal, which is fed to the input 25 of the block 11 and produced by the exchange control block 6. In this case, the processor issues a general or software reset via the output 18 of block 1, which is fed to the exchange control block b. Signs STATUS - signal End of operation from output 28, signal Requirement from output 29 of block 11 and state of trigger 7. interrupt enable - are transmitted to the digital computer via switch 5 to input 23 of block 1 when setting the read operation of the control register and state and when generating a signal output 34 block 3 decryption addresses. At that, the Error sign is output through the AND 10 circuit at input 15 of block 1. Symptom Error comes from block 11 from its output 24. Hardware costs for implementing the buffer RAM (one. IvMKpocxeMa with capacity. 1024 bits and address register of the buffer RAM ( three chips of the series 155) g / min.. The cyclic control register can be implemented on four chips of the series 155. The advantages of the invention in comparison with the basic object - the commercially available subcomplex external memory on floppy disks A3284 to UVC CM 1, CM 2 - conclude but in the following: The possibility of organizing cyclic monitoring allows the device to control the transmitted information autonomously with great reliability by comparing the cyclic monitoring bytes generated during the recording of information and recorded on the carrier (2 bytes) with cyclic monitoring bytes generated during playback. When they are not compared, a signal is output to the processor, in a timely manner, together with the processor, when an error occurs, thereby increasing the noise immunity of the device. The ability to organize asynchronous data transfer of synchronous drives allows the computer system to free the processor from the | the possibility of executing a hard cycle of exchange with synchronous accumulators, and when the processor handles interrupt requests with the highest priority, allows the interruption of the exchange without loss of information, reducing the influence of electromechanical ones; parameters of external drives for time synchronization of signals of the exchange protocol with a digital computer, exchanges data with the maximum possible speed, eliminating the dependence on the response time of external drives, freeing the processor FROM routine processing of information slowing down the implementation of basic processes ;, ensure that the device can be connected to processors with different exchange rate.

Inventory Formula

Claims (2)

1. Devices for interfacing a digital computer with peripheral devices, comprising a control word storage unit, the first information output of which is connected to the information input of the switch, an address decoder, the first output of which is connected to the first trigger input of the exchange control unit, an interrupt generation unit , block of amplifiers and element H, the second output of the decoder. address is connected to the first input of the element I and to the control input of the switch, the third and fourth outputs of the switch the address phrases are connected respectively to the synchronizing input of the interrupt unit and to the address input of the control word storage unit, the second and third information outputs of which are connected respectively to the information input of the parity generating unit and to the first input of the amplifier block, allowing the output of the interrupt unit to be connected to the first sign input of the switch the output of which is connected to the second input of the amplifier unit, the first driver specifying the output of the exchange control unit is connected to the control input of the control unit words, the output of the operation of the exchange control block, the input element I, the output of the interrupt block, the address decoder input, the reset input of the exchange control block, the enable input of the interrupt block, the first information input of the control word storage block is connected to the third to fifth input and with the first - fourth outputs of the amplifier unit, the input - output of which is connected to the first input-output of the device, characterized in that, in order to increase the exchange rate when working with synchronous peripheral devices and enhancement, noise immunity, it contains the session control block St. b, the cyclic control register, the address register and the buffer memory block, the first to fourth informational inputs of the session control block are connected to the outputs of the cyclic control register, the buffer memory block, the address register and the parity shaping unit, respectively; the outputs of the session control block are connected respectively with the information input of the cyclic control register, with the information input of the address register, with the information input of the buffer memory block, with The second information input of the control word storage unit, the first, second second, and third gating outputs of the session control block are connected to - the control inputs of the cyclic control register, the address register and the buffer memory block, respectively, specifying the output of the session control block is connected to the first control input of the parity shaping unit and to the shift input of the control word storage unit. The output of the request of the control block of the communication session is connected to the second sign-in input of the switch and to the second apuskayuschim included exchange control unit output end of the operations of the control unit communication session 5 is connected to the request inputs of the interrupt unit, the exchange control unit and the third indicative input of the switch; the output of the exchange direction of the session control unit is connected to the second control input 0 of the parity gating unit and with the real input of the exchange control unit, the second and third setting outputs of which are connected respectively to the Reset input and to the input of the session control block, the error output and input output of which are respectively with the second input-output device. 0 2. The device according to claim 1, wherein the session control block contains micro-commands, micro-command address register, micro-command register, micro-commands decoder, first and second switches, shift register, counter, slug memory address register, super-fast memory, pulse distributor, condition selector, four AND elements, two AND elements, a node of transceiver amplifiers, the output of the first switch is connected to the information inputs of the shift register, the counter 5 super memory and with the first. information input register address microinstruction, the first output of the condition selector is connected to the first inputs of the first and second elements And, 0 with the second information input of the micro-command address register and with the information input of the super-operative memory address register, with the second input of the second element I and with the second 5 gating the output of the block, the second output of the condition selector, the first indicative output of the second switch and the first output of the micro-instruction decoder are connected respectively to the first, 0 the second and third inputs of the impulse distributor, the first output of which is connected to the control input of the microinstructor decoder, the second output of the pulse distributor connected to the control inputs of the register microcommand, microcommand address register, super-operative memory address register, counter, shift register and super-fast memory, the output of the microcommand address register is connected to the microcommand memory input, the output of which is connected to the microcommand register information input and the first information input of the first switch, the second, third and fourth information inputs of which are connected to the outputs of the counter memory and the shift register, respectively, of the first-time memory; the first output of the micro-register register is connected to the first The second and third outputs of the microcommand register are connected to the second information inputs of the microcommands deshfrarator and the microcommand address register, the second output of the microinstrumenter decoder is connected to the input of the second switch, the second sign output of which is connected to the first output of the microcommands, which is connected to the input of the second switch, the second sign output of which is connected to the first output of the microcommands, connected to the input of the second switch; the third and fourth elements And, the second outputs of which are connected respectively with the first and second outputs of the node transceiver amplify Leu, first, second and third information outputs and information1 (ion input-output of the second switch are connected respectively to the first, BTopblM, third information output of the block and to the first input of the output of receiving and transmitting amplifiers, the third output of which is connected to the first input of the selector conditions the second, third and fourth output of the condition selector are connected to the respective stent of the first, second and third information inputs of the block; the first output of the node of transceiver amplifiers is connected to the second input of the first element AND whose output and output of the second element AND through the first element OR are connected to the first gate the output of the block, the outputs of the third and fourth elements And through the second element OR is connected to the third gate output of the block, the output of the register of the address of the super-operative Ps1m is connected to the address HEEM Jocho SuperO active memory, the group of inputs-outputs of the block is the second group of inputs-outputs of the transceiver amplifier unit, the fourth - ninth outputs and the second, third, fourth inputs of the transceiver amplifier unit are connected respectively to the error outputs of the block of the direction of the block, end of operation a block, a block requirement, with a block master output, with a fourth information output block, with a block reset input, with a block ready input, and with a fourth information block input. Sources of information: taken into account in the examination 1. Authors certificate of the USSR 575653, class, G 06 F 3/04, 1975, 2. USSR author's certificate for application No. 2798167 / 18-24, cl. G 06 F 3 / 04J 9.01.80, (prototype). ..J "iM.M iCl 9) “a tf By / ie I I ff r nan / ffT№ t / HGfTf  kl / 1 I I I I I  H  I I I I 1 I- semS / fe t / e  I I I I fesycffoSffOtu I I I I I ne exoff  I I II-ffwfo PO . I I I I I I I. ci / HxpOffu3otfifii I I L-ol 68 Uff.t / Lolé SbtSt a Pu & ff