SU1543415A1 - Device for interfacing two computers - Google Patents

Abstract

The invention relates to computing and can be used to interface computers in multi-machine computing complexes. In order to reduce CPU time losses in transferring information arrays by organizing direct access mode without blocking the processors, switching unit 14, mode register 13 and eight bus drivers 20-27 are added to the device to connect additional memory blocks and save a constant amount of address space COMPUTER. 4 il.

Description

The invention relates to computer technology and can be used to interface computers in multi-machine computing complexes.

The invention focuses on reducing processor time for transmitting information arrays due to the direct access mode of processors.

The drawing shows the ma device.

The device contains the first 1 and second 2 address selectors, the first 3 and second 4 status registers, block 15 5 interrupt, block 6 state, the first to third transceivers 7-9, the first register 10; (address counter), register 11 (array counter), second register 12 (address counter 20), mode register 13, switching unit 14, interface signal generation unit 15, the first. 16 and second — a swarm of 17 registers (receivers), the first 18 and second 19 registers (transmitters 25 ki), the first to eighth bus formers 20-27, the first element OR 28, the first element AND 29, the second element OR 30, single vibrator 31, inputs 32 and 33 of the device for connecting to the same inputs and outputs, the first and second computers, respectively, the inputs and outputs 34, 35 and 36, 37 of the device for connecting duplicate memory blocks of the first and second computers coot-jg respectively. ’,

Transceivers 7-9 are designed to separate the computer channels from the internal information channel of the interface device at various stages of operation. The counter registers 10 and 12 are used to record the starting addresses of the RAM source and the RAM receiver information and the formation of the current addresses for the RAM source and RAM receiver 45 nickname in the mode of transmission of the information array, counter register 11 - to generate the signal to end the transfer an array of information! .

Register 13 is used to form the gg mode of operation of the interface device, while register 13 has eight information bits corresponding to eight control buses. The information bits of the register 13 gg mode have the following meanings: 1p2p - determine the operation mode of the device; Зр-4р - determine the operation mode of the main transceivers 7-9 and the register-counters 10 and 12 addresses; 5p - determines the availability of transmitted information in the reserved RAM of the first computer; 6p - determines the availability of transmitted information in the reserved RAM of the second computer; 7p - initial. ’Installation (NU) of the switching unit 14; 8p - initial installation (NU) of the entire device except for the switching unit 14.

Block 14 is designed to control the operation of Formers 20-27 and start block 15.

Block 15 serves to control the transfer of information arrays.

The device operates as follows.

After turning on the power of the system of two computers connected by the interface device, the NU signals from the channels of both computers go to the OR 30 element and to the unit 14. From the output of the OR 30 element, the NU signal sets the blocks and registers of the device to its original state. In block 14, the OH signals of both channels are opened by the drivers 20 and 23 and closed by the drivers-21 and 22, respectively, the drivers 25 and 26 open, the drivers 24 and 27 are closed. Thus, after the action of the NU signal, input-output 32 is connected to input-output 36 through the open driver 20 and disconnected from the device data channel by the closed driver 22. Input-output 34 is connected to the device data channel through the open driver 23 and disconnected from the input -output 32 with closed shaper 21. Similarly, input-output 33 is connected to input-output 37 and disconnected from input-output 35.

I

Since the device is symmetrical, we consider one-way transmission of information.

In accordance with the program, the first computer determines the point in time when it is necessary to transmit or receive information entered in the backup unit of the reserved part of RAM, or to receive information from the backup unit of the reserved part of RAM of the second computer, through inputs and outputs 34 and 36 or 35 and 37.

Work begins by reading register 3 to determine device availability.

interruptions. Further15 and RAM -information of the array - is written to

1543415 When polling register j on the trailing edge of selector gate 1, block 6 writes information to both computers on device occupancy in registers 3 and 4. Moreover, for the second computer, information is recorded in the category of register 4, which characterizes the employment of the device from the side of the first computer. For the first computer, information is recorded in the category of register 3, which characterizes the fact that the mode organized by the first computer is not finished. The signal of block 6 through the PLI element 28 is perceived by block 5 as the resolution of the first computer to write information about the initial address of the nickname RAM source to registers 10 and 12, about the value of the transmitted register 11. In register 13, information about the operation mode of the device.

By writing information to the register 13 ends the preparatory phase of work. The transmission of information begins after the first computer accesses block 14, in which the first computer writes to block 14 information about the switching of the shapers 20 - 23 so that the shapers 21 and 22 open and the shapers 20 and 23 are closed.

As a result of the re-switching of the shapers 20 - 23, the input-output 36 .. is connected to the data channel through the open shaper 22 and disconnected from the input-output 32 by the shaper 20. Information is recorded in block 14 by the gate signal of selector 1.

Under the control of block 15, the information array is transmitted through input-output 34 to input-output 35. During the transfer of the information array, both computers continue to work according to the program. Synchronization of information word transceiver cycles is carried out by the signal from the output of block 15, from the output of which the signal is fed to the clock inputs of the register counters 10 and 12 to generate the next address value, as well as to the clock input of register 1J to generate the signal for the end of the array transmission. According to this signal, block 15 forms the last exchange cycle in which the last received information word is transmitted to the highway 35. After the end of the last cycle, the signal from block 15, as well as the signal from the register 11, is received by element And 29. From the element’s output, it is an OR OR bomb, as an element to the input of the TPR 5 signal. Signal 33, where

And 29 this signal through ele30 perceived device signal NU. Output signal

And 29, in addition, an interruption request for the TPR block is received, it is fed to the input-output, a response signal is generated, providing an interrupt, and

The input at which the interrupt vector address is received.

After the end of the organization of the program interruption mode, the second computer receiver switches to the maintenance subroutine, in which, having received the contents of the status register 4, through the input-output 33 receives information about the availability of information transmitted through the input-output 35. Next, the computer-receiver performs the following operations:

- writes to the register 13 information about the switching mode of the redundant part of the RAM, while the values

1st and 2nd digits of register 13 are the same;

- writes the switching code to block 14. In this case, the start signal does not start for block 15, since the inhibitory potential comes from the output of block 14.

In accordance with the switching code, unit 14 performs a switching of the formers 24 - 27 so that the formers 24 and 27 are open, and the formers 25 and 26 are closed. The computer receiver writes information about the NU mode of the entire device to the register 13 with the exception of block 14 (8p mode register 13) and proceeds to processing the received information array.

If by the time the program interruption mode is established, the computer receiver is busy solving a higher priority task, then it organizes a single call to the interface device to record information about the device’s occupancy in registers 3 and 4 and continues to work on the interrupted program, after which it reconnects and records the mode NU and processing the received information. In the event of a failure in the mode of transmitting information on channel signals OT7

Vet (SIP) of both channels block 5 organizes the program interruption mode By mistake of accessing the channel for the computer that initiates the exchange.

The operation of block 5 in this mode is similar to the operation of the corresponding block of the prototype.

Claims (1)

Claim A device for interfacing two computers, containing the first and second address selectors, the first and second status registers, the interrupt unit, the state generation unit, the first to third transceivers, the first and second address counter registers, the array counter register, the interface signal generation unit, first and second receiver registers,. the first and second register-transmitters, the first and second OR-elements, the first (AND element, and the control inputs (of the first and second register-receivers are connected to the corresponding control outputs of the interface signal generating unit, the information outputs of the first and Second register-receivers are connected respectively to the information the inputs of the second and first register-transmitters, the recording control inputs of the first and second register-transmitters are connected to the gate output of the interface signal generation unit The gates that gate the inputs of the first and second registers and address counters and the register counter of the array are connected to the gate output of the interface signal generating unit, the information inputs of the first register of the address and register counter of the array are bitwise combined and connected through the first transceiver to the input / output of the device data for connecting to the same input-output of the first computer and with the first information input-output of the second transceiver, the information input of the second register counter address it is connected through the third transceiver with the input / output of the device’s data for connecting to the second computer with the same input and output and the second information input-output of the second transceiver, the inputs of the selection of the first and second register counters of the address • are connected to the corresponding control outputs of the interface signal generation unit, information inputs the first and second address selectors are connected to the address inputs of the device for connecting the outputs of the same name to the first and second computers, respectively, the first output of the first of the second address selector is connected to the selection input of the first and first input of the second transceiver selection, the first output of the second address selector is connected to the selection input of the third and second ~ input of the second transceiver selection, the second outputs of the first and second address selectors are connected to the selection inputs of the first and second status registers, respectively and with the corresponding inputs of the state forming unit, the third outputs of the first and second address selectors are connected to the inputs of the selection of the first and second address register registers a, the fourth outputs of the first and second address selectors are connected to the input of the selection of the register-counter array, the information outputs of the first and second status registers are connected by the control outputs of the device for connecting to the same inputs and outputs of the first and second computers, respectively, the first information inputs of the first and second registers states are connected to the corresponding readiness outputs of the state forming unit and to the first and second input of the first element OR, respectively, the second information inputs of the first The second and second status registers are connected to the corresponding outputs. The interrupt block is interrupted and to the third and fourth. the inputs of the first OR element, the third information inputs of the first and second status registers are connected respectively to the second and first readiness outputs of the state forming unit, the output of the first OR element is connected to the interrupt input of the interrupt unit, the output of the first AND element is connected to the input of the end of the exchange of the interrupt unit and the first input of the second OR element, the gating input of the interrupt unit is connected to the output of the interface signal generating unit of the same name and to the first input of the first AND element, the second input of which the second input of the second OR element is connected to the inputs of the initial installation of the device for connecting the first and second computers, respectively. the fourth input of the second OR element is connected to the output of the initial installation interrupt unit, and the output with the same inputs of the state forming unit and the interface signal generating unit, the first and second inputs and outputs of the organization of the interrupt unit interrupt mode The voltages are connected to the inputs and outputs of the device for 15 connecting to the same inputs and outputs of the first and second computers, which is related to the fact that, in order to reduce the loss of processor time for the transmission of information arrays 20 due to the organization of the mode direct access without blocking the processors, a switching unit, a mode register, a radio vibrator, eight bus drivers are introduced into it, and the first 25 information inputs and outputs of the first, second and fifth, sixth bus drivers are connected to the inputs and outputs of the device for of the first and second computers, respectively, the first 30 outside information inputs and outputs of the third, fourth and seventh, eighth bus drivers are connected to the information outputs of the first and second register counters of address 35, respectively, the second information inputs and outputs of the first and fourth, second and third , fifth and seventh, sixth and eighth bus formers are combined and connected to 40 corresponding inputs and outputs, devices for connecting duplicate memory blocks, response outputs from the first to fourth and fifth of the eighth bus formers are connected to 45 first and second inputs of the response of the interrupt unit and to the inputs of the response of the device for connecting to the same outputs of the first and second computers, respectively, the inputs of the selection of the first and third, second, fourth, fifth and eighth, sixth and the seventh bus formers are connected to the corresponding outputs of the switching unit, the first and second information inputs of the output of the switching unit are connected to the inputs and outputs of the device for connecting to the first and second computers, respectively, the first and the second inputs of the selection of the switching unit are connected to the sixth outputs of the first and second address selectors, respectively, and the output of the exchange direction is connected to the corresponding input of the interface signal generation unit, the information inputs of the mode register are connected to the data bits of the input-output devices of the device for connecting to the same name the discharges of the first, and through the third transceiver - the second computer, the outputs of the operating mode of the mode register are connected to the corresponding inputs of the interrupt unit, m the first output> the operating mode of the mode register is> connected to the corresponding inputs of the blocks of interruption, switching, generating interface signals and with the inputs of the first and second register of receivers, the second output of the operating mode of the register of the mode is connected to the corresponding inputs of the blocks of interruption, switching and inputs of the first and the second register-transmitters, the third output of the mode register is connected to the inputs of the operating mode of the first and third transceivers, the fourth output with inputs of the operating mode of the second transceiver and the first of the second and second registers, address counters, information availability outputs for the first and second computers of the mode register are connected to the corresponding inputs of the interrupt unit, the first output of the initial setting of the mode register is connected to the corresponding input of the switching unit, the second output of the initial installation is connected to the corresponding inputs of the single-vibration interrupt unit, the output of which is connected to the fifth input of the second OR element and to the input of the initial setting of the mode register, the input of the initial setting of the control bits of the transceivers Stra mode connected to the output of the second OR gate.