SU1513462A1 - Device for interfacing computer with peripheral apparatus - Google Patents

Abstract

The invention relates to computing and can be used to build information exchange systems with a computer I / O channel. The aim of the invention is to increase the reliability of the exchange of information by ensuring control of the sequence of exchange commands. The device contains information exchange control block, command register, feature register, status register, address decoder, parity check node, decoder, encoder, OR element, counter, group of elements I. 1 zp f-ly, 3 ill.

Description

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The invention relates to computing and can be used to build an information exchange system with a computer I / O channel.

The purpose of the invention is to increase the reliability of information exchange by controlling the sequence of exchange commands.

FIG. 1 shows a block c-diagram of the device; 2 is a functional block diagram of the control unit; and FIG. 3 is a block diagram of the address decoder.

The device (figure 1) contains a register of 1 commands, the decoder. 2, register 3 features, encoder 4, group of elements AND 5, definition control node 6, element OR 7, counter 8, status register 9, address decoder 10, information exchange control unit 11, inputs and outputs 12-28.

Inputs 12–16 and outputs 23–27 of the device are intended for exchanging the following signals with a computer: input 12 - for receiving signals of the command or address information and data - Channel buses (SHIN-K); input 13 - for the signal of the identifier of the command information - Control from the channel (UPR-K); input 14 - to receive a signal on the 1st channel's channel (control of SIN-KK); input 15 - for the signal of the identifier of the address information - Address from the channel (ADR-K); input 16 - dp of the data identifier signal - Information from the channel (INF-K); output 23 - for the signal of the identifier of the address information - Address from the subscriber (ADR-L); output 24 is for a state identifier signal — Subscriber Control (UPR-A); output 25 -, for the data identifier signal - Information from the subscriber (INF-A); output 26 is for a signal indicating that devices are in communication with a channel; output 27 - for inputting signals of address information, data and subscriber state information (TIR-A).

Inputs 17–20 and outputs 21, 22, and 28 are designed to exchange the following signals with an external device (IU): input 17 for the I / O readiness signal to receive information; input 18 — for signals of data receiving buses; input 19 — for a signal indicating that there are data on the buses for transmission; input 20 - for a signal indicating that data transfer

is finished; output 21 is for data ready signal for transmission; output 22 is for data bus signals; output 28 - for command code signals,

The control block 11 (FIG. 2) contains the elements NOT 29-31, the elements AND 32-40, the elements OR 41-43, the triggers 44-48, the group of elements AND-OR 49, their number is equal to the TIR-A size, the element 50 delays and registers 51 and 52.

The address decoder 10 (FIG. 3) is intended to form the device address, compare the address received from the computer with its own address and form the corresponding signals in the control unit. The address decoder 10 contains the address register 53, the reference element 54 and the AND element 55.

The device works as follows.

At inputs 12 and 14 from a computer, the device address code is supplied, followed by an ADR-K signal at input 15. The address code is compared by comparison element 54 with the address set on address register 53.

The signal from the comparison element 54 through the AND element 55 enters the control unit 11, where it sets the triggers 44 and 47 to be in one state, and the signal RAB-A is generated at the output 26 of the device. In response to this signal, the computer removes the ADR-K signal from input 15. After the ADR-K signal is reset, control unit 11 sets (via NOT 29 and AND 34 elements) trigger 45, forming an ADR-A signal arriving at device output 23 in this case, through the AND-OR 49 elements, the output of the device 27 is permitted to issue the device address code from the address generator 53. The computer, having received the device address code, issues a command code to the inputs 12 and 14 of the device, accompanied by an UTGR-K signal at input 13. By this signal, the command code is entered into the command register 1, trigger 45 is reset in the control unit 11 and after removing the computer the UPR-K signal from input 13 through the elements NOT 30, AND 35, OR 42 is set to one state the trigger 46, forming the signal 5TIP-A, coming through the output 24 of the device to the computer, and through the elements AND-OR 49 to the output of the device 27, it is permitted to issue the contents of the state register 9.

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With the correct parity of the command code and the correct sequence of commands, the contents of register 9 are zero.

The command code is decrypted by the decoder 2, and the command sign is received in the first register register of 3 signs. The third output of the decoder 2 forms the sign of the control command, for example, Define operation, on the second and first outputs the signs of the Write or Read command,

Encoder 4 determines the ability to execute the command. If for executing a command (for example, a command Idle, Refine state, Define operation) you do not need to execute another command, then at the output of the encoder 4 a code 10 is formed, using which the command code is output via the group of elements And 5 to the output 28 of the device and O is written to the state register 9. When the Define operation command is received, the contents of the specified register bit 1 of the command are entered into the second register bit of the 3 signs register. To allow the execution of commands Write in this bit 1, for Read command - O. When a command to define an operation is received, counter 8 records the code for the number of commands read or written, which are executed by this command. When a Write or Read command is received, if the Define operation command has not previously been executed previously, the first digit of the 3 register of the signs does not contain its sign, and the output of the encoder 4 generates code 01, which does not allow the command code to be output to the device 28 via a group of elements And 5, and in the state register 9 is written 1 (sign Failure).

In this case, the computer, together with the UPR-A signal from output 24 to output 27, outputs the contents of state register 9, which is different from zero, which is a sign that the command has been rejected. If the Write or Read commands are received after the Define operation command, the execution of these commands is allowed as many times as the code. recorded in the counter 8. After each execution of the command Write or Read, depending on what is the same

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resolved, the contents of counter 8 is reduced by one and the register is reset by zero value of counter 8

3 signs, 5

If the Write or Read command comes too, it will also be rejected, since the sign of the previously executed control command is cleared (Define operation). After receiving the UPR-A signal from the output 24, the computer sends an INF-K signal to the input 16 of the device. Triggers 47 and 46 are reset by this signal and the signal from output 24 is removed, after which the computer removes the INF-K signal from input 16. Next, the operation of the device is described when executing a Record command. In the absence of an INF-K signal at the device input 16 and in the presence of a readiness signal from the CU to receive information at the device input 17, a trigger 48 is set through the NOT 31, AND 38, OR 43 elements, and an INF-A signal is output at the device 25 output. This computer sprinkles the data on the inputs 12 and 14, accompanying them with an INF-K signal on

five

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input 16. This signal on the element And 40 generates a signal to record information on the register 51, the signal readiness of information for transmitting it to the slave through the output 22 and with a delay

on delay element 50, a trigger reset signal 48. After resetting trigger 48 (removing the INF-A signal), the computer sends the next information to inputs 12 and 14, accompanied by an INF-K signal to input 16, and the cycle of receiving data from the computer is repeated. With the end of the exchange from the VU at the input 20, the status register 9 is entered through the AND 36 element of the control block 11 and the signs have terminated. The device has terminated, the device has terminated, and the trigger 46 is set to one state through the OR 42 element. BUT,

arriving at output 24 and allowing the output of the contents of the register 9 soto with signs to have ended, the device ended through the elements AND-OR 49 at the output 27 of the device. The flip-flop 46 is reset and the UPR-A signal is removed by the INF-K signal received at the input 16, the flip-flop 44 is reset through the AND 33 and the RAB1513462 signal is removed

L pa output 26 of the device, the run cycle

At that

the command is terminated. . When executing the Read command, the data, accompanied by a signal at input 19, comes from WU at input 18 and is entered into register 52 with subsequent 101. issuing the device output 27 at the same time as the INF-A signal at the output 25. Trigger A8, to which the INF-A signal is generated, is set in this case to a single state through the elements AND 37 and OR 43. Otherwise, the operation of the device when the command is executed Reading is identical to the work when writing command.

Claims (1)

1. A device for interfacing a computer with an external device, comprising a command register, a parity check node, an address decoder, a status register, an information exchange control unit, wherein a group of information inputs of the command register is connected to a group of information inputs of a parity node, the information inputs of the address decoder and forms a group of device inputs for connecting to the CdHrudp computer information outputs, while the outputs of the Parity Control node and the address decoder are connected respectively. The first and second inputs of the logical condition of the information exchange control unit, the first output of which is connected to the first information input of the status register, characterized by fidelity of information exchange by providing control of the sequence of exchange commands, a decoder, encoder, register of features, a counter, a group of elements AND, an OR element are entered into the device, the input of the record of the command register is connected to the third input of the logical condition of the exchange control unit and the device input for connecting to the first gating output of the computer, the information input of the parity check node is the device input for connecting to the information output of the computer, allowing the decryption input the address torus is connected to the fourth input of the logic condition of the information exchange control unit 0 five 0 five 0 45 50 55 eight And is the device input for connecting to the second gate output of the computer; the fifth input of the logic condition of the communication control unit is the device input for connecting to the third gate output of the computer; the second, third, fourth, fifth outputs and the first group of information outputs of the control unit information exchange form a group of outputs of the device for connection respectively to the first, second, third gate. inputs, a ready input and a computer information input group, the sixth, seventh, eighth logical condition inputs, the sixth output, the first group of information inputs and the second group of information outputs of the communication control unit form groups of inputs and outputs of the device for connecting respectively to the output end of the transmission , to the transmission readiness output, to the reception readiness output, to the transmission readiness input, to the group of information outputs and to the group of information inputs of the external device, the outputs of elements And group They form a group of device outputs for connection to the group, inputs of the device command code, and the output of the address decoder is connected to the second group of information inputs of the information exchange control unit, the third group of information inputs of which is connected to the group of information inputs of the counter , the group of information outputs of which is connected with the group of information inputs of the decoder, with the group of information inputs of the register of attributes, with the first. a group of information inputs of the encoder, with the first inputs of elements AND groups, the second inputs of which are connected to the first output of the encoder, the second output of which is connected to the second information input of the status register, the third information input and the group of information outputs which are connected respectively to the seventh output and the fourth group information inputs of the information exchange control unit, the ninth input of the logical condition of which is connected to the first input of the OR element and to the first output of the decoder, the second the output of which is connected to the tenth input of the logic condition of the information exchange control unit and to the second input of the OR element, the output of which is connected to the counting input of the counter, the output of which is connected to the installation input of the register of attributes, the information input of which is connected to the third output of the decoder and to the write input of the counter , the group of information outputs of the register of attributes is connected to the second group of information inputs of the encoder. 2, Device POP.1, characterized in that the information exchange control unit contains two registers, five triggers, three NOT elements, nine AND elements, three OR elements, a delay element, a group of AND-OR elements. the first i input of the first element AND is connected to the first input of the second element AND, and is the first input of the logical condition of the block, the second input of the first element AND is the second input of the logical condition of the block, the input of the first element is NOT connected to the first input of the first. the zero input of the first trigger is the third input of the logic condition of the block, the input of the second element is NOT the fourth input of the logic condition of the block, the input of the third element is NOT connected to the first inputs of the third, fourth elements , with the second input of the first element OR, with zero inputs of the second and third triggers, with the input of the delay element and is the fifth input of the logical condition of the block, the first input of the fifth element And is the sixth input of the logical condition of the block, the input of the first register is connected to the first input of the sixth element AND is the seventh input of the logic condition of the block; the first, second inputs of the seventh element AND and the second input of the sixth element of AND are respectively the eighth, ninth and tenth inputs of the logical condition of the block; information inputs of the first register, the first inputs of the elements of the AND-OR group, the group of information inputs of the second register, the second inputs of the elements of the AND-OR group form the first, second, third and fourth groups of information inputs of the block, respectively. 0 five 0 five 0 five 0 five 0 five the output of the fifth element AND is connected to the first input of the second element OR and is the first output of the block, the single output of the first trigger is connected to the third inputs of the AND-OR elements and is the second output of the block, the single output of the second trigger is connected to the fourth input of the AND-OR elements group and is the third output of the block, the unit output of the fourth trigger is connected to the fifth inputs of the elements of the AND-OR group and is the fourth output of the block, the unit output of the fifth trigger is connected to the first inputs of the eighth, ninth element And with the third inputs of the sixth, seventh And elements and is the fifth output of the block, the output of the fourth element And is connected to the input of the second register and is the sixth output of the block, the output of the second element And is the seventh output of the block SH and group of information outputs of the second register respectively form the first and second groups of information outputs of the block, while in the control unit, by information exchange, the output of the delay element is connected to the zero input of the fourth trigger, the synchronous input of which is dinene with the output of the third element OR, the first input of which is connected to the output of the sixth element And, the fourth input of which is connected to the fourth input of the seventh element And, with the second input of the fifth element And, and with the output of the third element NOT, the second input of the third element of the RShI is connected to the output the seventh element And, the fifth input of which is connected to the fifth input of the sixth element And, with the second inputs of the third, fourth element And, with zero output of the third trigger, the synchronous input of which is connected to the output of the first element And and the fifth the trigger, the zero input of which is connected to the output of the third element I, the third input of which is connected to the highest bit of the second inputs of the elements of the I-RSHI group, the synchronous input of the second trigger is connected to you-. the second element OR, the second input of which is connected to the output of the ninth element AND, the second input of which is connected to the output of the second element NOT and to the second input of the eighth element AND, the output of which is connected to the synchronous input of the first trigger, the zero output of which is connected to the third the input of the ninth element I5chet- vert, whose input is connected to the output of the first element NOT, the output of the first element OR is connected to the second input of the second element AND, the information inputs of the first, the second, third, fourth, and fifth triggers are connected to the unit potential bus of the device, the output of the first register is connected to the sixth inputs of the AND-OR group element. fe2 S ; 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