SU1278866A1 - Interface for linking electronic computer with group of peripheral units - Google Patents

Abstract

The invention relates to computing and can be used to connect a computer input-output channel with a group of external devices connected depending on. problem to be solved in a specific configuration. The aim of the invention is to improve the speed. The device contains switches for input and output information signals, switches for input and output control signals, initial sampling node, comparison unit, status registers, command addresses, address offset constants, initial decision address, final decision address, final address of the decision area, data configuration, counter, three S totals, two comparison nodes, a multiplexer, an encoder, a microprogram block (L th control, a group of communication blocks with external devices. 19 ill.

Description

Yu

sj

00 00

but

Claims (1)

One invention relates to computing and can be used to connect the input-output channel of an electronic computer (computer) with a group of external devices connected, depending on the problem to be solved, in a specific configuration.  The purpose of the invention is to improve speed.  FIG. 1 shows the functional scheme of the proposed device; Fig. 2 is a functional block diagram of a firmware control unit; in fig. H - functional layout of the initial sample; in fig. 4 is a functional diagram of a communication unit with an external device; in fig. 5-19 - algorithm of operation of the interface device.  The device contains. (FIG.  1) input information signal switch 1, data register 2, command register 3, condition signal bus 4, comparison block 5, address register 6, data bus 7, switch 8 control input signals, firmware control block 9, initial sampling node 10 , a group of communication blocks 11 with external devices, a counter 12, a configuration register 13, a register 14 of address offset constants, a register 15 of the initial decision address, a register of a 16 final decision address, a register 17 of the final address of the decision area second information input-output 18 of blocks 11, a reg Tr 19 states, switch 20 output information signals, bus 21 signals y; directors, switch 22 output control signals, encoder 23, bus 24 addresses, first adder 25, first comparison node 26, second adder 27, third adder 28, second comparison node 29, multiplexer 30, first information inputs-outputs of 31 blocks 11.  Firmware control block 9 contains (FIG. 2) a decoder 32 of the starting address code, multiplexer 33, address register 34, multiplexer 35, buffer memory 36, counter 37, OR element 38, multiplexer 39, microprogram memory register 40, micro-command register 41, multiplexer 42, counter 43 cycles, generator 44 pulses.  Node 10 of the initial sample contains (FIG. H) switch 45, amplifier receiver 46, encoder-decoder 47, trigger 48, element I 49, amplifier transponder 50.  Block 1 contains (FIG. 4) command register 51, program block number 52 of register 11, array register 53, data register 54, multiplexer 55, block 11 address register 56, comparison node 57, subscriber address register 58, multiplexer 59, counter 60, microinstruction register 61, trigger 62, multiplexer 63, counter 64, firmware memory 65.  The device works in the following way.  The information input (input of block 1) of the interface connects the buses of the SHIN-K channel, through which data, commands, and addresses are transmitted from the computer to the interface.  Control buses from the TIR-QC channel are connected to the same input.  To the information output of the interface, the buses of the TIR-A channel (switch output 20) are connected, through which data are transmitted to the computer, their own address and information about the state of the interface device.  To identify information located on SHIN-K and TIR-A, and for interlocking the signals, the identifier lines are used (address from DAR-k channel), control from WP-K channel and information from info-k channel, LAR-A address , the management of control / and information from the interface.  The identifier lines are connected respectively to the input and output of the switches 8 and 22 of the interface device.  The control lines from the computer are connected to the input of the switch 8 to control the selection of the interface device, scan and control the connection (operation of the RAB-K channel), enable sampling from the RVB-K channel and block from the BLK-K channel.  The control lines from the interface device (RAB-A operation and the requirement for maintenance of the TRB-A from the interface device) are connected to the output of the switch 22.  To the input and output of the sample connect the sampling line VRB-K from the channel and the sampling line VBR-A from the interface device.  To the input of the switch 8, the SMS-K state transition lines are also connected from the channel to block the possibility of disconnecting or connecting the interface device at prohibited points in the operation of the computer I / O channel.  Any signal from the computer canap on.  lines are considered valid when a RAB-K signal is present. Subscribers are connected to I1 units by means of communication lines with subscribers.  The initiator of the interface is always a computer.  A coman is used to operate the device. dy: Write, Read, Write current address code, Write code. configurations, Write the code of the address offset constant, Write the code of the initial decision address, Write the code of the final decision address, Write the code of the final address of the decision area, Write the code of the program number, Start the decision.  The list of commands belonging to the interface device is written into the decoder 32 of the starting address of the firmware control unit 9.  The decoder 32 starting address converts the code of the input command in the corresponding address of the first microcommand firmware.  The program of operation of the firmware interface device is recorded in the microprogram memory 40 of the firmware management unit 9.  The Record command records information to subscribers.  At the end of the recording comes the command Start a Slip.  At the end of the decision, a signal is issued to the computer channel and the TRB-A signal is sign that the Subscriber has finished.  The Read command is used to 35 resolve solutions from subscribers.  The commands Write configuration code and Write current address code are used to write information to counter 12 and configuration register 13.  The command Write the code of the final address of the decision area serves to set the coordinates of the decision area of the subscribers.  Conventions of the device operation algorithm: EC bytes (3) - set when the device is busy executing the decision; BS (4) is established in response to the termination of data transmission from the channel or if data transfer is not required; BS (5) - is established when translating the interface blocks with an external device (BSVU) BS BS OBU OBU OBU OBU XX TZ PV / P. BS BS VRU RK ADI VA6 STs4 RPA RA3 ROCK COM ZP KBL KM US AP DB DM AB AB K Adr from the State Not Ready in Ready, or by.  the end of the signal decision process The decision is terminated from the BSVU, or if no data transfer is required; set when a device fails: the SHIN-K parity is incorrect, the command is rejected, BSVU are not ready; set if there is no command in the command list; set if the command is rejected; set if BSVU are not ready; it is set if an error on SHIN-K; set if hardware failure.  interface from the ARK7 VBR-KU interface; Idle command 48 capture; command Check input; subprogram; byte state; updated status byte; selected device register; command register; BSVU ready; issuance of the address from register 6 of the interface of SHIN-A; 43 cycle counter; data register; registry address 34; the decision is over; team; record; end of block; end of array; device mate; adapter software address; dpina data block; the length of the array of data blocks; subscriber.  The code entry of the initial and (Anp) and the Record of the congruent decision code (Ac) are used to set the initial and final coordinates of the decision area, respectively.  The Write Address Address Shift Code (Asm) command is used to set the offset of the starting coordinate of the decision area relative to the beginning of the decision area of the previous decision. The Write Current Address Address Number (Lt) code is used to select an individual subscriber in the decision area of subscribers.  The Write a program code command is used to assign program numbers to blocks 11 instead of physical addresses stored in address registers in blocks 11.  Before the Read or Write command, the following commands should be written: Write the code of the address offset constant, write the code of the initial decision address, Write the code of the final address of the decision, Write the code of the final address of the decision area, Write the configuration code, and Write the code of the current address of the subscriber.  To perform the pa-algorithm.  interface bots use the following set of commands of the firmware control block 9 conditional jump, jump to the subroutine, jump on the decoder 32 of the starting address code, go on address register 34, repeat the cycle on the loop counter 43, return from the subroutine whose address is stored in the buffer memory ti 36, counter loading 43 cycles, continue unconditional jump, jump to FF firmware addresses. , F and O, whereby the routines for processing interrupts from the computer channel, for example, disconnecting from the interface channel of the master computer, start.  The control; signals for executing the commands generates multiplexer 35 depending on the iOT input conditions and on the input control code from the output of microcommand register 41 (subsequent address; i address).  The transition to the subroutine with the address O occurs under the influence of the signal from the block 11 on the input of the multiplexer 39 of the block 9 of the program control.  The microcommand address at the output of the element OR 38 is always incremented by one by the counter 37.  The synchronization unit 6 of the control unit 6 is synchronized by a common generator of 44 rectangular pulses.  All commands from the computer begin with a sequence of signals from the initial sample.  At the initial sampling signal sequence stage, the FBG-K signal is captured.  If the interface device is not turned on, the VBR-K signal from the output of yatatopa 45 again goes to its input and from the output of switch 45 it goes to the output of node 10 of the initial sample.  If the priority of this device is lower than the priority of other devices, the FBG-K signal passes through the switch 45 and goes to the next device, whose priority is higher.  If the interface device is switched on and its priority is higher, then the VBR-K signal from the output goes to the input of amplifier 46, and from its output goes to the input of the encoder-decoder 47 and to the input of the And 49 element.  If the trigger 48 is in the state of one (the device does not recognize the address), the VBR-K signal, having passed through the element 49 and the amplifier-transmitter 50, becomes the VBR-A signal and goes to the input of the switch 45 and further to the computer channel.  If the trigger 48 is set to zero (the device identifies the address), the VBR-K signal does not pass to the computer channel and the decoder 47 generates signals- according to the expressions VBR-KU RAB-K L VBR-K, / RVB -K VBR-KY VBR-KUL match address L odd address A ADR-K.  Installation of the trigger 48 VBR-KN V (TRB-A L RAB-K L RVB-K), selective reset Sh5-K L BLK-K L K EVM L K K, reset system RAB-K L BLK-K L KAL: L K Computer, disconnection from the interface |: DB-K L RAB-A A VBR-K.  ADR-K L AUA LC computer, where the computer - the device is connected to the computer; KA - the device is connected to subscribers.  The trigger 48 is reset from the firmware control unit 9 by resetting the RAB-A signal.  When the interface device is transferred to the mode of joint operation with a computer, the firmware control unit 9 goes into the mode of the FBG-KN signal from the output of the initial sampling unit 10.  The signal VBR-KN through the multiplexer 39 is fed to the input element OR 38, to another input which receives the address of the microcommand from the output of the multiplexer 33.  The modified address of the next microcommand from the output of the OR 38 element is fed to the input of the counter 37 and the memory address of the 40 microcommands.  Firmware control unit 9, on command, sends to the stack the address of the return command in the buffer memory 36, proceeds to run the device address and sets the output of register 41 of the microcommand to the control signal RAB-A through the switch control bus 21 via the switch 22 control output signals are fed to the output of the firmware interface device and further along the buses of the computer channel.  According to the control signal, the output of the device address from the register register 41 microinstructions is the address of the device from the register 6 addresses via bus 7 data through the switch 20 of the output information signals via BUS-A enters the computer.  The address of the device on the BUS-A is accompanied by an ADR-A identifier which, from the output of the register 41 of the micro-commands, via the control signal bus 21 goes through the switch 22 of the control output signals to the computer.  After checking the address of a device assigned to TIN-A, the computer channel in response to the TIR-K buses issues a command byte, which through the switch 1 of the input information signals enters the input of the register 3 of the command.  After issuing the command code from the BUS-K bus from the computer channel to the input-switch 8 of the input control signals, a signal UPR-K is received, which is fed to the input of the register of 3 commands, and the bus 4 signals the conditions to the input of the multiplexer 42.  The signal UPR-K unit 9 microprogramme control sets the input.  Register 3 commands the write enable control signal, and the command from the output of the switch 1 inputs information signals is recorded in the register 3 commands and from its output enters the input of the decoder 32 of the code of the initial address of block 9 of the multi-control program, which resets the ADR-A identifier.  By resetting the ADR-A identifier, the subprogramme is completed. Issuing the address of the firmware interface device and on the command Return from the subroutine to the address. the next firmware from the output of the buffer memory 36 through the multiplexer 33, the element OR 38 is fed to the input of the memory 40 of the firmware.  The firmware control unit 9 proceeds to the continuation of the algorithm to the analysis of the received command from the computer under the conditions at the inputs of the multiplexers 39 and 42.  The result of the analysis of the received command from the computer from the output of the field control register of 41 microinstructions over the data bus 7 is recorded in the state register 19.  The firmware control unit 9 goes to the subroutine Issuing a status byte with storing the return address in the buffer memory 36.  For this routine, control signals are chic.  21 control signals the status code from the register output 19 of the state through the switch 20 of the output information signals enters the computer channel.  The status byte is accompanied by the UPR-A identifier, which is set by the micro-command in the control field of the micro-register register 41 and through the switch 22 of the control output signals enters the computer channel.  If the polled units are 1 1 out of work, t. e.  At the input of the multiplexer 39, from the output of the register 61 of the mandates of the block 11, a signal is received Not ready, then the address register 34 of the micro-instructions block i1 is written to the register 34 of the address of the microprogram control block 9 from the output of the micro-command register 41.  Firmware control unit 9 issues a computer status byte to the TIR-A of the channel of a computer with a Not Ready sign.  After issuing a status byte with a sign of unavailability, block 9 of firmware is.  governing by the command to navigate through the address register 34 enters the algorithm for waiting for blocks 11 and issuing a status byte with the indication The adapter is ready by the TRB-A signal.  If the status byte is zero, m. e.  the command is received, then the microprogram control block 9 by the command Transition using the decoder 32 of the starting address code goes to the algorithm for executing the command from the computer, which from the register of 3 commands through the decoder 32 of the address code, multiplexer 33 and the OR element. 38, under the control of a signal from multiplexer 35, is fed to the input of the microprogram memory 40 as the source of the address of the next command.  Commands that do not require data transfer are completed in the initial sample, for example, the Test I / O and Idle commands.  Consider the execution of basic commands, the command Write the code of the program number.  A computer channel through 111IN-K to the input of the switch 1 of the input information signals exposes the code of this command and accompanies it with the UPR-K identifier by which the command code is recorded in the register 3 of commands.  From the output of the register of 3 commands, the command code enters the input of the decoder 32 of the code of the initial address.  By the UPR-K signal, the firmware control unit 9 analyzes the received command and sends to the cycle counter 43 cycles a constant that corresponds to the number of information bytes received in the data register from the computer channel.  At the output of the micro-command register 41, the control signal is output from the control. Setting the flip-flop 62 of the block 11 to zero.  The signal from the output of the trigger 62 controls the multiplexer 55, connecting the register 56 of the block 11 to the input of the comparison node 57, and the block 11 enters the mode of waiting for the signal from the output of the comparison node 57 (matching the address code from the bus 24 of the address and the code stored in register 56 block addresses 11).  In addition, according to the control signals from the register 41 of the micro-commands of the firmware control unit 9, the configuration register 3, the address offset constant register 14, the initial decision address register 15, the final decision address register 16 and the decision register 17 of the final address of the decisive area, the ADR-A identifier is removed, to which the computer channel responds by resetting the UPR-K signal, according to which the microprogram control unit 9 from the state register 19 through the output information switch 20 exposes to IMiH-A the status byte Neither, but on the output of the switch 22 of the output control signals sets the identifier ZT1P-A and waits for a response from the computer channel to the transmitted status byte.  If the status byte is zero, then the channel sends an INF-K signal, via which firmware control block 9 resets the identifier UBR-A and removes the status byte from BII-A.  The initial sampling device of the interface completes.  The channel resets the INF-K identifier, to which the microprogram control unit 9, from the output of the microcommand register 41, sends an INF-A signal through the control output switch 22 and waits for the data transfer from the channel.  Data input 2 from the computer channel through the switch 1 of the input information signals enters the data byte and records the data register 2 using the INF-K signal.  Using the INF-K signal, the firmware control unit 9 checks the parity of the information data received in register 2.  The signal from the register output of 41 microinstructions in the counter 12 from the output of the data register 2 records the code of the physical address of the block 11.  Then, the firmware control unit 9, via the control output switch 22, outputs the INF-A signal to the computer channel.  The computer channel responds by dropping the INF-K.  The code of the physical address of the block 11 from the output of the counter 12 through the first 25, second 27 and third 28 adders is fed to the input of the encoder 23.  From the output of the encoder 23, the code of the physical address of the block 11 enters via the address bus 24 to the inputs of the nodes 57 comparing all the blocks 11.  Unit P, in which the code at the input coincides with the code arriving at the other input of the comparison node 57 through the multiplexer 55 from the output of the register 56 of the address of the block 1I, outputs a comparison signal received at the input of the multiplexer 59.  Under this condition, the block 11 from the output of the register 61 microinstructions to the bus 4 of the condition signals outputs a ready signal to receive the program number of the block 11 from the data bus 7 to the register 52 of the program, many block numbers I1.  Then unit 11 enters the signal standby mode. The program number from the output of register 41 of the microcommands of microprogramming control unit 9.  Firmware control unit 9 resets the INF-A signal.  The computer channel places on the SHIN-K a program number code and accompanies it with an INF-K signal, by which this code is written to data register 2.  The microprogram control unit 9 aggalizes the parity of the received KOI and signal, after which, via the control signal bus 21, outputs a output signal from the register 2 of information data to the data bus 7.  From bus 7 danIUIX information is fed through the second information input-output 8 to the inputs of all groups of the block.  eleven.  From the output of the register 41 microinstructions of the microprogram control unit 9 to the input of the multiplexer 59 of the block 11, the condition of the program number is received.  According to this condition, the multiplexer 63 receives the address code of the microcommand to the inputs of the counter 64 and the memory 65 of the microprogram.  From the microprogram memory 65, a selected microcommand is written to the micro-command register 61 by the clock signal received from the control signal bus 21.  From the output of register 6 microinstructions, a control signal and a prog code arrive at the input of the register 52 of the program number, the frame number from the data bus 7 is recorded in the register 52 of the program number, after which the selected block 1 goes into the standby mode of the new command.  Microprogram control unit 9 exposes the INF-A signal to the computer channel and waits for new data from the computer channel.  The process is cyclically traced until the registers 52 of the program number of all I1 blocks are completely filled up to the point in time when the computer channel responds to the INF-A signal of the interface device with the UPR-K signal and receives a signal from the computer channel. UPR-K, microprogram control unit 9 removes the INF-A signal, after which the computer channel removes its UPR-K signal.  The firmware control block 9 from the state register 19 through the switch 20 of the output information signals sends to the computer channel the status byte of the execution of this command and accompanies it with the UPR-A signal.  The computer channel resets the UPR-A and RAB-A signals and goes into standby mode from the computer channel of the new command.  After filling out all registers 52 of the program number of blocks 11, the command to write information to registers 13-17 follows.  Writing information to these registers is of the same type.  Each of the commands, as when writing information to the program number register 52, begins with a sequence of signals of the initial sample and ends with the transfer of a state byte to the computer channel, resetting the UPR-A identifier and resetting the IFK-K identifier by the computer channel.  The microprogram control unit 9 sends the INF-A signal to the computer channel and waits for the INF-K identifier from the computer channel, through which the first byte of information is recorded from the computer channel into the data register 2.  In response to the U1F-K signal, the firmware control unit 9 sends the INF-A signal to the computer channel, shifts the data code in the data register 2 by one byte, decreases by one the contents of the loop counter 43, checks the reset of the loop counter 43 and goes to standby of the INF-K signal from the computer channel, according to which y the second byte of information is recorded in the data register 2.  The process is repeated cyclically until the counter is reset to 43.  When the last zero is cleared. A control signal from the output of the register of 41 micro-instructions to the selected register (registers 13-17) is recorded from the register 2 of the data.  The execution of each of these commands ends with a sequence of data transfer signals with the output of a status byte and indicating the device terminated.  Commands Record and Read.  Each of these commands has two modes - word-by-word and group exchange.  The mode is indicated in the command code.  When the word by word is at the same address recorded in the counter 12, one data block is transmitted, after which this command ends.  The next address is set by a new command.  In a group exchange command, only the starting address of the array of data blocks is specified, and subsequent addresses of the array of data blocks are formed at the interface itself.  Team . Word record.  At the initial stage, the command is executed in the same way as the preceding commands.  After writing to the counter, 12 codes of the current address of the abbot at the output of the first adder 25, a code (A, g) is generated as the sum of the codes contained in the counter 12 (A) and register 15 of the initial address of the decision (A,), t. e.  A ,, A, +, the address code () at the output of the first adder 25 is fed to one input of the second adder27, to the other input of which the address code of the address offset (A) is received from the register 1 4 of the address offset constant.  At the output of the second adder 27, an address code is generated (, A ,,,, arriving at one input of the third adder 28 and to the input of the second comparison node 29, where it is compared with code (A) from the output of register 17 of the final address of the deciding region.  A signal from the output of the second comparison node 29 controls the multiplexer 30.  Depending on the result of the comparison, the required code is fed to the input of the third adder 28 from the output of the multiplexer 30.  The output code of the third adder 28 (A) is formed according to the law A. , A ,, 4 l. The address code of the subscriber addressed by block 11 formed at the output of the third adder 28 is fed to the input of the tuner 23 and via the address bus 24 to the inputs of the subscriber address registers 58 of all blocks 1.  At the output of the encoder 23, depending on the configuration code diya and the address code from the output of the third adder 28, the program number of the block number 11 is generated, which is. bus 24 address goes to the inputs of nodes 57 comparison of all blocks 11.  At the other inputs of the comparison nodes 57, the code of the program number of this block 11 from the register 52 of the program number is in effect.  One of the blocks 1 recognizes the code-program number of the block received from the bus 24 of the address and generates a match code on the multiplex on 59 of the recognized block 11.  On this signal, the selected block 11 from the register 61 microinstruction output exposes a ready signal to the bus 4 conditions conditions.  From the output of the microinstructions register 61 to the input of the subscriber address register 58, a signal is received by which the subscriber address code from the address bus 24 is written to the subscriber address register 58. Then the selected block 11 waits for control signals from the firmware control unit 9.  Parallel with the formation and recording of the address code of the subscriber in the register 58 of the address of the subscriber in register 2, the dunn forms the command code for block 11, which enters 18 data from the output of register 2 to input-output 18 of all blocks P from the microprogram control unit 9 On the control signal bar 21, the adapter command identifier is sent to the input of multiplexer 59 of all blocks 11.  On this signal, the selected unit 1 from the data bus 7 to the command register 51 writes the command code and waits for the array length identifier 9 from the firmware control unit 9.  In the data register 2, the next information word is formed and, via the control signal from the firmware control unit 9, the data bus 7 is fed to the inputs of the G1 blocks.  The same control signal is fed to the input of multiplexer 59.  The addressed block 1I generates a signal Reception of the array length code, according to which the array length code consisting of the length of the array of data blocks and the length of the data block is written to the register 53 of the array from the data bus 7.  Then, addressable unit 11 proceeds to awaiting control signals from unit 9 of g-program control.  In the data register 2, the next data word is generated by a command from the firmware control block 9 via bus / data on input-output 18 to the inputs of blocks 11 and on the control signal from the register of micro-commands 61 this data is written to the data register 54.  Then the contents of register 53 of the array is reduced by, its zeroing is checked.  From the output of the register of 61 microinstructions, control signals are sent to the subscribers, and from the register 54 of the data on input-output 31, the in-subscribers record data.  If the contents of register 53 of the array is zero, then addressable block I1 proceeds to wait from the block 9 of the firmware control for identifiers Address or End of Exchange.  If the contents of register 53 of the array is not zero, then the process of entering data into subscribers is cyclically repeated at the addresses from counter 60 to about vol. nuli  The addressed block 11 in the block 9 of the firmware control issues a signal to the end of the operation, and the block 9 of the firmware controls proceeds to the sequence of the end of the specified command from the computer channel.  The group entry command on the initial ethane is made the same as the Word record command.  After transmitting to the first address of the first data block by the control signal from block 9 of firmware control +1 of the counter 12, one is added to the contents of the counter 12 and the next subscriber address is selected.  At the outputs of the encoder 23 and the third sum of the matrix 28, new addresses of the block 11 and the subscriber served by this block 11 are formed.  The process is repeated cyclically until.   resulting in a reset signal from the output of the second comparison node 26 in the counter 12.  The next step is selected in the V coordinate, and the contents of the counter 12 in the X coordinate are set, to zero. The process is repeated cyclically before and, then from the blocks 1 to the microprogram control block 9 receives the conditional signals about the end of the execution of the specified command.  Firmware control unit 9 performs a sequence of channel termination signals.  COMPUTER.  After writing to the subscribers, via the data block 1 from the computer channel, a decision start command is received, which is sent to the multiplexers. 59 of all units 11 via the bus 4 condition signals from the output of the microprogram control unit 9 no signal is received Start decision.  This signal from the output of the register of 61 microinstructions to the subscribers receives a control signal about the completion of the exchange cycle and permission to begin the decision.  The firmware control unit 9 outputs the computer bytes to the computer channel and enters standby mode from the conditional signal units 11 End of the decision.  If at the time of the termination of the decision a signal from the BBR-K channel is missing, then the status byte with the sign of the Subscriber has terminated is output to the channel by a Signal request from the TRB-A subscriber.  If the VBR-K signal is not cleared, then after the end of the decision, the sign of the Solution will be completed when the second byte is sent to the computer channel.  The Word Reading and Group Reading commands are similar to the Word Recording and Group Recording commands with the difference.  that the data stream comes from subscribers through blocks 11 to data bus 7 and then through the switch 20 of the output information signals to the computer channel.  After the data reception has been completed by the command of the firmware control unit 9, from the state register 19, the status channel byte comes to the computer channel with the sign “Channel has finished” and the Device has finished.  If the status byte is received by the computer channel, the firmware control unit 9 proceeds to wait for the next command from the computer channel.  If the command Remember state is received from the computer channel, then the firmware control unit 9 switches to the status byte input mode at the TRB-A signal.  If commands that are not included in the list of commands of the interface device are encountered, they are not executed and a status byte is issued to the computer channel with the indication Special case.  If it is necessary to re-solve the same problem with a shift in the decision area, a new array of addresses with a shift is formed.  In this case, the address offset constant code is written to the register 14 of the address offset constant, which is summed in the second adder 27 with the code of the current address of the un-shifted solution.  Then, the array of subscriber addresses is formed in parallel with the entry of information into the subscribers according to the described algorithm.  The problem is solved in another area of the decisive area of additional costs for the formation of a new address array in computers.  An apparatus for interfacing an electronic computer with a group of external devices, comprising an input information signal switch, a control input signal switch, a control output signal switch, a data register, an initial sampling node, a comparison unit, an instruction register, an address register, an output information switch signals, status register, counter, configuration register, encoder, firmware control block, group of communication blocks with external devices, and information The input of the input information signal switch is connected to the information output of the electronic computer, the output switch of the output information signals is connected to the information input, the input of the electronic computer, the switch output group of the control output signals is connected to the gate group of the electronic computer, switch information input groups input control signals connected to a group of gates of an electronic computer, input and output samples of the initial sampling node are connected respectively to the output and access of the electronic computer; the first information inputs of communication blocks with external devices of the group are connected to the corresponding 1 m information inputs of the external devices of the group, first code outputs, address outputs and first code inputs of communication blocks with external devices of the group are connected to the corresponding code inputs, address inputs and code outputs, respectively, of the external devices of the group, with a group of outputs micro-operation of the firmware control block is connected to the information output of the control output switch, the gate inputs of the output information signal switch and the status register, the first information input of the initial sample node, the information input of the address register, the write register write enable input, the second code inputs of communication blocks with external devices of the group, with the installation input and into the house of the register of the configuration register, with the recording input and the counting input of the meter, with data register shadows and with the control input of the control input switch, the first output of which is connected, to the second information input of the initial sample node, the third information input of which is connected to the output of the comparator unit, the enabling input of which is connected to the second output of the control input switching signals third output which is connected to the input of the record of the register of commands, the output of which is connected to the command input of the firmware control block. the group of inputs of logical conditions of which are connected to the information outputs of the initial sampling node, the fourth output of the control input switch, the output switch of the information input signals, with the second code outputs of communication units with external devices of the group, the second information inputs of which are output information signals, the information input of the status register, the output of the data register, the output of the address register and the first information the second input of the comparator unit, the second information input of which is connected to the information input of the command register, the output switch of the information input signals and the information input of the data register, the record input of which is connected to the fourth output of the control input switch, the output of the status register is connected to the second information input of the output switch information signals, characterized in that, in order to increase speed, three adders, two comparison nodes, a multiplexer, the address offset constant constant register, the decision start address register, the decision end address register, the decision address end register, the output of the data register is connected to the information inputs of the address offset constant register, the decision start address register, the counter, the decision end address register, and the end address register the decision area, the configuration register, the group of outputs of the micro-operations of the firmware control block is connected to the inputs of the installation and the inputs of the record of the register of the offset Neither the address, the register of the initial address of the solution, the register of the final address of the solution, the register of the final address of the solving region, the outputs of the register of the initial address of the solution and the counter are connected to the first and second inputs of the first adder, respectively, the output of which is connected to the first inputs of the first comparison node and the second adder, the second the inputs of which are connected to the outputs of the register of the final address of the solution and the register of the constant of displacement addresses, respectively, the output of the second adder is connected to the first inputs of the second comparison node and the third adder, the address inputs of communication units with external devices of the group are connected to the third adder and encoder, the output of the configuration register is connected to the first information input of the encoder, the second information input of which is connected with the output of the third adder, the second input of which is connected to the information output of the multiplexer, the control input of which is connected to the output of the second comparison node, the second input of which is connected to the output of the register of the final address of the decision area and the information input of the multiplexer, the output of the first comparison node is connected to the recording input counter. 1 fftta Q fft / eyj7ff j Initial 6bibopKCt  J 0A 6 a L ffC G9 Bcr / ffcft ct ff / y- A / 7 / yeah / ff / Iff / y-it-ff L / 70. WITH Mfft / rcr ff / r7 / ea fff / c - / g Sco 7C3 npOSDdMUCI (Bom oi oopeca and proо oo / o neno alno vial1borki PA 3 -7 // O  1 6C / 5l 1 errr O f / c / a / f ffC / 7/7 ffCW- / BC / S / 1 /7.f7. BC f9 Sat / uas P tzhhv Bf1 Fi & .7 3cfH. fio / f. Zam am C-rOBO / f0M. C / 77ff CO 3af /. asl  xWy  / ifff3cfM (/ Cyt / y / 7f7 J ewfftyf / c SC a / 77 73 u / c / f - ct jetr / of a TPG-A B2) 12D.2 / 7/7 BCfd / 7/7. ffA6 TPB-A O P / 1B - // 7 6Ff PA3 laso / 7/7. 6C / 3/1 BA6 6f1 c SEC. visas Bt fffovct /7./7. /9 6 With G9 fftf / ff & f Si 16f / c-fff WffffC FA CffpffcPf S-A 5 / V / 6С / 5/1 ГЗ (В 8 О but 10VO KoMGffba Refine 70 7 state BS / 5/1 Short sample pic.p Download RCA - reading sc. Issuance of the subscriber's address to 24 Issuance of given Wb / l on tires-A Issuance of Cffpoc -1 sch. Cycle 3 Reset lAHcp-A BS 14-1 1 BS / 51 7 Mid. tsikhla Ts DN. npl hf} / n Team 1 en1 ee.73 8NZ 8NZ Choose & register 14reg 77 g Choose Cv. Register / J Reset HHcp-fi Receive in BCJ5 RD2 1 W 8NZ V Select register 15 Select register J6 Reset GZHVCh8 0 Reset ra5-A BSM 7 l -1 account 43; Record from RD2 to VRG Insr-A 0 8NZ /7.D receive data words. Check in with RD2 B 72 ijcm. 62 /7./7. weak given // 6 / x Record with RD2 6 AP52 16P Commands to add AP, DBMDI Pp. Reception of the word given} ( Bring with Record from РД2 to 72 РД2 В 12 Address. subscriber usggsnow Record with, РД2 В pp prmem words given // 6 / L Record with РД2 д Fblv, 16 3S8 Address Record 19M Reading data from aSoH Gotov AB B 54 mi addresses