SU1425697A1 - Computer interface - Google Patents

Abstract

The invention relates to computing and can be used in highly reliable computing systems with redundancy at the level of computers for interfacing them through an input-output interface. The purpose of the invention is to expand the functionality by eliminating the situation of inoperability in the absence of a ready signal at least one of the interfaced computers and using the waiting time for responses on the request of the computer of one of the interfaces to organize the exchange on the request of the computer of another interface. The purpose of the invention is achieved through the introduction of a device containing input and output buffer registers, a group of elements AND, a group of elements AND-OR, two elements AND-OR, a switching unit, two triggers, two elements NOT, a request processing unit, a second request processing unit and block information management. The introduction of the second query processing unit allows organizing parallel reception of commands from the computer of both the first and second interfaces. The introduction of the information transmission control unit allows waiting times for responses on request of the transmitting computer to be used to exchange information on request by the transmitting computer of another interface. 1 il. i (L 4 ND CD O5 CO

Description

The invention relates to computing and can be used in highly reliable computing systems with redundancy at the level of computers (VM) for interfacing them through an input-output interface.

The purpose of the invention is the expansion of functional capabilities by eliminating the situation of inoperability in the absence of a ready signal of one VM and providing1 and the possibility of using the waiting time for responses on the request of the VM of one of the interfaces to organize the exchange on the request of the VM of another interface

The drawing is a diagram of the device.

The device contains output 1 | and input 2-buffer registers; switching unit 3, first 4 and second 5 triggers, first 6 and second 7 elements AND-OR, group 8 elements AND - 1ZHI, first 9 and second 10 elements NOT, group 11 elements AND, first 12 and second 13 query processing units , the information transmission control unit 14, the first 15 and second 16 elements of the NLI, the Device also has the first | 17 and second 18 information inputs of the First 19 and second 20 information outputs, the first 21 and second 22 groups of control outputs, first 23 and b 24 groups of control inputs (a combination of the first and second inputs of the device outputs with tires expands the channels of the first and second interfaces, respectively, the control group (qix during the exchange in the first 25 and second 26 information inputs and outputs of the device, first 27, second 28, third 29, fourth Ills fifth P2 and sixth OTK outputs of the control unit transferring information, the first 30, second 31 and third 32 outputs of the switching unit, the outputs of the HV request signals of the first 33 and second 34 request processing blocks, the first 35 and 36, the second 37 and 38, the third 39 and 40, the fourth 41 and 42 outputs of the first and the second block processing requests, respectively, the first 43 and 44, the second e 45- and 46 informational inputs of the first and second processing units. requests

The device works as follows.

Before starting the triggers 4 and 5 in the zero state, at the outputs

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elements NOT 9 and 10 potentials of a single level.

Groups of computers can be connected to the device, and at the same time one VM transmitting and receiving them of the VM can be paired. The initiator of the start of operation of the device is the transmission of the VM. Requests for data transfer from the VM of the first interface are received in the first request processing unit 12 via buses 23 and 24, respectively.

The work of the query processing units is similar, therefore, we consider the function-. rationing one of them - the first. Requests on the bus 23 are received on the first group of 43 information inputs of the block. In the block, a request with an external priority is defined and, according to the group 21 of the control outputs, the device-f is sent to the required VM as a signal to connect this VM to the device for information transfer. After that, in the request processing block, the processing of other requests is blocked until the service is completed for the request of the selected VM,

On the first information input 17 of the device, a command from the transmitting VM goes to the second group of information inputs. 45 block and is interpreted in it as VM numbers of the second interface 5 participating in the exchange as receiving, and the number of information bytes transmitted. The unit level signals corresponding to the VM numbers of the second interface. from the outputs 33 of the request signal, the VM blocks are transmitted to the corresponding outputs of the second group 22 of the control outputs of the device. The unit-level signals from the corresponding outputs go to the VM of the second interface c. The quality of signals connecting VM data to a device for receiving data, the output machines confirm their readiness to receive data via the bus 23p which goes to the first group 43 of the information inputs of the block and causes the zero level signal to be generated at the control output 37 of the block.

When working as part of an asynchronous computational combination, a situation may arise when a VM, which is transmitting in one interface, is included in the number of other interfaces that are requested by the VM. However, Sov 31425697.

The peMeHitbie VMs have independent channels during 32, which means that the input-input and output information, as a result, the buffer register is occupied. With the appearance of this signal in switching unit 3 a single level signal is generated at output 30, which is fed to the inputs of a group of 11 elements And where allows the transfer of bytes

where such a situation is resolved.

At a certain point in time in one of the blocks (12 or 13), the request processing will be accepted.

days of readiness to receive from all host VMs. Suppose it happened in block 12. Null information is received via bus 37 to the input of the block. 14 of the information transfer control, to another input of which, via the bus 35, the unit code from the request processing unit 12 is received. At the output 27 of the information transmission control unit, a data transmission control signal is generated from the first interface to the second, which is fed to the inputs of the switching unit 3, a group of 8 AND-OR elements, the first 6 and the second 7 OR elements. Based on this control signal and the permitting potential, a single level signal is generated at the output of the HE element 9 in the switching unit 3. The input buffer register is free, which is transmitted over the bus 32. The signals of the single VM are received at the inputs of the I-SHSh 6 element, and receiving data

This is done on buses 27, 32 and from the output of the element NOT 9. A signal from the output of the element AND-OR 6 sets trigger 4 to one state. The signal of a single level from the output of trigger 4 via bus 21 is sent as a request for a data byte. In response to the request, the transmitting VM is exposed to the input 17 bytes of data, accompanied by a signal at the corresponding input of the bus 25. This signal through the OR 15 element is fed to the inputs of the trigger 4, the HE element 9, the switching unit 3 and the information transfer control unit 14. Trigger 4 goes to zero. In switching unit 3, a single level signal is generated at the output 30 and is fed to the inputs of a group of 8 AND-OR elements, where it allows writing the data byte from input 17 to the input buffer register 2. In the information transfer control unit 14, the contents of the transmitted byte count are increased.

The signal of the zero level from the output of the element 9 is fed to the input of the switching unit 3 and causes the formation of a signal of the zero level on the output 2 from the buffer register to the output 1 buffer register. The same signal goes to one of the inputs of the AND-OR 7 element, to the other input of which a single level signal is output from output 27 of block 14. A single level signal from the output of the AND-OR 7 element is fed to the input of trigger 5 and translates it into a single state . The signal from the output of the trigger 5 enters the receiving VM as a request to receive a data byte.

Receiving VMs organize receiving a data byte from output buffer register 1 via bus 20 and send

signals confirming reception on buses 24 and 26. These signals arrive at the inputs of the element OR 16. The arrival of at least one of the signals means that the notification of receipt before reception

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must be held. The single-level signal from the output of the element OR 16 is fed to the input of the trigger 5 and translates it into the zero state,

The transmitting VM in response to the zero state of trigger 4 after some time removes the data bytes from the buses and the tracking signal.

The absence of the byte tracking signal at the input of the element OR 15 causes the zero signal from its output to the input of the element NOT 9. The signal of the single level from the output of the element NOT 9 enters the inputs of the element AND-OR 6 and the switching unit 3, where it causes formation of a single level signal at output 32. At the inputs of the AND-OR 6 element, the signals of the single level from the output of the HE element 9, from the output 27 of the block 14 and from the output 31 of the block 3. The signal of the single level from the output of the AND-OR element 6 is fed to trigger 4 and translates its g into a single with standing A single-level signal from the trigger of trigger 4 goes to the transmitting VM as a request for issuing a data byte. The process described above is repeated.

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transfer of data byte to the host VM.

When exchanging with the transmitting VM in the first interface in the information transfer control block 14, it blocks the possibility of organizing the exchange I by the VM codes of the second interface. In the second block, 13 requests are pro-; confirmation of the readiness of the VM of the first interface to; receiving information on the command of the VM of the second interface.

I In the course of data transmission in information transmission control unit 14, the number of transmitted bytes of information I is constantly compared with the number of bytes that must be transmitted. If they are equal, a single-level signal is generated at the I output 29 of the block, which is fed to the transmitting VM (via the control outputs 22 of the device) as a signal for the end of the exchange. According to this signal, the VM removes the request. I Clearing a request causes ijto in block 12 of processing requests I clears the processing of the request for icoB and selects the next priority request for transferring VM information to the first interface. It removes the lock on the ability to exchange | commands of the VM of the second interface. I By the readiness of VMs participating in the exchange, data exchange is organized by the commands of the VMs of the second interface, | similarly discussed above

It may happen that some: receiving VMs at the set time: do not confirm readiness to receive Data. In this case, the device operates as follows. The signal of the unit level on the bus 35 (36) is fed to the input of the information transmission control unit. Through-j set time, a warning signal is generated at the output of the block that the output P1 (P2) is malfunctioning. In the case when there is no info exchange on commands of the VM of the second (first) interface, the output 27 (28) of block 14 generates a signal that controls the data transfer from the first (second) interface to the second (first) interface. Further, the operation of the device is as described previously. An exchange of data is organized between it transmitting and prepared by the host VM. Serving perso

alert signal (if necessary) analyze the causes of its occurrence. With the arrival of ready-to-receive signals from all receiving VMs, the disturbance alert signal is reset.

In a case when accepting VM

the first and second interfaces do not confirm readiness to receive data; a signal is generated at the OTK output of the information transfer control unit 14 - the operation of the computer complex is terminated.

Claims (1)

Invention Formula A device for coupling computers that contains an input buffer register, an output buffer register whose output is an information output of the device, a group of elements AND, a group of elements AND-OR, two elements AND-OR, switching unit, two triggers, two elements NOT, first query processing unit, two elements OR, the first and second inputs of the AND-OR group elements connected respectively with the first and second information inputs of the device, the outputs of the elements of the AND-OR group are connected to the information inputs of the input buffer register, the outputs of which are connected to the information inputs of the AND elements of the groups whose outputs are connected to the information inputs of the output buffer register, the first output of the block switching is connected to the second inputs of elements AND of the group and to the first inputs of the first and second elements AND-OR, the second output of the switching unit is connected to the first and second inputs of elv; AND-OR group, and the third output of the switching unit is connected to the second inputs of the first and second elements AND-OR, the third inputs of which are connected respectively to the outputs of the first and the second element NOT, as well as the first and second information inputs of the switching unit, the fourth input of the first element AND-OR is connected to the third information input of the unit switching, with the fifth input of the second AND-OR element and the third inputs of the AND-OR group elements, the fifth input of the first II-IL element is connected to the fourth information input of the ka switching, with the fourth input of the second element IgILI and with the fourth inputs of the elements of the AND-OR group, the outputs of the first and second elements OR are connected to the fifth and sixth information inputs of the switching unit and the installation inputs in the first and second the triggers, the installation inputs in 1 of which are connected respectively to the outputs of the first and second AND-OR elements, the outputs of the triggers are connected to the corresponding outputs of the first and second groups of information transmission resolution outputs The properties, the inputs of the first and second elements OR are connected to the corresponding inputs of the first and second groups; information transfer confirmation inputs of the device, the first group of information inputs of the first request processing block is connected to the corresponding request inputs of the first device group, the information input of the first processing block is connected to the first information input of the device, the group of control outputs of the first request processing block is connected to the corresponding outputs of the first device enablement output groups, the request signal outputs of the first request processing unit are connected according to the other outputs of the second group of control outputs of the device request, which differs in that, in order to expand the functionality of the device by eliminating the situation of inoperability in the absence of a ready signal of one computer and providing the ability to use the waiting time for responses on request of the computer of one of the interfaces for organizing exchange at the request of a computer of a different interface, a second request processing block and a block are entered into it 0 five 0 0 five 0 five information transmission control, where the first group of information inputs of the second request processing block is connected to the corresponding request inputs of the second device group, the information input of the second request processing block is connected to the second information input of the device, the group of control outputs of the second request processing block is connected to the corresponding outputs of the second output group enabling the device connection, the outputs of the request signals of the second query processing loop are connected to the corresponding output s of the first group of control outputs of the device request, the first outputs of the first and second request processing units are connected respectively to the first and second inputs of the information transfer control unit, the second outputs of the first and second request processing units are connected respectively to the third and fourth inputs of the information transfer control unit, third the outputs of the first and second request processing units are connected respectively to the fifth and sixth inputs of the information transmission control unit, the fourth outputs of the first and second request processing blocks are connected respectively to the seventh and eighth inputs of the information transmission control unit, the ninth and tenth inputs of which are connected to the outputs of the first and second OR elements, respectively, and the first and second outputs to the third and fourth information inputs of the switching unit, respectively, the third the output of the information transmission control unit is connected to the corresponding outputs of the first and second groups of outputs of the indication of the end of the device exchange, the fourth, fifth and sixth outputs of the control unit Laziness transmission of information are outputs of signs of malfunction. f3 hertz w w