RU2018944C1 - Device for interfacing computer with external objects - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has a memory unit, address selector, unit for control of recording and reading, interrupting unit, first and second data buffers, diagnostic register, unit for setting own address and parity, command register, state flag indication unit, bite counter, counter zeroing indication unit, data register gang, external object number register, bus occupancy indication unit, local synchronization unit, parity check unit, phase check unit, bus synchronization unit, exchange control unit, phase selection unit, bus synchronization unit, external amplifier control unit and arbitration unit. EFFECT: simplified device and diagnostics. 2 cl, 2 dwg

Description

 The invention relates to computer technology, and in particular to devices organizing the procedures for exchanging a personal computer with external objects via the SCS1 bus, such as NMD, NML, ADCU, etc., and can also be used to build local computer networks.

 A device for interfacing a system and a local highway, comprising an operation unit, a group forwarding unit, an access control unit for arteries, a local arbiter, an interface unit for a system arterial, an interface unit for a local arterial, a decoder, address registers [1].

 A disadvantage of the known device is its complexity.

 Closest to the claimed technical solution is the NCR 5386 SCS1 exchange controller [2], which contains a direct memory access unit, an address comparator, a write and read control unit, an interrupt unit, a first data buffer, an interrupt register, a unit for setting its own address and parity, a register commands, status register, command decoder, state flag fixation node, byte counter, counter zeroing fixation node, data register block, external device number register, bus busy fixation node, local synchronization block, Lok parity control, phase control unit, the synchronization unit bus exchange control unit, phase selection unit, the second data buffer amplifiers external control unit.

 A disadvantage of the known device is that it requires when connecting additional elements made on microcircuits with a small degree of integration.

 The invention solves the problem of simplifying the construction of the device board by introducing elements that perform arbitration inside the device microcircuit, which allows you to separate the data bus and the arbitration. In addition, the introduction of a diagnostic register and a general hardware reset mode simplifies device diagnostics.

 The specified technical result is achieved in that in a device containing a direct memory access unit, an address selector, a write and read control unit, an interrupt unit, first and second data buffers, an interrupt register, an own address and parity set unit, an instruction register, a state register , command decoder, state flag fixing node, byte counter, counter zeroing fixing node, data register block, external object number register, bus busy fixing node, local synchronization block, control unit soars eta, phase control unit, bus synchronization unit, exchange control unit, phase selection unit, external amplifier control unit, the output and the first input of the direct memory access unit, the group of inputs of the write and read control unit, the output of the interrupt unit, the group of inputs of the address comparator connected to the corresponding control and address buses of the computer, the first group of inputs and outputs of the first data buffer is connected to the computer data bus, and the second group of inputs and outputs is connected to the inputs and outputs of the data of the interrupt register, job block own address and parity, instruction register, byte counter, state register, the first data inputs and outputs of the data register block and the external object number register, the information inputs of the own address and parity set block are connected to the corresponding computer control buses, and the control inputs, respectively, with the outputs the address selector and the write output of the write and read control unit, the output of the address selector is connected to the control inputs of the instruction register, interrupt register, byte counter, register block The data output, the external object number register, the write output of the write and read control unit is connected to the entries of the command register, byte counter, state register, data register block, and the read output is connected to the read inputs of the command register, interrupt register, state register, number register an external object, a data register block, the second data input-output of which is connected to the data input-output of the parity control unit, the second data input-output of the external object number register and the first data input-output of the second bu Data era, the second data input-output and identification input-output of which are connected respectively to the data bus and control bus of external objects, the outputs and inputs-outputs of the control of external objects of the control unit of external amplifiers, the bus synchronization unit, the data exchange control unit, the phase selection unit connected to the corresponding control inputs and inputs-outputs of external objects, the output of the state flag fixing unit is connected to the inputs of the control unit of external amplifiers, the phase selection unit, the first inputs of the month a synchronization block and a command decoder, the second input of which is connected to the output of the command register, and the output is connected to the second input of the local synchronization block and the first sync input of the bus synchronization block, the second sync input of which is connected to the first output of the local synchronization block and the sync inputs of the data exchange control unit and the second data buffers, the first and second outputs of the status of the bus synchronization unit directly and through the bus busy fixing unit are connected to the first and second outputs of the flag fixing unit connected to the input of the corresponding bit of the state register, the inputs of the remaining bits of which are connected respectively to the outputs of the counter zeroing fixing unit, the parity control unit, the phase control unit and the first output of the interrupt register, the second output and the first input of which are connected respectively to the input of the interrupt unit and by the output of the state register, the second input of the direct memory access unit is connected to the second output of the local synchronization unit, the third input of which is connected to the output of the byte counter, also dynamically connected with the input of the counter zeroing fixing unit and the input of the command register data, the output of the own address and parity setting unit is connected to the control inputs of the parity control unit and the second data buffer, the output of the data exchange control unit is with the control input of the byte counter, the output of the parity control unit is with the second control input of the second data buffer, the output of the phase selection unit - with the input of the phase control unit, a diagnostic register, an arbitration unit, the first and second inputs of which are connected respectively to the output of the unit for setting its own address and parity and the first output of the local synchronization unit, and the group of outputs is connected to the arbitration bus of external objects, and the output of the general reset of the bus synchronization unit is connected to the inputs of the corresponding bits of the interrupt register and state register, synchronization, the group of outputs of the register of its own number is connected with a group of inputs of the arbitration bus buffer, the group of outputs of which is a group of block outputs, a group of data I / O, a control input and a register read input diagnostics are connected respectively to the second group of inputs and outputs of the first data buffer, with the output of the address selector, the read output of the write and read control unit, while the arbitration unit contains its own number register and the arbitration bus buffer, the inputs of which are the first and second inputs of the block, respectively the outputs of the register of its own number is connected to the group of inputs of the buffer of the arbitration bus, the group of outputs of which is the group of outputs of the block.

 In FIG. 1 shows a diagram of a device; in FIG. 2 is a diagram of a computer complex in which the device is used.

 The device comprises (Fig. 1) a direct memory access unit 1, an address selector 2, a write and read control unit 3, an interrupt unit 4, a first data buffer 5, a diagnostic register 6, an interrupt register 7, an address and parity setting unit 8, 9 command register, 10 status register, 11 command decoder, status flag fixing node 12, 13 byte counter, counter zero fixing node 14, data register block 15, external object number register 16, bus busy fixing node 17, local synchronization block 18, block 19 parity block 20 con Rola phase, an arbitration unit 21, block 22 the synchronization bus, communication control unit 23, the phase selection unit 24, a second buffer 25, the data register 26 of own numbers, buffer arbitration bus 27, block 28 controls external amplifiers.

 The computing complex (Fig. 2) contains a personal computer 29, a device 30 interface, external objects 31.

 All units of the device are made standard. New communications register 7 interrupt and register 10 states are provided by the fact that they used additional bits. The interrupt register 7 is an eight-bit read-only register, which, together with the state register 10, is used by the processor to determine the cause of the interrupt. At the end of reading the register of 7 interrupts, its bits displaying the cause of the interrupt are automatically reset. The register of 10 states is an eight-bit register, one of the digits of which is used to control the "Hardware reset" signal. Logical “1” in this category indicates that the “Hardware reset” signal of all objects connected to it is installed on the SCSI bus. If there was an interruption upon the arrival of the “Hardware Reset” signal, then the moment when it was removed is monitored for this category. Diagnostic register 6 is an eight-bit read-only register. After turning on the power, it always contains the code 10000000 - "Self-diagnosis successfully completed."

 The device is executed in the form of a microcircuit and can work in two modes: "master and slave". In addition, the device supports SCSI bus arbitration (including resetting) and can operate as a control processor in direct memory access (DMA) mode. In the operation of the device, the following phases are defined.

 The first phase "bus free" shows that no device is connected to the bus, does not use it and it is available for any of them. This phase is characterized by the simultaneous absence of BSY and SEL signals at the corresponding inputs of block 22 for a given period of time, which is necessary to calm the signals in the cable.

 The second phase, “bus arbitration,” allows one external entity to take control of the SCSI bus so that it can act as a “master” or “slave”. The device microcircuit supports bus arbitration; therefore, it can be used to build systems with several “masters”. The SCSI bus arbitration procedure is as follows. After the “bus free” phase, the device waits for a while, then simultaneously exposes its number and the BSY signal at the input of block 22 at the input of the buffer 25 data. After waiting for the specified time interval, the external object checks the status of the data bus. If the priority object has set its number, the device should reset the BSY signal and its number and return to the first phase. If the device has the highest priority, then it sets the SEL signal at the input of block 22.

 The third phase of "selection" allows you to select the "slave" in order to perform a specific function (for example, reading or writing). During the "selection" phase, the I / O signal at the input of block 24 must be reset to distinguish it from the "selection" phase. The selection procedure is performed as follows. The external entity that won the arbitration determines itself as the “master” by not setting the I / O signal at the output of block 24. Then the “master” sets its own number and the number of the selected “slave” at the input / output of buffer 25 data, combining them by OR. After setting all these signals on the bus, the master takes its BSY signal at the output of block 22 and then goes into the standby mode of the BSY signal from the selected slave. The “slave” determines that the “master” is trying to call it by a combination of SEL signals and its number on the data bus. After that, the “slave” remembers the number of the “master” and sets its BSY signal. Having received the BSY signal at the input of block 22, the "master" removes its signal SEL and the numbers of the "slave" and its own, which completes the phase of "selection".

 The fourth phase of "selection" is performed similarly to the phase of "selection" except that the "master" and "slave" are interchanged and the "slave" at the same time sets the I / O signal at the output of block 24. Thus, after the selection and selection operations, the signal BSY always sets the slave. Block 19 parity does not allow you to set the response signals with a parity error.

 After the connection between the “master” and “slave” is established, the “information exchange” phase is performed. This phase includes commands for receiving and transmitting commands, data and messages. These commands are terminated by interruption and are allowed only for the microcircuit, which is in the "slave" mode. These commands can use modifiers that determine the mode of the RAP and the "transmission of a single byte."

 Before loading the instruction code into the register of 9 instructions, a counter of 13 bytes must be loaded, with the exception of the "single byte transfer" mode. After the command is loaded into register 9, the flags are reset in the device, indicating that the data registers of block 15 are full and it goes into standby mode for data from the SCSI bus and from the processor, respectively, in the transmit and receive modes.

 After determining the information phase, the device exchanges data between the processor and the SCSI bus. If the RAP flag is defined in the command code, then the exchange takes place without access to the block 15 registers using the signals DREQ and DACK of block 1. Otherwise, the exchange occurs through block 15 of the data registers. After receiving (transmitting) data, the device generates an interrupt signal, setting the corresponding bits in registers 7 and 10, after which it remains in the “slave” state, occupying the bus. If the value of counter 13 is zero, then it means that all bytes have been successfully transferred and node 14 generates a signal at its output, which enters the corresponding bit of state register 10. If the “Parity Enable” bit was set in the status register, then the device performs parity control during data exchange. When a parity error is detected, an interrupt is generated and the “completion of operation” flag is set in the interrupt register 7, and the “parity error” flag is set in the status register 10. The 13 byte counter shows the number of unsent (not received) bytes, including the erroneous one. If during the data exchange the "master" set the ATN signal at the output of block 22, then the "bus service" bit is set in the interrupt register 7. Data exchange procedures can be stopped before completion by loading the pause command into the register 9. In this case, the “slave” finishes receiving (transmitting) the current byte and stops its operation, saving the value of the byte counter and the state of the I / O, C / D, MSG signals. After that, you can use the command to break the connection with the "master" or reload the interrupted command without changing the counter value of 13 bytes to continue it.

 The "Transfer Info" command is an exchange command for the controller in the "master" mode, it also ends with an interrupt. This command is only issued in response to a bus service interrupt. Upon receipt of the interrupt, but before issuing the command, the processor must analyze the state of the I / O, C / D, MSG signals in the 10 state register in order to determine the phase of the SCSI bus and the direction of transmission, as well as load a 13 byte counter. Subsequently, the exchange occurs similarly to the previous one. The completion of the exchange and the issuance of interruptions occur in the following cases.

 The device transmitted (received) the number of bytes specified by counter 13.

 “Slave” changed the phase (I / O, C / D, MSG signals), which is fixed by block 24, until counter 13 is reset.

 The slave released the SCSI bus and reset the BSY signal, after which the device goes into the disconnected state.

 The last byte of data in the Message In phase has been received. In this case, the “end of operation” bit is set in the interrupt register 7 and the ACK signal remains set at the end of the command. This enables the processor to issue an ATN signal to transmit a response message to the “slave”. After that, to remove the ACK signal, it is necessary to issue the message received message command. A detected parity error cannot cause a command to terminate and an interrupt to be issued. To do this, the device must wait for one of the above cases. If the command needs to be completed urgently, you can use the "reset" or "disconnect" command. These commands put the “master” device in the “disconnected” state, and the associated “slave” remains on the bus. Therefore, if it is necessary to stop the operation of the “slave”, the “reset” SCSI bus command must be used, setting the signal at the input-output of block 22, from the output of which it goes to the corresponding bits of register 7 interrupts and register 10 of states of the “slave” device, which stops its operation, freeing up the SCSI bus.The RST signal is reset after writing any other command to the device register 9.

 The arbitration unit 21 is introduced to separate the arbitration bus and the data bus, which allows the device to simultaneously issue its own address and “listen” to the data bus to determine the “winner”.

Claims (2)

 1. A DEVICE FOR COMBINING COMPUTERS WITH EXTERNAL OBJECTS, comprising a direct memory access unit, an address selector, a write and read control unit, an interrupt unit, first and second data buffers, an interrupt register, a unit for setting its own address and parity, an instruction register, a state register , command decoder, state flag fixation node, byte counter, counter zeroing fixation node, data register block, external object number register, bus busy fixation node, local synchronization block, parity block, control block Phase field, bus synchronization unit, exchange control unit, phase selection unit, external amplifier control unit, the output and the first input of the direct memory access unit, the group of inputs of the write and read control unit, the output of the interrupt unit, the group of inputs of the address selector are inputs and the outputs of the device for connecting to the corresponding control and address buses of the computer, the first group of inputs and outputs of the first data buffer is the group of inputs and outputs of the device for connecting to the computer data bus, and the second group of inputs is of moves is connected to the inputs / outputs of the data of the interrupt register, the unit for setting its own address and parity, the instruction register, the byte counter, the status register and the first inputs and outputs of the data of the block of data registers and the register of the number of the external object, the information inputs of the unit for setting the own address and parity are inputs devices for connecting to the corresponding computer control buses, and their control inputs, respectively, with the output of the address selector and the write output of the write and read control unit, the output is the address bar is connected to the control inputs of the command register, interrupt register, byte counter, data register block, external object number register, the write and read control unit write output is connected to the command register, byte counter, status register, data register block inputs reading - with the inputs of the reading of the command register, interrupt register, status register, register of the external object number, data register block, the second data input-output of which is connected to the data input-output of the control unit parity, the second input-output data of the register of the external object number and the first input-output of the data of the second data buffer, the second input-output of the data and the input-output of the identification of which are inputs and outputs of the device for connecting, respectively, to the data bus and control bus of external objects, outputs and the inputs and outputs of the control of external objects of the control unit of external amplifiers, the bus synchronization unit, the data exchange control unit, the phase selection unit are the inputs and outputs of the device for connecting to the controlling inputs and outputs of external objects, the output of the status flag fixing unit is connected to the inputs of the external amplifier control unit, the phase selection unit, the first inputs of the local synchronization unit and command decoder, the second input of which is connected to the output of the command register, and the output to the second the input of the local synchronization block and the first clock input of the bus synchronization block, the second clock input of which is connected to the first output of the local synchronization block and the clock inputs of the data exchange control unit and the second data buffer, the first and second outputs of the status of the bus synchronization unit directly and via the bus busy fixation unit are connected to the first and second inputs of the status flag fixation unit, the output is connected to the input of the corresponding bit of the status register, the inputs of the remaining bits of which are connected respectively to the outputs of the reset zeroing unit counter, parity control unit, phase control unit and the first output of the interrupt register, the second output and the first input of which are connected respectively to the input of the unit interrupt and status register output, the second input of the direct memory access block is connected to the second output of the local synchronization block, the third input of which is connected to the output of the byte counter, also connected to the input of the counter zeroing fixing node and the input of the command register data, the output of the unit for setting its own address and the parity is connected to the control inputs of the parity control unit and the second data buffer, the output of the data exchange control unit is connected to the control input of the byte counter, the output of the parity control unit is it is single with the second control input of the second data buffer, the output of the phase selection unit is connected to the input of the phase control unit, characterized in that a diagnostic register, an arbitration unit, the first and second inputs of which are connected respectively to the output of the unit for setting its own address and parity and the first the output of the local synchronization block, and the group of outputs is the group of outputs of the device for connecting external objects to the arbitration bus, and the output of the general reset of the bus synchronization block is connected to the inputs the corresponding bits of the interrupt register and the status register, the group of data I / O, the control input and the read input of the diagnostic register are connected respectively to the second group of I / O of the first data buffer, with the output of the address selector, the read output of the write and read control unit.  2. The device according to claim 1, characterized in that the arbitration unit contains a register of its own number and buffer of the arbitration bus, the inputs of which are respectively the first and second inputs of the block, the group of outputs of the register of its own number is connected to the group of inputs of the buffer of the arbitration bus, the group of outputs of which is group of outputs of the block.

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