JP2667285B2 - Interrupt control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to an interrupt control device that controls (masks, prioritizes, etc.) an interrupt signal sent to a microprocessor device (hereinafter, referred to as a CPU).

[Prior art]

Generally, an interrupt operation refers to an operation in which the CPU temporarily stops a program being executed and interrupts execution of the interrupt program, and the CPU has an interrupt request terminal for causing the interrupt operation. An external device connected to the CPU through the interrupt request terminal can execute an interrupt program by sending an interrupt request signal.
If there are more than the number of interrupt request terminals, it is necessary to distinguish those interrupt requests. The interrupt control device provides the CPU with information for distinguishing the interrupt request. FIG. 7 is a block diagram showing a configuration of a conventional interrupt control device, and FIG. 8 is a block diagram showing a connection state between the conventional interrupt control device and a CPU, where 1 controls an interrupt operation. a control circuit for, 2 interrupt request register to set the bit corresponding to the interrupt request input IR ₀ ~IR ₇ 11, 3 have priority resolver to determine the priority of the input interrupt request, 4 fixed period input The in-service register 5 that holds the bit corresponding to the interrupt request that has been input is masked for the input interrupt request (even if an interrupt request signal is generated,
Interrupt mask register for holding information of a state that cannot be transmitted to U19), 6 is a data bus buffer for transmitting and receiving data to and from CPU19, and 7 is a write control input from CPU19.
▼ 13, read control input ▲ ▼ 14, address input A ₀ 15,
Alternatively, the read / write control circuit 8 which receives the chip select input ▲ ▼ 16 and transmits it to the control circuit 1, and the interrupt request output INT10 of the relevant interrupt control device is input to the interrupt request input of another interrupt control device. Cascade buffer comparator for cascade connection, 9 is interrupt response input from CPU19.
▼, 12 are bidirectional data buses D _{0 to} D ₇ , 17 are cascade lines CAS _{0 to} CAS ₂ , 18 are master interrupt controller 22 or slave interrupt controller 22 for cascade connection A slave program input / enable buffer output SP / EN, 20 is an address bus, and 21 is a control bus. Incidentally, when performing cascaded together to connect one of the interrupt request inputs IR ₀ ~IR ₇ of the master interrupt controller 22 to the INT terminal of the slave interrupt controller 22, each of the cascade line CAS ₀ to connect the ~CAS ₂ 12. In this case, INT signal when the interrupt signal connected to the interrupt control unit 22 of a slave n has become active becomes active, the interrupt request input IR _n of the master is active. Then, the master interrupt control device 22 determines which of the slave n interrupt control devices 22 to accept the interrupt as valid in consideration of the masks and priorities of other interrupt request inputs IR, and determines that slave n Number of cascade line CAS _0- CA
Output in binary to S _2. Next, the master interrupt control device 22
The slave selected by the cascade input outputs an appropriate pointer to the CPU 19 in consideration of the mask and the priority from the interrupt signal input thereto. Thus, a cascade line CAS conventional interrupt controller 22 ₀ If ～CAS ₂ is three, cascaded can not only connect two stages, three stages or more cascaded without adding additional cascading line more Could not do. When two stages of cascade connection are used, up to eight slave interrupt control devices 22 can be connected to the master interrupt control device 22, so that 64 interrupt requests can be processed. Next, the operation will be described. When one or more of the interrupt request inputs IR ₀ ~IR ₇ 11 becomes "H" level, the interrupt request register 2 corresponding to the interrupt request
Is set. Further, the interrupt request is checked for its mask status by the contents held in the interrupt mask register 5, and its priority is determined by the priority resolver 3. As a result, the control circuit 1 interrupts the CPU 19. Request output INT10 is output.
When receiving the interrupt response input ▲ ▼ 9 of the CPU 19 to the interrupt request output INT10, the bidirectional data bus is received.
Keeping the D ₀ to D ₇ 12 to a high impedance state, both further by the interrupt response input ▲ ▼ 9 is sent from the CPU 19, the 8-bit pointer (indicating the start address of an interrupt program which CPU 19 executes) Output to the directional data bus 12. On the other hand, the bit of the in-service register 4 corresponding to the interrupt request is set at the falling edge of the interrupt response input ▼, and the bit of the interrupt request register 2 is reset at the rising edge. Normal EO
In I mode, the bit of in-service register 4 is
19 via a bidirectional data bus D ₀ to D ₇ 12 from the EOI command becomes the set state until the input. Next, in CPU19 via a bidirectional data bus D ₀ / D ₇ 12 8
When the bit pointer is received, execution of the interrupt program at the corresponding address is started, and when the interrupt program ends, an EOI command is sent to the interrupt control device 22.
As a result, the corresponding bit of the in-service register 4 is reset, and the contents of the interrupt request register 2 are checked to see if there is any interrupt request input waiting to be executed. Then, if there are remaining interrupt request inputs, the interrupt request input with the highest priority is selected, and the above-described interrupt operation is repeated.

[Problems to be solved by the invention]

Since the conventional interrupt control device is configured as described above, three or more cascade connections cannot be performed as shown in FIG. 9, and an interrupt response input from the CPU 19 as shown in FIG. ▲ ▼ and cascade line CAS ₀ ~CAS ₂ interrupt control unit 22 is a problem, such as not be used on expansion board connected to a system bus can not be transferred. The present invention has been made to solve the above-described problems, and can increase the number of interrupt signals on an expansion board and input an interrupt response from the CPU 19.
An object of the present invention is to provide an interrupt control device which enables control of an interrupt request signal even on an expansion board which cannot receive ▼.

[Means for Solving the Problems]

An interrupt control device according to the present invention includes a data bus buffer for a CPU to read an interrupt factor that has issued an interrupt request, and whether or not an interrupt request remains after a write operation from the CPU. , And an INT signal generation circuit for outputting an interrupt request output INT to the CPU if the remaining is checked.

[Action]

INT signal generating circuit in the present invention, an OR output of the interrupt request inputs IR ₀ ~IR _7, interrupt request outputs an AND output of the signal indicating that the CPU comes write the EOI command (active low) Output as INT.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an interrupt control device according to an embodiment of the present invention.
The same or corresponding parts as those shown in FIG. In the figure, 23 is a chip select input ▲ ▼, output enable signal 24 is read permission, 25 a data bus to be set a bit corresponding to input an interrupt request input IR ₀ ~IR ₇ as an interrupt factor buffer, 26 aND between the OR output of the interrupt request inputs IR ₀ ~IR ₇ 11, a signal indicating that the CPU comes write the EOI command (active low)
This is an INT signal generation circuit that outputs an output as an interrupt request output INT10. FIG. 2 is a block diagram showing a connection state between an interrupt control device and a CPU according to an embodiment of the present invention. In FIG. 2, reference numeral 27 denotes the interrupt control device, It is configured to input to the interrupt control device 22. Next, the operation will be described. When one or more of the interrupt request inputs IR ₀ ~IR ₇ 11 becomes "H" level, OR output interrupt request output those signals INT10
Therefore, the interrupt request output INT10 becomes "H" level (FIGS. 3 and 4). In this case, the write control input ▲
Assuming that ▼ 13 and the chip select input ▲ ▼ 23 are inactive (“H” level), the interrupt request output INT10 (output from the INT signal generation circuit 26) is interrupted by the conventional interrupt controller 22. A request is input and a series of interrupt operations occur. The CPU 19 starts the interrupt control device 27 at the beginning of the interrupt program.
To read the contents of the data bus buffer 25 (activate the read control input 14 and the chip select input 23) to take in the interrupt factor. Then, when the interrupt processing is completed, the CPU 19 performs a write operation on the interrupt control device 27. Actually, the purpose of this write operation is to activate the write control input 13 13 13 and the chip select input ▼ 23 23, and the bidirectional data bus D ₀
Signal out to ~D ₇ 12 on can be anything. Then, write control input ▲ ▼ 13 or chip select input ▲ ▼
When either 23 becomes "H" level, yet again interrupt request output any remaining interrupt request input IR ₀ ~IR ₇ 11 is INT10
Is output from the INT signal generation circuit 26, and a series of interrupt operations is repeated (FIGS. 5 and 6). Therefore, as shown in FIG. 10, when the interrupt response input ▲ ▼ from the CPU 19 and the cascade lines CAS _{0 to} CAS _{2 of the} interrupt control device 22 are on an expansion board connected to a system bus that cannot transfer ( If INT10 for example is connected to the IR ₂ 11), the interrupt request input IR from the expansion board
_{One of 10} to ₁₂ becomes active and interrupt control device 22
Accepts IR ₂ , the interrupt control device 22
The CPU 19 that outputs the pointer for IR ₂ and stores the pointer address at that point first reads the data buffer (not shown) of the expansion board, and determines which interrupt request input IR ₁₀ to _{12 of the} expansion board is active. judge. Then, for example, if a plurality of interrupt request inputs IR ₁₀ ~ ₁₂ it is sufficient that the active, advance the mask, leave program priorities, to be executed the interrupt program CPU19 selects. The device that generates an interrupt on the expansion board is CPU1.
When an appropriate process is executed after an interrupt is received by the interrupt 9, the interrupt request inputs IR ₁₀ to IR ₁₂ are made inactive. In the above embodiment has been an interrupt request input IR ₀ ~IR ₇ 11 as only eight, no particular number restriction. The same effect can be obtained even when the interrupt control device 27 is incorporated into the conventional interrupt control device 22 and used.

【The invention's effect】

As described above, according to the present invention, the data bus buffer for the CPU to read the interrupt factor that has issued the interrupt request, and the remaining interrupt request output INT in response to the write operation from the CPU are output. Since it is configured with an INT signal generation circuit, the number of interrupt signals on the extension board can be increased, and even on an extension board that cannot receive an interrupt response input signal from the CPU, There is an effect that an interrupt control device enabling control can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an interrupt control device according to one embodiment of the present invention, FIG. 2 is a block diagram showing a connection state between the interrupt control device and a CPU according to one embodiment of the present invention, and FIG. 6 are time charts for explaining the operation of the interrupt control device according to an embodiment of the present invention, FIG. 7 is a block diagram showing the configuration of a conventional interrupt control device, and FIGS. FIG. 11 is a block diagram showing a connection state between a conventional interrupt control device and a CPU. In the figure, 11 is an interrupt request input, 12 is a bidirectional data bus, 13 is a write control input, 14 is a read control input, 23 is a chip select input, 25 is a data bus buffer, and 26 is an INT signal generation circuit. is there. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An interrupt request output from an external device is input to a CPU executing an interrupt process by inputting a head address of an interrupt program output to a data bus when an interrupt request output signal is received. Information to distinguish input signals
A data bus buffer for outputting a start address of an interrupt program corresponding to the interrupt request input signal to a data bus; a write control signal for receiving the interrupt request input signal; An interrupt control device comprising: an INT signal generating circuit having an interrupt request generating circuit for outputting the interrupt request output signal when receiving a chip select signal.