JPS62145345A - Control system for direct memory access interval - Google Patents

Abstract

PURPOSE:To perform DMA transfer without inhibiting one DMA operation even if DMA which requires speediness conflicts with DMA which requires no speediness by controlling the DMA transfer interval between memories where a transfer speed is not important. CONSTITUTION:When DMA control information is written in a DMA (direct memory access) register 24 from a CPU 11, a CPU 21 sets the DMA interval between a main system 1 and a slave system 2 in a timer 26. The main system 1 starts DMA in response to a DMA request signal from the salve system 2, whose DMAC 22 attains to DMA data in a memory 23 and also resets the timer 26. When a DMA request signal from an I/O 3 is sent to the slave system 2, on the other hand, DMA to the contents of the memory 23 is performed through the I/O 3 at a high speed.

Description

[Detailed Description of the Invention] [Summary] This is a direct memory access interval control method, and when direct memory access (hereinafter referred to as DMA) is processed at specified intervals, DMA transfer between memories does not particularly concern the transfer speed. If there is a conflict between the DMA transfer and the 1MA transfer, which requires high speed, one of the DMA transfers was prohibited, but by controlling the DMA transfer interval between memories, the transfer speed is not a particular issue. In this case, it is possible to perform DMA transfer without inhibiting either one of the DMA transfers even when the transfer is in progress, and even DMA transfers that require high speed can be performed without errors.

[Industrial application field]

The present invention provides DM between memories that does not particularly concern transfer speed.
The present invention relates to a direct memory access interval control method when A transfer and DMA transfer that require high speed compete with each other.

A system consisting of a main system (for example, a system controlled by the main processor in a dual processor), a subordinate slave system (for example, a system controlled by an input/output control processor), and an input/output device (hereinafter referred to as I10). One method for transferring data between devices is the DMA method.

This DMA method uses a processor (hereinafter referred to as CPU)
Memory (RAM) and memory (RA)
This is a method in which data is transferred between the memory (RAM) and Ilo at predetermined intervals.

In this method, if Ilo is a hard disk, for example, high-speed DMA between memory (RAM) and Ilo is required.

On the other hand, memory (RAM) and memory (RIIIM)
DMA between
There is a need for the development of a method for efficiently performing DMA transfer when two leaves A conflict.

[Prior art and problems to be solved by the invention] FIG. 3 shows a block diagram illustrating a conventional example.

This block diagram shows the control of the entire terminal and l10 in a terminal adopting a dual processor system, for example.
Main system 1 performs calculations on the data received from 3.
And, for example, I10 system that specializes in controlling I103? 11
It is composed of a slave system 2 corresponding to a device, and an l103 under the control of the slave system 2.

In addition, the main system 1 has a cpUlt which monitors the f) j lyrics '4111/operation in the main system 1 and controls the transmission of signals to and from the outside.
and a DMA control device (hereinafter referred to as DM) that controls DMA of data stored or to be stored in the memory (RAM) 13.
(referred to as AC) 12, and DMAC to record data and transfer recorded data.
Memory (1?AM) performed by DMA after control of 13
Furthermore, the slave system 2 also has the same functions as the main system 1, including a CPt 121, a DMAC 22, and a memory (RAM) 23, in which DMA control information is written from the CPU 11 or CPt 121. CPt121 or CP
Intervention request signal (hereinafter referred to as iRQ) to IJll
DMA between the Kano A regisc 24 that sends ■' or ■, the slave system 2 and the main system 1
and a data buffer 25 for temporarily storing data to be processed.

Next, iterate to the system configured as above,
The operation will be explained by taking as an example a case where f71 inter-CPU DMA is performed from CPU II to CPU 21, and at that time there is a DMA conflict between 103 and CPU 21.

In addition, D between main system 1 and slave system 2
It is assumed that the MA interval is performed at a pre-fixed interval, and the DMA interval between the slave system 2 and l103 is performed at a higher speed than that between the main system 1 and the slave system 2.

The cputt of the main system 1 instructs the DMAC 12 to prepare for processing the OM8 through the data bus a, and at the same time sends the DMA register 2 through the data bus a.
Write the DMA control information of slave system 2 to 4.

When the DMA 1lil control information is written to the DI'lA register 24, an iRQ■' is generated from the DMA register 24 to the CP[I21 of the slave system 2,
The CPt121 of the slave system 2 reads the DMA control information from the DMA register 24, and based on the read DMA control information, receives and receives DMA data from the main system 1 through the data bus C in the slave system 2 to the DI'1AC22. instruct the preparation of

When the preparation is completed, the DMAC 22 sends a request signal ■ to the DMAC 12 in the main system 1. Kano AC
12 is a memory (R static) via address bus b at the same time.
The contents of the designated address No. 13 are transferred to the data buffer 25 by DMA.

When the transfer of DMA data to the data buffer 25 is completed, a DMA response signal ■ is simultaneously sent from the DMAC 12 to D18C22 of the slave system 2, and the DMA response signal
Data reception prepares for input.

Thereafter, when the preparation for DMA data is completed, the data latched in the data transfer buffer 25 is transferred to the memory (RAM) 23 of the slave system 2 by DMA. Further, when the DMA transfer is completed, the next DMA request signal ■ is sent out from the DMAC 22.

In addition, DM from slave system 2 to main system 1
When performing A transfer, the signal is left behind. That is, writing of DMA control information to the DMA register 24 is performed by the CPU 21, and iRQ■ is sent to the CPU II. However, the DMA request signals ■ and D? 'lA response signal The response signal section is the same as in the main-slave (M-5).

On the other hand, the transfer between slave system 2 and l103 is as follows:
For example, when DMA transfer is performed from slave system 2 to l103, the DMA request signal (2) from l103 and the DMA response signal (2) from slave system 2 are carried over.

In the above manner, when data transfer is performed in Kano A, memory (RAM) where transfer speed is not an issue is used.
) 13 and memory (RA gate) 23, slave system 2 and l103 that require high speed (for example,
If the DI'lA conflicts with the main system 1 and the slave system 2 (if the main system 1 has a hard disk), and the DMA between the main system 1 and the slave system 2 is also executed between the DMA between the slave system 2 and the slave system 1103, the DMA between the slave system 2 and the slave system 1103 will be may be in a standby state.

Therefore, D requires high speed.1. IA's DMA transfer speed decreases due to contention, and slave system 2
An error occurs in the DMA between 1103 and 1103. However, there was a problem in that in order to prevent errors from occurring due to contention, one of the DMAs had to be prohibited.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention is the main system 1 explained in FIG. Slave system 2. In particular, slave system 2 consists of CPO21 explained in Fig. 3.
, DMAC 22, memory (RAM) 23, etc., the data transfer interval setting means 26 (indicated as a timer in FIG. 1) allows the CPU 21 to arbitrarily set the DMA interval between the main system 1 and the slave system 2. , hereinafter referred to as a timer).

[Effect]

A timer is used to arbitrarily set the interval between the memories of the main system and slave system, where data transfer speed is not a particular issue, and DMA between the slave system and Ilo, which requires high speed, is performed during this DMA interval. By controlling this, even if a DMA that requires high speed competes with a DMA that does not require high speed, errors in the DMA that requires high speed are prevented, and DIIA transfer of either one is not prohibited. , and without reducing the transfer speed.
? I^ transfer becomes possible.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

Next, the operation of this embodiment will be explained. The operation of this embodiment is based on the premise that there is a conflict between DMA between the main system 1 and slave system 2, where transfer speed is not an issue, and DMA between slave systems 2 and 1103, which require high speed. The operation will be explained below.

It is also assumed that data transfer is performed from the main system 1 to the slave system 2 and from the slave system 2 to l103.

(11. When control information is written from the CPU II to the DMA register 24, an iRQ■' is generated from the DMA register 24 to the CPt121, and the iR
Q■' causes the CPU 21 to read the DMA control information from the DMA register 24, and perform D? with others such as l103. Considering iA+, s, the DMA interval between the main system 1 and the slave system 2 is set for the timer 26.

Also, the DMAC 22 is caused to perform A'=(iM) for receiving and receiving DMA data, and when it is completed, the DMA request signal table is sent to the in-system 1.

(2) The main system 1 receives the DMA request request signal D? from the slave system 2? 1A, DMAs the DMA data to the data buffer 25, and outputs a DMA response signal ■ to the slave system 2.

(3) In response to the DMA response signal ■ from the main system I, the DMAC 22 of the slave system 2 transfers the DMA data stored in the data buffer 25 to the memory (RA1'
1) Perform DMA to 23, reset the timer 26, and start calculation.

(4) 3rd, when the timer 26 finishes counting, again (
The processing from 1) is returned for the number of bytes specified by the DMA control information.

(5) On the other hand, regarding the DMA being performed on the slave system 2 or l103, the DMA request signal ■ is sent from l103 to the DMAC22, and the DMAC22
The contents of memory (I?AM) 23 specified by C2
After the DMA response signal ■ is sent from 2 to l103, DMA is performed.

However, in this case, the processing is performed faster than the DMA interval between the main system 1 and the slave system 2.

That is, if the DMA being performed from slave system 2 to l103 and the main system 1 and slave system 2
If there is a conflict between DtIA between the main system 1 and the slave system 2, the main system 1 and the slave system 103 must be connected so that the DMA being performed from the slave system 2 to the machine 103 is completed during the DMA interval between the main system 1 and the slave system 2. The DMA interval with the system 2 is set in the timer 26.

〔Effect of the invention〕

In the past, when high-speed DMA and normal DMA competed, it was only possible to prohibit one of the DMAs, but according to the present invention, it can be done efficiently without causing any errors. This has the effect of allowing conflict processing to be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a block diagram explaining a conventional example. In the figure, 1 is the main system, 2 is the slave system, 3 is Ilo, and 11.21 is the CPU. 12.22 is DMAC, 13, 23 is memory (RA gate)
, 24 is a DMA register, 25 is a data buffer, and 26 is a timer, respectively. 1 haze

Claims (1)

[Claims] Data transfer between the memory (13) in the main system (1) and the memory (23) in the slave system (2), and the memory (23) and the input/output device (3). In a data processing system, data transfers between the memory (23) and the input/output device (3) compete, and these data transfers are executed in a direct memory access mode with predetermined intervals. If data transfer conflicts with data transfer between the memories (13, 23), a data transfer interval setting means (26) is provided for setting a data transfer interval between the memories (13, 23), and The data transfer interval setting means (26) controls the memory (13) so that data transfer between the memory (23) and the input/output device (3) is processed during data transfer between the memories (13, 23). , 23) A direct memory access interval control method characterized by controlling the direct memory access interval between .