SU1278871A1 - Interface for linking microprocessor peripheral equipment with input-output channel of electronic computer - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer complexes for the exchange of information between computers and microprocessor-based external devices. The purpose of the invention is to expand the class of tasks to be accomplished by providing the ability to exchange a group of microprocessor-based external devices with a computer. The goal is achieved by the fact that a device containing the amplifiers-receivers of information and control of the channel, blocks of amplifiers-transmitters of information and control of the subscriber, blocks of setting AND comparing the address of the external device control, block of parity, decoder of commands, control block, register konshnd and parity check bit shaper, the register of the initial address of the data exchange region, the microprocessor master address block, the external device address register, the register d the block lines, the block of elements; and the formation of the subscriber address, the data register, the status register, and the synchronization block. 2 hp f-ly, 8 ill.

Description

The invention relates to computing and can be used in computer complexes for the exchange of information between computers and microprocessor external devices. The aim of the invention is to expand the class of tasks by providing the possibility of exchanging a group of microprocessor external devices with a computer. FIG. 1 is a block diagram of the device; in fig. 2-5 g functional diagrams of the control unit, the microprocessor trunk address generation unit, the subscriber address unit AND the subscriber address generation unit and the synchronization unit; FIG. 6 is a time chart of the operation of the device at the initial sampling stage; in FIG. 7 -; , time diagram of the work of the block of elements AND formation of the address of subscribers; in fig. 8 is a timing diagram of the synchronization block. The device (Fig. 1) contains a block 1 of amplifiers-receiver channel information, a register 2 of the initial address of the communication area, a block 3 for setting the address of an external device control device (VHF), a block 4 for comparing the address of an external device control device, a parity unit 5, a decoder 6 commands, a microprocessor trunk address generation unit 7, a channel control amplifier receiver block 8, a control block 9, a register 10. commands, register P. addresses external device, block 12 amplifiers, control subscriber control, register 13 block length, driver 14 bits of parity, block 15 elements And the subscriber address normalization, register 16 data, block 17 synchronization, block 18 amplifiers transmitters information subscriber, state register 19, output information 20 and control bus 21 of the channel, input control 22 and information. 23 bus channels, microprocessor data bus 24, microprocessor address bus 25, microprocessor interrupt bus 26, microprocessor bus 27 for controlling external devices, bus 28 for controlling channel signals, lines 29 for comparing the address of controlling an external device and parity, parity bus 30 for registers 10 , 13 and 16, subscriber control signal bus 31, internal control bus 32, external device address bus 33, output bus 34 of the initial address of the exchange area, and microprocessor trunk synchronization bus 35 . The control unit 9 (Fig. 2) contains the descrambler 36 phases of operations, the register 37 of the phases of operations, the decoder 38 of the control signs, the register 39 of control characters, the encoder 40 of the control signals of the subscriber, the register 41 of the control signals of the subscriber. The microprocessor trunk address generation unit 7 (FIG. 3) contains the base address register 42 of the status byte area (OBS), AND 43 and 44 element groups, OR 45 group of elements, AND 46 element group. Subscriber I AND unit 15 is formed (FIG 4) Sodb: neighbors groups 47 and 48. The synchronization unit 17 (Fig. 5) contains the address decoder 49, the state decoder 50, the phase decoder 51, the microprocessor highway state register 52 and the phase register 53. The device works as follows. Registers 2,11,13,16 and 19 directly interact with the bi-directional bus 24 of the microprocessor trunk, so that the microprocessor has the ability to both write and read the data of these registers in accordance with their assigned addresses. To control the exchange of information through the bus 25, 27 and bus 26 interrupt unit 17 is used synchronization. Block 17 analyzes the calls to the device registers named by analyzing the addresses of the registers on bus 25, followed by signals on bus 27 in accordance with the operation algorithm. An example of the algorithm of operation of block 17 is as follows. The read (write) operation signal set up on bus 27 is recognized by decoder 51, from which the control action is directed to decoder 49, which allows resolution of the address on bus 25 to be resolved. The address set on bus 25 is recognized by decoder 49, after which bus line 35 is activated, which ensures that the selected device register is switched with the trunk. If there is an enable signal from block 9 forwarded over bus 32, the Read (Occupation) signal from bus 27 through decoder 50 enters register 52, which is used to generate a message to block 9 via bus 35 about the start of the operation on the trunk. Block 9 sends a response signal on completion of the initiated operation via bus 32. This signal with the help of the decoder 51 and the register 53 generates an external confirmation signal of the performed operation, placed on the bus 27. The timing diagram of the operation of the block 17 is shown in FIG. 8. Block 7 is used for issuing the microprocessor RAM addresses of external devices (WU) to the bus 25, both in data exchange operations (the case of addressing the RAM data area in read or write data block operations), and in the state byte reading procedures, stored in the area of the state bytes (OBS) RAM, implemented during the initial sampling of the device channel. The bytes of the state in the OBS are divided into two categories. The first one includes the current bytes of the state of external devices connected to the HLV, which characterize the degree of readiness of the HL to start the execution of the next channel command. With this, the VU may be in a state of readiness unavailability or busy. The second category includes typical state bytes of the VU, which during the initial sample determine the response of the device to the channel to receive a command when the selected VU is ready. Sixteen bit register 2 is intended both for storing the address of the next RAM cell during data exchange and for storing the channel command code during the initial sampling (for which it uses the low byte of register 2). An eight-bit register 11 stores the address of the slave with which the current operation is associated. The address of the slave is loaded from both the computer channel and the microprocessor program (in the case of the transmission of the asyn chronical bytes of the slave state). The 16-bit register 13 is used, on the one hand, for storing the number of data bytes. which has yet to be transmitted in data exchange operations), on the other hand, the microprocessor program uses 1) the lower order bit of register 13 to place the application for transmission of the asynchronous byte of the state from f $ y. An eight-bit register 16 is designed to temporarily store data bytes from a channel, as well as data bytes and status bytes transmitted to the channel. The eight-bit register 19 is used by the microprocessor program to decipher the reason for the interruption set by the device on the bus (line) 26. Block 15 (FIG. 4) provides the formation of the subscriber's address. The first group of elements And 47 skips the address of the CCS5 coming from block 3, and the second group of elements And 48 addresses the slave address coming from register 11. The address is output to the I / O channel to block 18 by the control signal generated by block 9. The time diagram of operation block 15 is shown in FIG. 7. At the time of the initial sampling, the address arriving over the information bus 20 is analyzed by block 5 and mapped in block 4 to the address generated by block 3, which is a set of jumpers by the number of address bits. Upon successful identification of the address of the DCU assigned to the device, block 9, acting in accordance with the algorithm of interaction with the computer channel and perceiving the control signals of channel 28, allows writing into the register AND addresses of the VU set to information. The bus line 20. At the same time, block 9 resets the lower part of register 2, thereby providing access to the current status bytes stored in the OBS area. Block 7 provides to bus 25 the address of the current status byte corresponding to the selected slave using the contents of register 1G. The extraction of the current status byte from the OBS region occurs under the control of block 17, which is initiated by block 9, resulting in the status byte being written to register 16 via bus 24. Block 9 organizes a return address byte received in the channel 23 Block 15, Next through

the information bus 20 receives a channel command, which is written to the lower part of register 2 under the control of block 9. At the same time, the type of incoming command (write, read) is decoded by decoder 6 and the command type is fixed in register 10.

The extraction from the OBO type region of the type byte of the state in response to the incoming channel command is carried out only under the condition that the selected WU is ready to begin the execution of this command. Such an analysis is performed by block 9 according to the contents of register 16, where the current byte of the slave state was previously recorded.

If the slave is ready to execute the incoming command, a sample is taken from the OBS area of the standard status byte with a record in register 16 by analogy with the sample of the current status byte. In this case, the addressing of the type status byte corresponding to the channel command just received is determined by the contents of the lower part of register 2.

If the slave is not ready to execute the posting channel command (the case of unavailability or busyness of the CU), no sample of the standard status byte is attempted.

Block 9 provides data to the channel via the 23 bytes of the status bus (current or typical) stored in register 16, as a result of which the Initial Sample phase ends. After the initial sampling is completed, block 9 writes the interrupt reason code to register 19 and calls the interrupt signal on line 26 through block 17. A typical sequence of actions of the microprocessor program for processing the interrupt signal is the following. The first step in this sequence is to read the contents of register 19. The address of register 19 is received through gaine 25. From the contents of register 19, the microprocessor program determines the cause of the interruption.

In this case, there may be the following message options:

Record type command;

a command like chi

command rejected due to parity error;

the command is rejected due to the lack of acceptable commands in the list (counted in the OBS area);

team entered the chain with the previous team.

Next, the microprocessor program reads the contents of register 11 to determine the number of the selected slave and read the lower part of register 2 to perceive the code of the incoming channel command.

If the incoming command requires data exchange, the microprocessor program loads register 2 with the initial address of the RAM data exchange area, and register 13 with the planned length of the data block. The microprocessor completes the processing of the interrupt by writing to register 16. When writing the OOP code to register 16, block 9 proceeds to perform data exchange, writing a value other than OOP, block 9 considers this value as a status byte and organizes its transfer to the channel. , similar to the transmission in the initial sampling phase. When exchanging data, write block 9 in the standard manner requests the next data byte from the channel and, after it arrives at information bus 20, allows writing to register 16, then initializes block 17 to transfer the received data byte to the microprocessor RAM at the address stored in register 2. After performing this operation, block 17 performs an increase (increment) of the address in register 2 and a decrease (decrement) of the block length value in register 13, the described procedure is repeated until completed and data block transfers. The termination of the transmission of a block of data may occur either upon detection by block 9 of the zero contents of register 13 or at the initiative of a channel when block 9 receives an order from the channel.

Claims (3)

The data exchange of the read type is performed in the same way, with the only difference being that the I7 dp block is first started to read the RAM cell at the address stored in register 2,. and writing the received data byte to the register 16, and then block 9 organizes the transmission of a data byte to the channel via information bus 23. The time diagram of the device operation at the initial sampling stages, transferring the data byte from both the I / O side and the sides of the microprocessor trunk are shown in FIG. 6, where the numbers indicate the tire positions of FIG. 1, After the end of the data transfer, block 9 calls the interrupt procedure by first writing to the register 19 the interrupt reason code, namely the message about the end of the data transfer and the possible detection of errors in the evenness of the data bytes coming from the channel. The microprocessor program processes the interrupt, starting with reading register 19, then reading the information remaining in registers 2 and 13 can be useful. In this case, register 2 contains the address of the RAM cell following the one with which the last data byte was exchanged Register 13 stores the difference between the specified block length and the number of data bytes transferred. The program terminates the interrupt procedure by writing to the 16 byte register of the state containing the pointer. The channel has finished in a possible combination with other indicators (CWC finished, CW finished, Failure in the device, etc.). Block 9 transmits the received status byte to the channel via information bus 2.3 and simultaneously resets register 10, thereby becoming ready to execute commands for other slaves connected to the CC. When an asynchronous state occurs in one of the slaves (for example, the slave ends, Attention), the microprocessor program writes one to the low-order bit of register 13, which is perceived by block 9 as a request for transmitting the asynchronous state byte. Filing is denied by hardware during data exchange and when executing a chain of commands, except for the cases related to the selected slave. Block 9 informs the microprocessor program that it is ready to receive the asyn hron status byte by calling the interrupt procedure, pre-writing the Enable asynchronous status byte code to register 19. After reading register 9, the microprocessor writes the address of the requested slave to register 11, and asynchronous status byte to register 16, after which block 9 transmits it to the channel in the traditional way. With the release of the microprocessor means for executing the next channel commands, a status byte is sent to the device with the obligatory pointer of the CCA finished. This requirement applies both to situations associated with the execution of the current command, and with various types of faults. In the case of general or selective flushes, organized by the channel, block 9 initiates an interruption procedure, presenting in register 19, respectively, the General reset and Selective codes. After the reset procedure is completed, the microprocessor transmits an asynchronous status byte to the device with an HLM pointer ended accompanied, if necessary, by other pointers. If the device performs data transfer or an interruption procedure or stores in the register 16 still unassigned status bytes to the channel, then block 9 in response to the commands sent by the channel responds with a short sequence of control signals from the ULA provided by the input-output interface. Block 9 works as follows. During the initial sampling, the decoder 38 receives, using the bus lines 29, the results of the comparison of the address of the CC and the parity of the address. Only when comparing the address and the correct parity, the decoder 38 begins to recognize combinations of channel and subscriber signals (buses 28 and 31) that are considered related to the interface device. Such combinations can be Connect to interface, Address output, Continue, Status byte issue, Store status, Data byte exchange, Data lock, Stop, Command chain, Interface disconnection, Master reset, Network reset, etc. These control features are stored in register 39. The decoder 36 recognizes operation phases such as Initial Sample, Data Block Exchange, Allow Asynchronous Status Bytes, Interrupt Procedure, Storage of Unrealized Status Byte, Initialization of the Synchronization Unit. The phases of operations are recorded in register 37, Bus 35, which controls the operation of decoders 36 and 38, ensures the ordering of procedures performed by the interfacing device with the channel and trunk. Bus 30 provides block 9 with information about the direction of data exchange, about the need to sample the typical status byte, the application for transmitting the asynchronous status byte, and the completion of the exchange of the data block. The set of subscriber signals, defined by the standard and output to the channel via bus 31, is generated by the AO encoder depending on the current phase of operation and the set control signs and recorded in register 41. The set of signals on bus 32 representing the phases of operation and control signs is used to coordinate the operation of the main units of the device. Unit 7 operates as follows. Depending on the current control phase transmitted via bus 32, the subscriber’s address is generated on AND 43 and 44, and then through OR 45 and 46, it arrives on bus 25 when there is a signal to Set the address transmitted on bus 35. When there is a phase of operation, the Exchange of data block address is formed on the elements AND 44 and is determined by the contents of register 2, to which block 7 is connected via bus 34. In this case, register 2 stores the address of the data exchange area. When there is a phase, the Initial selection is formed on the elements And 43 of the three components / The lower bits are determined by the contents of the lower half of register 2. In the first stage of the initial sample of the external device, the lower part of register 2 contains the UN code, thus providing access to the current bytes state of the VU stored in the OBS area with addresses of the type of UNC. At the second stage of the initial sampling, the youngest part of register 2 stores the code of the incoming channel coders, providing access to the type status bytes corresponding to the received command. Older, address bits are split into two floors with a floating border between them - depending on the number of connected slaves. The high-order field is determined by the contents of register 42, which is a set of jumpers (the maximum number is eight, for the case of connecting a single external device). This field specifies the location of the OBS area in the microprocessor RAM address space. The second field is determined by the VU number stored in register II, which is connected to block 7 via bus 33. The length of this field is dependent on the number of connected VUs. The fixed value of this field corresponds to the set of cells in the OBS region for the selected address of the external device. Claim 1. A device for interfacing microprocessor external devices with a computer I / O channel, comprising a channel information amplifier / receiver unit, an address setting device for an external device control device, an external device control address comparison unit, an parity device, a command decoder, channel control amplifier / receiver block, control block, command register, subscriber control amplifier / transmitter block, evenness bit driver, transmitter / amplifier block subscriber information, the input of the amplifier-receiver channel information unit is the device input for connecting to the output information bus of the channel, and the output is connected to the first information input of the address comparison unit of the external device control unit, parity control module inputs and the decoder com. The output of which is connected to the information input of the command register, the output of the address setting unit of the external device control device is connected to the second information input of the address comparison unit control devices by an external device whose output and output of the parity check block are connected to the first input of the control unit, the input of the channel control amplifier / receiver unit is the input of the device for connection to the output control bus of the channel, and the output is connected to the second input of the control unit, register output commands is connected to the third input of the control unit, the first output of which is connected through the subscriber control amplifier-transmitter unit to the device output for connecting to the input control bus channel la and the second output - to the control input of the bit parity output of which is connected to the input control unit discharge transmitters amplifiers subscriber information, which is output. is an output of a device for connecting to an input data bus, not a channel, characterized in that, in order to expand the class of tasks of the device by providing the possibility of exchanging a group of microprocessor external devices with a computer, a register of the initial address of the exchange domain, block is entered into the device adress formation microprocessor trunk, external device address register, block length register, subscriber address block, AND subscriber address generation, data register, synchronization block, and status register, the output of the channel information amplifier / receiver block connected to the information inputs of the initial address register of the communication region, register addresses of the external device and the data register, the input-output of which is connected to the microprocessor data bus of external devices, with the input-output register of the initial address of the area exchange The data, the external device address register, the block length register and the output of the state register, the register output of the start address of the data exchange area are connected to the first information input of the microprocessor trunk address generation unit, the output of the external device address connected to the microprocessor bus, the input -the output of which is connected to the microprocessor bus control of external devices, the first mA and microprocessor trunk address generator; the first output of the data register and the block output The 35 elements of the subscriber's address generation are connected to the information inputs of the parity check bit generator and the subscriber information amplifier-transmitter block, the output of the block length register 40 and the second output of the data register are connected to the third control block input. 2. The device according to claim 1, wherein the control unit 45 comprises an operation phase decoder, an operation phase register, a control feature decoder, a control indication register, a subscriber control signal encoder and a subscriber control signal registrar, the first the information inputs of the phase decoder of operations and control features are connected to the second input of the control unit, the second information inputs to the third input of the control unit, the third information inputs to the synchronization bus, the control inputs and outputs encoders output synchronization unit coupled to the microprocessor bus interrupt external devices, and a second output connected to the input block length register, a data input of the register state, synchronizing the start address input register for data exchange, the register address of the external device, the data register. the microprocessor trunk address generation unit and the fourth input of the control unit; the output of the address setting device control unit of the external device is connected to the first information input of the subscriber address building block; the second output of the control unit is connected to the command register enable input, the address building block input address the subscriber, the second input of the synchronization block-, the resolution inputs of the state register J with the clock inputs of the external device's address register, the register the initial address of the data exchange area, the microprocessor trunk address generation unit and the data register; control features whose outputs are connected to the second output of the control unit and through the subscriber's control signal encoder to the input regis A control signal path of a subscriber, the output of which is connected to the third information inputs of the phase decoder of operations, the decoder of control features and the first output of the control unit, the fourth information input of the decoder of control features is connected to the first input of the control unit. 3. The device according to claim 1, about tl and which is so that the block forming addresses microprocessor line contains the register of addresses of the status byte region, three groups of elements AND and a group of elements OR, and the control inputs of the elements AND of the first and second groups are connected to the input of the block's resolution, and the outputs - respectively with the first and second inputs of the elements OR, the outputs which are connected to the information inputs of elements AND of the third group, the control inputs and outputs of which are connected respectively to the enabling input and output of the block, the information inputs of elements AND of the first group are connected to the first and second m information input unit and the output of the base address register byte field condition, the data inputs of the second group of AND gates connected to the first data input unit. 2c yjs T1 2 before 2L Pus.2 ffm flOHu J Dm block 11 address U6Udres 5U  l / P Avrvs 6 / 10N 18 Signs upra5 / 1 &, i Nia from 6/1 one 15 FIG. 2fB5P - / (2fflMP-ff -f L. .. |. F.tifHOTI 22 / fffPiJ -Hh-fCZ E 22yOr-a-I -t-ri g1ulrch ll / gl / I. ..- 1. 22CLR- D 22INCHN) (2 tini lOUlHWi SffH n zpsh pnUf-Sx. 25Shya .miHD ZU - Start SbfSoptfQ -l oHOf} bboda fidpec subscriber on SnoK 18 Symptom cpr00peni (Assembly 9) Service ID (Register 11 f Initial sampling of the Seoda channel ID of UVUsdpoka5 X Fav. 7 UJuHQ27.Cu8Hafl confirming operations Shinad2. Signal / g Tire operation operation Shin 5. Havana signal of performance of operations. Signal, reading („recording) ыс systa6 penny on the bus 27 Bus 25. Udres device. gh Fi & .8