SU1410041A1 - Device for interfacing subscribers with computer - Google Patents

Abstract

The invention relates to computing, in particular, to devices for interfacing computers with data transmission channels, and can be used in automated control systems for providing automatic collection and processing of information. The aim of the invention is to increase the speed of information exchange. The goal is achieved in that the device containing the initial pulse shaper, two flip-flops, an input information switch, the first buffer memory block, the first address counter, an output information switch, and an exchange unit, have a block of input amplifiers, a decryption block, and a-tact generator pulses, a decryption unit of the reset signal of the address counters, an address and access switchboard, a second counter to the address, a second block of buffer memory and a block of encryption of the signal of switching memory blocks. 1 hp f-ly, 11 ill. SL

Description

The invention relates to computing technology, in particular to computer interface devices with subscribers, working via data transmission channels, and automatic control systems, and is intended to provide for the automatic collection and processing of information.

The aim of the invention is to increase the speed of information exchange. Fig. 1 shows a structural block diagram of the device; Figs. 2-4 show functional diagrams of a decryption unit of the reset signal of the address meters, a decryption unit of the switching signal of the memory blocks and the exchange unit; Figures 5-9 are functional diagrams of a control signal decoding node, a volume counting node, a readiness signal decoding node, a state identification signal (eats) trigger and a device address setting unit; 10-1 1 - single-signal driver circuits on the front and fall of the input signal and a single signal driver on the I front of the input signal. I The device (Fig. 1) contains a decryption unit, a block of 2 input amplifiers, a driver of 3 pulses, a start of 1 set, a generator of 4 clocks of I pulses, a first trigger 5 of control I, a second trigger 6 of control, block I 7 deciphering the reset signal of the address I counters, the address switch 8 and the I call, the input information switch 9, the first and second counters; 10, 11 addresses, the first buffer memory unit 12, the second buffer memory unit 13, the decoding unit 14 of the switching signal of the memory block, the output information switch 15, the exchange unit 16, the switching inputs 17, 18 and the trigger input 19 of the trigger 5 , setup input 20, inputs 21, 22 and 23 of reset trigger 6; the group of inputs of block 7 includes: input 24 of the output command, input 23 of the signal, the beginning of the text, input 26 of the synchronization, inputs 27 and 28 of the address, switching, input 29 of the command input. 30 input of the initial setup signal.

. The inputs of KOMMyTatopa 8 contain: input 31 of the write address, input 32 of the read address, inputs 33, 34 of enabling the recording of information in the first or second memory blocks (control inputs), inputs 35 and 36 of setting the device operation mode (address inputs) (mode

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receiving information from a source of information or a test control mode) and outputs - address output 37 for memory block 12, address output 38 for memory block 13, access signal output 39 for memory block 12, access signal output 40 for memory block 13 . The inputs of switch 9 contain: test information input 41, address inputs 42 and 43 for setting the ra mode — device bots (information reception mode from the information source or test control mode), 44 44 resolution for recording in the first or second second blocks memory, the second information input 46 (information from the information source), as well as information outputs 47, 48 to the first and second memory blocks. Figure 1 also shows information input 49, address input 50, access signal input 51 and output 52 of memory block 12, information input 53, address input 54, access input 55 and information output 56 of the second memory block 13, group of block inputs 14, information inputs 57 and 58 (information about the bits of the counters 10 and 11), control inputs 59 and 60, input 61 of the signal Start of text, setup input 62, input 63 of the signal End of text, input 64. Synchronization and output 65 memory switching signal. The inputs of the switch 15 comprise: information inputs 66, 67 from the first and second memory blocks 12 and 13, address inputs 68 and 69 (information read permissions from the first or second memory blocks), information inputs 70 and 71 (status information The first and second counters are 10 and 11), the control is the input input 72 of the resolution for reading information about the amount of information stored in the memory, and the information output 73. The inputs of block 16 contain: information input 74, inputs 73 and 76 mode (permission to process test information or from a source of information), input 77 synchronization, setup input 78. 79 input status and outputs: (first) information output

80 (test information), group of exits 81-83; information outlet

81 (in a computer), information identification signal output 82 (signal CPf-Y) and device state identification signal output 83 (CCT signal), input group 84-86; informational

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input 84 (test information from a computer), input 85 of the identification signal of the test information (signal S-B) and input 86 of the identification signal (commands of the OBR signal), (fifth) output 87 of the signal of issuing information about the volume of the information instance, memory, (fourth) output 88 of command Output, (sixth) output 89 of command End of array, J third) output 90 of command Input, (second) output 91 of signals of the address of test information.

Block 7 of decoding the reset signal of the address counters (FIG. 2) contains a single signal shaper 92 on the front and fall of the input signal, element OR 93, groups of elements 94 and 95. The block diagram of driver 92 is shown in figure 10.

The decryption unit 14 of the switching signal of the memory block (FIG. 3) contains AND elements 96 and 97, element OR 98, shapers 99 and 100 of a single signal on the front of the input signal, element OR 101, switches AND 102 and 103 ,. element AND LI 104, element NOT 105, trigger 106, element NOT 107, trigger 108, a group of elements And 109, inputs 110-115 drivers 99 and 100; signal inputs 110, 113, synchronization inputs 111, 114, setup inputs 112, 115 and outputs 116,, 117 of a single pulse of drivers 99 and 100 (drivers 99 and 100 are identical, see Fig.11).

The block 16 of the exchange (figure 4) contains; control signal decoding node 117, the first delay element 118 (one-shot), information register 119, volume counting node 120, readiness signal decoding node 121, the second delay element 122 (one-shot), HE element 123, identification signal trigger 124 state, the second control trigger 125, the second element AND 126, the register 127 bytes of state, the OR element 128, the first control AND 129 control, the device address setting node 130, the encoder 131 state bytes, the first element AND 132, the output switch 133 , a decoder 134 commands, input switch 135, knots l 136 bit-wise modulo two, the comparison circuit 137 addresses, node 138, OR elements, a node output amplifiers 139, node 140

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input amplifiers. The drawing shows the inputs 141 and 142 of the first group: (second) input 143 of the identification signal of the state and, (fourth) input 144 of the identification signal of the command identification, (fifth) input 145 of the recording information of the test information, (first) input 146 of synchronization, inputs 147, 148 commands Output instance volume, Continue input of the second group, (sixth) input 149 signal End command, (third) setup input 150 and outputs: (first O output 151 of information recording permission signal, (second) SI output 152 - Identification of information of node 117; informational input 153, input 154 of permission of the app C and setup input 155 and information output 156 of register 119; counting input 157, start inputs: input 158 of the command Increase the instance volume and input 159 of the Input command, and also installation input 160, output 161 of the signal End of the sample volume and output / i 162 Signal permission to issue an instance of node 120; setup input 163, command input 164 Call, signal input 165 Command end, signal input 166 Error, output group for node 130: output 167 of ready signal and output 168 of signal Not ready and group of codes for encoder 131: Output 169 Signal Not Ready and Output 170 Signal Ready node 121; input 171 (of setting) of the signal. Synchronous address, third, first, fourth and second reset inputs: input 172 of the command identification signal, input 173 of the initial setting, input

174signal End of command, input

175 signal The end of the sample volume and the output 176 of the state identification signal of the trigger 124; a group of inputs 177, 178 of the status byte request signals, data error, a group of inputs 179, 180 readiness, a state identification signal input 181, an initial setup signal input 182, a command identification signal input 183, a call and (second) output 185 of the signal address of the device node 130; (third) input 186 command signals, a group of inputs 187 and 188 readiness, (second) input 189 of the command identification signal

. (first) input 190 of the signal Error, I (fourth) input 191 of the signal Switching memory blocks and a group of outputs 192 of the encoder 131; information inputs 193 (information from memory blocks) and 194 (status bytes), the third, first and second address inputs 195-197 and output 198 of the output switch 133; information input 199 (input 2–8 of the input information bits); input 200 of the enable signal for receiving commands from the decoder 134; information input 20.1; input input permission 202; and information output 203 of input switch 135; input 204 information and output 205 test bit of the node 136; (second) input 206 (1-3 bits) of the input information and the first input 207 (of the device address signal), output 208 of the comparison circuit 137, inputs 209, 210 and output 2 1 1 of node 138; the second, third and first inputs 212-214 of node 139 and the first to third inputs 215-217 of node 140.

The control signal decoding node 117 (FIG. 5) contains a single signal shaper 218 on the front of the input signal, a single signal shaper 219 from the input signal decay, trigger 220, AND 221 element group, OR element 222, And 223 element, trigger 224, inputs 225 228: the signal inputs 225, 227 and the inputs 226, 228 of the synchronization of the formers 218, 219. The block diagrams of the formers 218, 219 are shown in FIG. 11 and 11.

The volume counting unit 120 (FIG. 6) contains a two-bit counter 229, a trigger 230, an AND element 231.

Node 121 of the signal readiness (Fig.7) contains a dial-in field 232, triggers 233, 234, OR elements 235, 236, 237, triggers 238, 239, And elements 240, 241, triggers 242, 243 ,. indicator 244, elements And 245, 246. The dial-pad 232 consists of two buttons located on the front panel of the device. Indicator 244 contains an amplifier on a microcircuit and three indication lamps (not shown), recording the presence of signals Ready, Not ready, Error.

The trigger 124 of the state identification signal (FIG. 8) consists of a NOT element 247, an OR element 248, and a trigger 249.

The device address setting node 130 (FIG. 9) contains OR 250, 251 elements, a dial-in field 252, a trigger 253, an AND 254 element, a AND 255 element group.

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Typesetting field 252 consists of eight toggle switches (not shown). When each toggle is turned on, a signal is sent to one of the device’s eight output buses, depending on the address assigned to this device in the system to which the specified device belongs;

Shaper 218 single signal on the front and fall of the input signal (figure 10) contains the element NOT 256, triggers 257, -258, elements And 259, 260 and 261.

Shaper 219 single signal on the front of the input signal contains the element NOT 262, triggers 263, 264, elements And 265, 266, 267.

In the drawings figure 10, 11 shows the inputs 268-271: signal inputs 268, 270 drivers, inputs 269, 271 synchronization, outputs 272, 273.

The device performs the following functions:

- receiving information from the source of information;

-conversion of the n-bit parallel code from the information source to the eight-bit parallel code with a check bit;

- accumulation of information received from a source in a buffer memory device;

-transfer accumulated; and | {formations in a computer.

The device can operate in two modes: test control; receiving information from the source of information.

The operation of the device is as follows:

a) turn on the device;

b) control of its working capacity by entering the device into the array of test information from the computer and its subsequent input into the computer for comparison with the initial one; If the control results are positive, the device is ready to work in the mode of receiving information from the source of information;

c) when a device receives information from the source, it is automatically received (based on the beginning of the text signal) and then converted and written to the memory;

d) by filling the memory (or by the end of text signal) the interface communicates with the computer and transfers the accumulated information array there, simultaneously receiving information from the source and writing it into the memory, this process can last until until the source has stopped transmitting information;

e) if work with the source of information is completed. and no new information is expected, the device can be turned off. j

Information is exchanged between the device and the computer, for example, in accordance with the standard OST 4.GO 304202. Based on the specified OCT 15, diagrams J were developed, defining the exchange process between this device and the computer.

Communication between the device and the computer is carried out on 22 buses, 11 of which are used to transmit information from the computer device (called SHIN-U), as well. the other 11 are used to transmit information from a computer (called SHIN-B) to the device, with 18 buses 25 used for transmitting information, and 4 for transmitting identification signals.

Identification signals (called SI-B, OBR, SI-U, eats) are used by ZO to determine the type of information that is available on tires SHIN-B and SHIN-U, as well as for mutual blocking of signals from the device and the computer.

Signals SI-B and OBR determine the type g of information transmitted on 1IN-B. The presence of an OBR signal indicates that on SHIN-B there is a device address code, which is assigned to it as a computer subscriber and with which 40 communications and a command code are established. Address transmission is carried out via tires TIR-B1 - TIR-BZ (1-3 bits), transmission of a command via TIR. B4 - TIR B8 (4-8 bits). The presence of a SI-B signal in the presence of an OBR indicates that there is a data code on TIR-B.

The SI-U and SCT signals determine the type of information transmitted over SHIN-Y. The presence of a CCT signal indicates that gQ on the TIR-Y has a status code. The presence of a SI-U signal in the presence of a CCT indicates that there is a data code on TIR-B. OBR and CCT, CI-B and CI-U signals are interrelated: the appearance of the OBR signal causes a response CCT signal, the removal of the OBR signal leads to the removal of the CCT signal, the appearance of the SI-B signal leads to the appearance of the SI signal On the contrary, the removal of the SI-B signal leads to the removal of the SI-U signal. During the exchange, the interface and computer devices use the following commands and states:

Input - a command from a computer on which the device begins to enter information into the computer;

Continue the computer command, on which the Device resumes entering information if there has been a computer-initiated interruption;

The output is a command from a computer, according to which the device is prepared for the test information premium and starts receiving data;

Continue output - a command from a computer, according to which the device resumes receiving test information if there was a break at the initiative of the computer;

The end of the array is a computer command, according to which the device completes the reception of test information and is prepared for its transmission to the computer;

Increase the sample size - the command, according to which the device must transmit to the computer data on the amount of information stored in its memory and to be transferred to the computer;

Give out state - a command from a computer, according to which a device must transmit information about its state to a computer;

A call is a command from a computer that is transmitted in the event of errors in the transmitted information that cannot be corrected automatically, provided that the computer conducts a test control of the device or has finished receiving information from the source of information; on this command, the device stops all operations until operator intervention;

Ready - a state transmitted from the device and meaning that it is ready to perform the operation. To continue the exchange with the computer after execution of the previous command;

, Not ready — a state that is transferred from the device and means that it has completed all operations; this state occurs when a call command is received by the device and when it is transferred to this state by the operator for the purpose of checking or switching off;

Continuation is a state transmitted from the device and meaning.

that it is ready to receive or transmit information;

Request - the state transmitted from the device and indicating that it has completed receiving information from the source and is ready to be transferred to the computer;

Data error - a state transmitted from the device and indicating that it detected error when monitoring information received from a computer ...

The exchange of information between the device and the computer occurs in the following order:

- when the device is turned on and the Ready button is pressed, one of the BUS-U (corresponding to the block address) will receive the Call signal; The computer sends an OBR signal to the device and a command to issue a state, while the call signal is removed and the device exits the Ready state accompanied by the CCT signal;

. - The computer transmits to the device a command Output accompanied by OBR, to which the device responds with a Byte of the status Continued accompanied by a CCT signal.

-The computer transmits to the device a command Output accompanied by the CER, to which the device responds with a state byte. Continued in concurrent signaling of the CCT;

: - The computer sends the test information | bytes of data to the device, to which the device, having received in rare-byte data, responds with the CI-U signal, if the test information is transmitted to the device in parts (with interruptions), The computer, stopping the transmission of information, removes the signal REF., To which the device responds with a signal call;

- The computer transmits to the device a command to output a state, to which the device responds with a Ready state byte or a Data Error;

- A computer in the case of a flash can repeat the output of test information, starting with the transfer of the Output command to the device, based on the results of a three-time (if necessary) output of test information

The computer decides on the continuation of the test control device;

- if the errors in the data are eliminated, do not exist, the computer transfers the device to the call command, after which it is searched and eliminated

The fault is faulty, and the device is set to Not Ready;

- at the end of the transmission of the entire array of test information, the computer transmits the command End of the array to the device, to which the device responds with the Ready state byte or Data error; In case of an error, the computer can repeat the output of the entire array of test information, starting with the Output command;

- if errors in the data were eliminated, the device, at the command of the End of the array, is transferred to the mode of transferring test information to the computer and transmits the Call signal to it;

- The computer sends the Instance of Instance command, to which the device responds with the Continuation state byte, and then transmits two bytes of information about the amount of information that it is ready to transmit to the computer;

- after transmitting information about the amount of information, the device removes the CCT signal and sends a call signal to the computer;

-The computer transmits the state condition command, to which the device responds with the Ready state byte;

. - in case of computer failure, it can re-enter (up to three times) the input of information about the amount of information;

- if errors in the data were eliminated, the computer transmits the Enter command, to which the device responds with a status byte, and then begins to transmit test information in the exclusive mode;

- upon completion of receiving test information, the computer removes the OBR signal, to which the device sends a call signal;

-The computer transmits the state condition command, to which the device responds with the Ready state byte and waits for information from the information source;

- when the device receives information from the source, it receives it, transforms it and memorizes it;

- upon completion of reception (memory filling or signal arrival, corresponding to the end of the incoming information array), the device transmits

in a computer signal Call;

, - further occurs. the process of entering into the computer an array of information from the source

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nickname dan, which is similar to entering an array of test information.

The device works as follows.

When the power source of the device is turned on, the former 3, which is a generator of a single pulse, produces a specific duration, which is recorded at block 11 (input 51) of the block 12

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Lem 92, which receives a signal from the output of the trigger 5 (input 27) and clock pulses from the generator 4 (input 26). From the switch 9, information arrives at block 12, where information is recorded. With the simultaneous presence of information at the inputs (input 49), addresses (input 50) and access

reset the device nodes.

The signal of the initial installation, the incoming on the trigger input 5, occurs switching switches 8, 15 trigger input 5. (Input 18), the signals

9 and 15 in such a way that the recording of incoming information is possible first in block 12 of memory. The memory unit 13 at this time is turned on for reading / In addition, the initial setup signal switches the trigger 6 to a position that records information from the source of information.

The generator 4 clock pulses produces the generation of synchronization pulses necessary for the operation of the device nodes. The switch 8 outputs which switches the switches, so that the recording of the incoming information is possible in the memory block 13. With block 12 we can

20, information is read through the switch 15 and the block 16. In the test control switching mode. blocks 12 (13) occurs with the help of the command End Array, which

25 steps into the trigger input 5. In block 14, a signal is generated at. switching in the following cases: upon receipt of an array of information exceeding the volume of two blocks 12

25 steps into the trigger input 5. In block 14, a signal is generated at. switching in the following cases: upon receipt of an array of information exceeding the volume of two blocks 12

lt From the sync signal accompanying

each byte of incoming information, sigzo and 13 memories; upon receipt, the address and address arrays, which are necessary information in the volume, are needed to record information in the memory block. From the switch 8, the address goes to the counter 10, which is currently enabled to record information. The access signal from the switch 8 is fed directly to block 12.

bones of one buffer block, but less than two; upon receipt, the array of information in-volume is less than one memory block.

Switching the blocks 12 (13) of the buffer memory is carried out only under the condition of complete reading of information from block 13 (12), which was Q in read mode.

Block 7 produces the generation of reset signals for counters 10 and 11 in the following cases:

a) when the device is turned on by a signal coming from the expander of the imaging unit 3 (input 30);

b) on the basis of the beginning of the text coming from the output of block 1 (input is what means its filling.

25)

c) software for computer commands: Input (input 29), i.e. before reading the information from the completed block 12 (13); . Output (input 24), i.e. before recording the CQ test information in block 12 (13).

There is also a reset of the counter 10 (11) before writing the information into block 12 (13), which is currently on write, and after reading the NIN information from block 13 (12), which was in read mode. This mode is carried out by forming pulses forming the element AND 96 or 97 will form a signal that is fed to one of the drivers 99 or 100 to form a single signal on the front of the input signal. The signal received by the formers 99, indicating that one of the blocks 12 (13) of the memory is full, goes to the switch 1Q2, where the signals from the trigger outputs 5 are used as switching signals. From the switch output 102 the switch signal goes through the HE 107 element input of group of elements I 109 and further

each byte in memory.

By filling the memory or on the basis of the end of the text, block 14 generates a signal arriving at the counting

from which switches are switched, so that the recording of incoming information is possible in memory block 13. From block 12 may

the information is read through the switch 15 and block 16. In the test control mode, the switching of blocks 12 (13) occurs using the command End of the array, which is fed to the input of the trigger 5. In block 14, a switch signal is generated in the following cases: when the array arrives information greater than the volume of two blocks 12

and 13 memories; upon receipt of a set of information in the volume

o and 13 memories; upon receipt of a set of information in the volume

bones of one buffer block, but less than two; upon receipt of an array of information in-volume is less than one memory block.

Switching the blocks 12 (13) of the buffer memory is carried out only under the condition of a complete reading of information from the block 13 (12), which was Q in read mode.

In the first case, the state of the outputs of the counters 10 and 11 on the elements And 96 and 97 is analyzed. If all sections of the counter 10 or 11 take on the meaning, which means its filling.

An AND 96 or 97 element will generate a signal that is fed to one of the drivers 99 or 100 to form a single signal on the front of the input signal. The signal received by the formers 99, indicating that one of the blocks 12 (13) of the memory is full, goes to the switch 1Q2, where the signals from the trigger outputs 5 are used as switching signals. From the switch output 102 the switch signal goes through the HE 107 element input of group of elements I 109 and further

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at the output of the block. The signal from the com-: mutator 102 switch triggers the I 106 trigger, thereby ensuring that the I signal does not pass through the end of the text, so that the memory block 13 does not switch before the memory 12 is finished before the reading of the block 12 occurs. read mode. In the second case, the signal is received. The end of the text is possible earlier than it is read out from memory block 12. In this case, to ensure timely switching of the memory, the signal of the end of text is stored on trigger 108 and when a signal is received about the end of reading from the switch 103 to the AND 109 elements, a signal is generated to switch the memory blocks 12 (13). Upon receipt of an array of information in the amount of less than one block 12 (13) signal The end of the text comes from the second

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output of block 1 to the input of block 14. Directly to the elements And 109, ensuring the generation of a switching signal.

The exchange unit 16 operates in three modes:

-inclusion and logical connection to the computer;

- test control;

- receiving information from the source of information.

When the device is turned on, the exchange unit 16 receives a setup signal, which sets its elements in the initial state. When you click the Ready button, node 121 issues a signal to the encoder 131 state bytes and node 130 to prepare the Ready state byte and the Call signal. Formed

 the status byte Ready is stored in a register of 127 status bytes. If the input bus OBR no signal, the signal Call through nodes 138 and. 139 arrives at the SN-V corresponding to the address of this device, which is installed on the dial field 252. Connecting the device to the computer begins with the command Give state in accompanying the identification signal OBR, by which the call signal is removed. Decryption of incoming commands to the device takes place with the help of |; encoders 134 and 137. If the address of the incoming command coincides with the device address, circuit 137 compares

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from the enable signal, by which the decoder 13A decrypts the incoming command. The decoded command is used to form the status byte, and the signal from the output of the AND element 132 arrives at the trigger 124 to form the identification signal eats. Having received the status byte, the computer removes the command and the BREAK signal. When the command is removed, the signal End of the command is generated at the output of element 122, and the command ends at the trigger 124, which leads to the removal of the status byte from 111IN-Y. After that, the computer conducts a test check of the device, producing output to the device and inputting an array of test information from it using the commands Output, Continue output, End of the array. When a Vyogod command is received, accompanied by an OBR, the device generates and sends to the computer the state byte of the continuation accompanied by the CCT. After removing the command Output from TIR-B from TIR-U, the status byte is removed, and a input byte of test information is sent to the input buses of TIR-B, accompanied by the SI-B identification signal. The SI-B1 gate, which arrives at output 91 and then to switch 8 and is used as the address for recording test information in block 12 (13), at the output of trigger 129 is formed an iCHPHan, which arrives at switch 135, as a signal to allow passage of input information. At the same time, the output from the element 118 enters the input of the node 117, where on the front of the incoming signal using a shaper, 207 a response signal SI-V is formed. Accepting a signal from a SI-U computer removes a data byte from SHIN-B and a SI-B signal. When removed, the device removes the SI-V signal. After that, the computer exposes the next byte of data to the TIR-B, accompanied by the C-B. In the event of an error in the data byte, the error signal. From node 136 is sent to the encoder 131 to form a byte of data error, having received a computer, can repeat the output of the test information. If the error is not satisfied with a three-time replay30

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then, the computer sends the call command, incoming messages to the node 121 from the decoder 134, upon reception of which the device generates a state byte

from the enable signal, by which the decoder 13A decrypts the incoming command. The decoded command is used to form the status byte, and the signal from the output of the AND element 132 arrives at the trigger 124 to form the identification signal eats. Having received the status byte, the computer removes the command and the BREAK signal. When the command is removed, the signal End of the command is generated at the output of element 122, and the command ends at the trigger 124, which leads to the removal of the status byte from 111IN-Y. After that, the computer conducts a test check of the device, producing output to the device and inputting an array of test information from it using the commands Output, Continue output, End of the array. When a Vyogod command is received, accompanied by an OBR, the device generates and sends to the computer the state byte of the continuation accompanied by the CCT. After removing the command Output from TIR-B from TIR-U, the status byte is removed, and a input byte of test information is sent to the input buses of TIR-B, accompanied by the SI-B identification signal. The SI-B1 gate, which arrives at output 91 and then to switch 8 and is used as the address for recording test information in block 12 (13), at the output of trigger 129 is formed an iCHPHan, which arrives at switch 135, as a signal to allow passage of input information. At the same time, the output from the element 118 enters the input of the node 117, where on the front of the incoming signal using a shaper, 207 a response signal SI-V is formed. Accepting a signal from a SI-U computer removes a data byte from SHIN-B and a SI-B signal. When removed, the device removes the SI-V signal. After that, the computer exposes the next byte of data to the TIR-B, accompanied by the C-B. In the event of an error in the data byte, the error signal. From node 136 is sent to the encoder 131 to form a byte of data error, having received a computer, can repeat the output of the test information. If the error is not satisfied with a three-time repetition5

then, the computer sends the call command, incoming messages to the node 121 from the decoder 134, upon reception of which the device generates a state byte

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He is ready. If the entire array of test information is received without errors, the device generates the Ready state byte, and the node 130 generates a Call signal. In response to an incoming command, Issue status. accompanied by an OBR signal, the device removes the signal call and places a Ready state byte on the SHIN-U, accompanied by a CCT signal. The computer, having received a status byte, removes the command and signal from the switch, and the device removes the state byte and the CCT signal. The computer confirms that the entire array of information is transmitted by the command End to the Mass, to which the encoder 131 forms the Request state byte, and the Call, i.e. The device is ready to transmit the received test information.

Claims (1)

1. A device for interface of subscribers with a computer, containing two control triggers, the first block of buffer memory, information and address inputs of which are connected respectively to the first output of the input information switch and the output of the first address counter, and the output is connected to the first information input - the output information tator connected by the output with the information input of the exchange unit, the first output of which is connected to the first information input of the input information switch, and the output group and information group The inputs are the corresponding groups of outputs and inputs of the device for connecting to groups of information control inputs and outputs of a computer, and an initial setup pulse shaper, the output of which is connected to the reset input of the first control trigger and the first reset input of the second control trigger, characterized in that In order to increase the speed of information exchange, a second block of buffer memory, a second address counter, a clock generator, a block for decoding a memory switch signal are inserted into the device, ommutator addresses and handling unit decoding signals reset counters JKOB address block of input amplifiers and decryption unit, the second WMOs 10041 - 16 the reset of the second trigger of the puncture is connected to the first BiirxonoM of the depygif rashch block, the input connected to the first one from the outputs of the block of input amplifiers, the second output of which is connected to the second information input of the input switch, the group of address inputs of which is connected to the outputs 10 of the first and second control flip-flops, and the second output — with the information input of the second block of buffer memory, the address input and output of which are connected respectively to the output 15 of the second address counter and the second information input of the output information switch, the third and fourth information inputs of which are connected respectively to the outputs of the first and second address counters, and the address input to the output of the first control trigger and the address and access switch enable input address of which connected to output25 the house of the second trigger control, and the first and second information inputs, respectively, with the third output, the input amplifier unit, and the second output of the exchange unit, the mode input of which is connected to the output of the second control trigger, and the status input to the counting input of the first control trigger and the output of the memory switching signal decoding unit , the group of which is connected to the outputs of the first and second address counters, the first control trigger, the first and second outputs of the decryption unit, and the driver outputs the pulse of the initial installation and the generator of clock pulses, the counting inputs and the reset inputs of the first and second counters of the address are connected respectively to the first and second terminals, Dami of the decryption block for resetting the address counters, the group of inputs of which is connected to the outputs of the first control trigger, the impulse generator of the initial setup, clock generator, the first output of the decryption block, the third and fourth outputs of the exchange block, the fifth and fourth outputs of which are connected respectively to the control the output of the output information switch and the installation input of the second control trigger, and the sixth output with the third reset input of the second control trigger and the installation .17I The first input of the first control trigger, the access inputs of the first and second buffer memory blocks are connected to the third and fourth outputs of the address and access switch, the power input and the initial setup of the exchange unit, respectively, are connected to the outputs of the clock generator and pulse generator of the initial setup. 2; A device as claimed in claim 1, o-TL and of course that the exchange unit with the h; holds a node of output amplifiers, the group of outputs of which is a group of outputs of the block, the node of input amplifiers, group of inputs of which is a group block inputs, an input switch whose output is the first block output, an output switch, a node of elements of the RShI, a node for specifying an address, a device, an address comparison circuit, a coder for status bytes, a command divider, a node for bit-modulo two, egist of state bytes, node of the count of the record, node of decryption ready signals, information register, whose information input is the block information input, state identification signal trigger, node, | 1; control signal decoding, first: left input. and group of inputs are respectively a synchronizing input and input block5 mode two eletiHTa delays, two AND elements, two control diggers, an OR element and an Element, and the information register resolution enable input is connected to the counting input of the volume counting node Ill by the first output of the control signal decryption node, the second output ohm connected to the first input node of the output amplifiers and the first address-liiy input of the output switch, the output and the first and second information inputs of which are connected respectively to the first input of the node of the 1PI elements, the outputs of the information register and the register of the status bytes, the output of the identification signal trigger the state is connected to the second input of the Decryption of control signals node, the second is the address input of the output switch and the second input of the node of the output amplifiers, the third input is connected to the output of the node of the I.PI element, The second Yoy whose entrance is connected to the output 4118 house of the device address setting node, the second output connected to the first input of the address comparison circuit, and the initial installation input - with the initial installation input of the block, the reset inputs of the first control trigger register, information and the volume counting node 5 with the first reset input trigger of the state identification signal, the first input of the decryption node of the ready signals and the third input of the decoding node of the control signals, the second group of inputs JKOToporo is connected to the group of outputs of the command decoder, the resolution input of which is connected to the first installation input of the first control trigger, the installation inputs of the second trigger and the state identification trigger, the second reset input connected to the first output of the account node. This volume, the second output and the group of start inputs of which are connected respectively to the fifth output of the block and the group of outputs of the command decoder, the first output of the node of the output amplifiers is connected to the information inputs of the input switch and the decoder commands, the second input of the address comparison circuit and through a node of modulo two incrementally with the first inputs of the first AND element and the state byte encoder, the second inputs of which are connected to the second output of the node of the amplifiers, the identification input of the command of the device address setting node, the second input installation of the first control trigger, the third reset input of the state identification signal trigger, and the fourth input of the control signal decryption node, the fifth and sixth inputs connected respectively to the outputs The first and second delay elements, whose inputs are connected respectively to the outputs of the NOT element and the second control trigger, the reset input of the OR element connected to the output, whose input group is connected to the group of outputs of the decoder of commands, the third output of the node of the input amplifiers and the output of the control trigger, respectively and the second inputs of the second element AND, the output of which through the element is NOT connected to the enable input of the input switch, the group of outputs of the command decoder is connected to the three the third, fourth, and sixth outputs of the block, the third input of a state-byte corrugator, and the second input of the readiness decryption node, the third input of the second state identification signal trigger connected to the output of the second delay element, the fourth input of the state byte encoder the block state input, and the output group is connected to the group of state inputs of the node specifying the device address, the group of inputs of the status byte register and the fourth input of the readiness signal decryption node the first and second groups of outputs of which are connected respectively to the group of inputs of the nafaftorator state bytes and the group of inputs of readiness of the node for specifying the device address, the output of the address comparison circuit is connected to the third input of the first And element, the third address input of the output switch is connected to the mode input of the the output of the first delay element is the second output of the block; the status identification node input of the address setting unit is connected to the trigger output of the state identification signal. e-iD fe  rv. rVx I am an od CD iPue. eight