SU1372347A1 - Device for receiving and transmitting information - Google Patents

Abstract

The invention relates to a radio communication technique and can be used for receiving and transmitting information in systems with a large number of transmitters and receivers operating in one communication channel. purpose

Description

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invention - increasing the reliability of receiving information by eliminating its loss during the transmission of confirmation device. The device contains a receiver 1, selector unit 2, selector 3 1gul, first element OR 4, shaper 5 clock pulses, counter 6, first element And 7, first register 8 shift, second shift register 9, third shift register 10, comparison unit II, memory block 12, second element OR 13, reset pulse shaper 14, trigger 15, information block 16, unit code shaper 17, cool code shaper 18, transmitter 19 channel 20 connection, in the information block element And 21, generator 22, counter 23, switch 2A, information723Д7

The input inputs are 25. In this device, the received information is written into the information register, and after determining the correspondence of the address of the received information to the specified one, it is written into the buffer register for further processing. At the end of the reception of information, a signal appears at the output of the first element AND, the second element OR, and the reset pulse shaper, which prepares the receiving branch of the device for the next reception without waiting for the end of the acknowledgment codogram. This ensures parallel operation of the receiving and transmitting branches, which eliminates the loss of information 1 or

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The invention relates to radio communications, in particular, to systems for receiving and transmitting information, and can be used to transmit and receive information transmitted in binary code in systems with a large number of receivers and transmitters operating in the same communication channel.

The purpose of the invention is to increase the reliability of the reception of information by eliminating its loss during the transmission of acknowledgment-1.

The drawing shows an electrical functional diagram of an apparatus for receiving and transmitting information.

The device contains receiver 1, unit selector 2, selector 3 zero first element OR 4, shaper 5 clocks, counter 6, element 7, first 8, second 9 and third 10 shift registers, comparison unit 11, memory block 12, second the OR 13 element, the reset pulse shaper 14, the trigger 15, information} a.Y. block 16, the unit code generator 17, the zero code generator 18, the transmitter 19 and the communication channel 20

The information unit 16 contains the element And 21, the generator 22, the counter 23, the switch 24 and the information inputs 25.

The device works as follows.

When a code combination is received, the signals from the receiver output I are fed to the inputs of the selector 2 units and the selector 3 zero. When the unit code is received, the potential at the output of the selector 2 becomes one, and the output of the selector 3 remains zero. When receiving a code zero, the potential at the output of the selector 3 takes the value of one, and at the output of the selector 2, the value zero. Thus, as a result of the arrival of any elementary parcel containing the code attribute zero or unit, signals at the output of the first element OR 4 appear at the unit level, which are fed to the input of the clock generator 5, designed to generate signals of a certain duration. The signals from the output of the imager 5 clock pulses

arrive at the first inputs of the counter 6 and the clock inputs of the first register

8 shift address) and the second register 9 (informational) and element And 7 "With the help of these pulses information is recorded coming from the input of the device through the unit selector 2 and its bit advance along the information register 9, and then the address register 8, and each shift clock pulse corresponds to a shift of the number recorded in the register by one bit. Counter 6 counts the incoming clock pulses and when the nth number of pulses at its output reaches, the potential of the unit that arrives is reached m input AND gate 7. At this time, all the received information packet is recorded in the information and address register 9, and 8, wherein the register 9 - the information part, and the register 8 - Address,

In the comparison block 11, the information recorded in the memory block 12 is compared with the information recorded in the address register 8. If the information is the same (the signals from the outputs of these blocks are the same), this indicates the address status of the received information to the device address of the comparison unit 11, a signal arrives at the second input of the element AND 7, at the output of which a signal of the unit which transfers the flip-flop 15 to the one state is output, and, arriving at the control input of the third shift register 10 (buffer), It records the information part of the received codogram into it for further processing.

At the end of the clock pulse from the output of the generator 5 clock pulses, the signal at the output of the element And 7 and the second element OR 13 disappears. On the reverse differential (front) of the signal, the reset pulse shaper 14 generates a pulse, which resets the address and information registers 8 and 9 and counter 6 to the initial state and prepares the device to receive information. If, as a result of the comparison, the received address does not coincide with that recorded in memory block 12, the signals at the outputs of the comparison block 11 and the And 7 element are missing and a confirmation message is not generated.

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The triggering signal 15 is fed to the first inputs of the unit code generator 17 and the zero code generator 18, as well as to the transmission enable input (input element I 21) of the information block 16, allowing them to work. In this case, the pulses from the generator 22 of the information block 16 are fed through element 21 to the counting input of counter 23, the second outputs of which control the operation of the switch 24. Under the influence of these pulses, the switch 24 alternately connects the output to one of its inputs, thereby transforming the parallel code recorded at the information inputs of the information block 16c, sequential, the resulting code is fed to the third inputs of the shapers 17 and 18 of the code unit 1; s and zero, to the second inputs of which the post also signals from the output There are 22 clock pulses, where the t-mpoBaHMbie in the generators 17 and 18 of the unit code and the zero code send signals confirming reception of the information are encoded appropriately at the inputs of the transmitter 19 and further on the communication channel 20. (k - clock pulses of the generator 22) at the second output of the counter 23 a pulse appears which sets the trigger 15 and the counter 23 to the initial zero state,

The number 1 of the bits of the address register and the outputs of the memory block is equal to the number of elementary parcels in the address part of the codogram (the number of bits needed to write in the binary code of the addresses of the receivers connected to the communication line). The number m bits of the information register is equal to the duration of the information part. cograms The number n of the counter bits is equal to the total length of the codogram () o

The number K of the counter bits in the information block is equal to the length of the service confirmation record and must satisfy the condition K p,

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Claims (1)

Invention Formula The device dp reception and transmission of information containing the receiver, whose input is connected to the communication channel, the receiver output is connected to the input of the unit selector and the zero selector, the output of the zero selector is connected to the first input of the first element 11G1I, the output of the unit selector is connected to the second input of the first element tLHH , the first shift register, the outputs of which are connected to the corresponding first inputs of the comparison unit, the second inputs of the comparison unit are connected to the outputs of the memory unit, the output of the comparison unit is connected to the first input of the element P1, the output of the first element OR is connected to the input of the clock pulse generator, the counter, the output of which is connected to the second input of the element AND the input element And in the In-Iurmation block, the output of which is connected to the first input of the counter, the output of the counter is connected to the input of the switch, the output of the switch and the E1formation unit are connected to the second inputs of the drivers of the unit code and the zero, the group of inputs, the switch of the information block is the information input of the device, the output of the clock generator of the information block is connected to the third input of the drivers of the unit code and the zero and hectares of the information block with 0 five 0 five 0 five the second input of the element I, the second output of the counter of the information unit 1 is connected to the second input of the trigger and its second input, the output of the unit code generator is connected to the first input of the transmitter, the output of the code generator zero is connected to the second input of the transmitter, the output of which is connected to the communication channel differing the fact that, in order to ensure the reliability of information during its reception, the second and third shift registers, the reset pulse shaper, the second OR element, the output of the unit selector are connected to the first in One second shift register, a group of outputs of which are connected respectively to the inputs of the third shift register, the output of the second register is connected to the first input of the first shift register, the output of the clock pulse generator is connected to the second inputs of the first and second shift registers, to the third input of the And element and to the first input the counter, the output element And is connected to the input of the third shift register and the input of the second element OR, the output of which is connected to the input of the driver of the reset pulse, the output of which is connected to the second input With the meter and the third inputs of the first and second shift registers, the output of the third register is the output of the device.