SU1325545A1 - Information reception and transmission device - Google Patents

Abstract

The invention relates to the reception and transmission of information and can be used to transmit and receive information transmitted in binary code in systems with a large number of receivers and transmitters operating in the same communication channel. The purpose of the invention is to increase the reliability of the reception and transmission of information. In the reception mode, the address of the called device is fed to the first inputs of the comparison block 10. If this code coincides with the code recorded in the memory block AND, the comparison unit 10 through the element 12 and the trigger 15 initiates the transfer of data. After polling all the information inputs 24 of the device, the counter 22 returns the trigger 15 to its original state, stopping the transmission. The device protects the counter 14 from being reset to the initial state against interference impulses arriving at the input of receiver 1. I Il. (L with oo 1chE sd 01 NU SP

Description

The invention relates to the field of receiving and transmitting information and can be used to transmit and receive information transmitted in binary code in systems with a large number of receivers and transmitters operating in the same communication channel.

The purpose of the invention is to increase functional reliability.

The drawing shows a diagram of the device.

The device comprises a receiver 1, a selector unit 2, a selector 3 zero, an element OR 4, elements AND 5 and 6, a driver 7 clock pulses, a counter 8, a shift register 9, a unit 10 of comparison block 11 of memory, an element 12, an element I 13 , second counter 14, trigger 15, unit code generator 16, zero code generator 17, transmitter 18, information block 19, consisting of a 20 clock pulse generator, And 21 element, counter 22 and switch 23, information sources 24 and channel 25 zi

The device works as follows.

When receiving a regular code combination, the signals from the output of the receiver 1 are fed to the inputs of the selector 2 units and the selector 3 zero. When a unit code appears in any bit at the output of the selector 2, but the signal is "1, and on the output of the selector 3, the signal is" O. When code zero appears, the signals at the outputs of the selectors change, i.e., at the output of the selector 2, the signal "O" is present, and at the output of the selector 3 - the signal "1.

Consequently, as a result of any elementary parcel containing a code feature entering the device, the output of the first element OR 4 results in signals with the level "1. The inputs of the elements 5 and 6 receive signals “1, respectively, from the output of the element NOT 13 and the output of the trigger 15. Signals“ 1 from the output of the element OR 4 arrive through the elements 5 and 6 to the input of the driver 7 clock pulses, which generates signals of a certain duration and sends them to the clock input register 9 and the counting input of the counter 8. Using these pulses, information is recorded in the shift register 9 in accordance with the values of the code received at its information input from the selector 2, and each Each shift of a clock pulse corresponds to a shift of the number written in the register by one bit. With the arrival of each new clock pulse, the second counter 14 is established in the initial (zero) state. The level “About the output of the second counter 14 allows the operation of the first counter 8. Counter 8

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counts the incoming clock pulses, and when reaching the Nth number of pulses (N is the number of register bits required for recording information), the signal "1" arrives at the input of the HE element 13 and the second input of the second And 12 element appears at its output.

At the same time, the signals arriving at block 10 from the outputs of register 9 and the outputs of the block AND of memory are compared.

If the signals are the same, at the output of the comparator unit, the signal "1, which, having passed through the element 12, appears, arrives at the first input of the trigger 15 and transfers it to the single state. The signal from the direct output of the trigger 15 is fed to the inputs of the shaper 16 of the unit code and the shaper 17 of the zero code and to the second input of the And 21, allowing it to work. At the second output of the trigger 16, the signal “O” appears, which, entering the input of element 6, prohibits the input of signals to the input of the imaging unit 7, and consequently, the formation of clock pulses by the imaging unit 7. The signal “O from the output of the imaging unit 7 enters the installation input it counts the pulses received at its counting input from the output of the generator 20 of the information block 19. When the counter 14 reaches a certain number, a signal appears at its output, which sets the counter 8 to the zero (initial) state.

The pulses from the generator 20 are fed through the element 21 to the counting input of the pulse counter 22, the first outputs of which control the operation of the switch 23. Under the action of these signals, the switch 23 alternately connects the output to one of its inputs, thereby transforming the parallel code written on inputs 24, sequential.

The resulting code is fed to the inputs of the shaper 17 of the pool code and the shaper 16 of the unit code, the other inputs of which receive signals from the generator 20, where they are coded accordingly.

The generated code send signals confirming the reception of information by this particular receiver arrive at the inputs of the transmitter 18, and from its output to the channel 25 of communication. After the switching of the information inputs of the device is completed, a pulse with a level of "1" appears at the second output of counter 22, which sets the pulse counter 22 and the trigger 15 to the zero (initial) state.

The signal “1 from the second output goes to the first input of the third element I 6 and allows the pulses to be output from the output of the element OR 4 to the input of the former 7. If the signals from the outputs of the registers 9 and block 11 of the memory do not match, the potential

With the level "O" at the output of the comparison unit 10, the trigger 15 is not transferred and the acknowledgment code combination is not generated or transmitted. The signal "O from the output of the element HE 13 after the appearance of the signal at the output of the counter 8 blocks the first element 5, the shaper 7 stops generating pulses that reset the counter 14 to the zero state, and after counting the specified number of pulses, it flips the counter 8 to the zero state by preparing the device to receive a new code combination.

The proposed device has a significant technical and economic effect, which consists in eliminating the possibility of the second counter being reset to the zero state by interfering signals or code combinations intended for other information receivers. This completely eliminates the possibility of disrupting the normal operation of the device and, therefore, increases the reliability of the reception and transmission of information.

Claims (1)

Invention Formula A device for receiving and transmitting information containing a receiver and a transmitter, the input and output of which are respectively connected to the communication channel, the input of the receiver through the selector zero is connected to the first input of the OR element and through the unit selector to the second input of the OR element and the information input of the shift register, outputs which is connected to the corresponding first inputs of the comparison unit, the second inputs of which are connected to the corresponding outputs of the memory unit, the output is connected to the first input of the first element five 0 five 0 five Ta And, the second input of which is connected to the input of the element NOT and is connected to the output of the first counter, the output of the first element And is connected to the trigger input, the output of the element is NOT connected to the first input of the second element And, the output of the clock pulse generator is connected to the input of the zero setting of the second counter, the clock input of the shift register is combined with the counting input of the first counter, the output of the second counter is connected to the input of the zero setting of the first counter, in the information block the output of the clock generator is connected to the first input And, the output of which is connected to the counting input of the counter, the first outputs of which are connected to the address inputs of the switch, whose inputs are the information inputs of the device, the output of the information block switch is connected to the first inputs of the zero code generator and the one of the code generator units, the second inputs of which are combined with the second input element And information block and connected to the forward output of the trigger, the third inputs are combined with the counting input of the second counter and connected to the output of the clock pulse generator pulses of the information block, the input of the zero setting of the trigger is connected to the second output and the input of the zero setting of the counter of the information block, characterized in that, in order to increase the functional reliability, the third element AND is entered into it, the output of the element OR is connected to the second input of the second element AND, the output which is connected to the first input of the third element I, the second input of which is connected to the inverse output of the trigger, the output to the input of the clock pulse generator, the output of which is connected to the counting input of the first counter.