SU1757108A1 - Device for tv-monitoring of intermediate stations of communacation system - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the monitoring time and reduce the load on the communication line. This goal is achieved due to the additional introduction of blocks, which, in the absence of a change in the states of monitored objects, ensure the transit of telecontrol information instead of receiving it. 1 il.

Description

The invention relates to telecommunications and can be used for telecontrol of communication lines with intermediate stations installed on it., D

The purpose of the invention is to reduce the monitoring time and reduce the load on the communication line.

The drawing shows a structural electrical circuit of the proposed device.

The device for telecontrol of the intermediate stations of the communication system contains at the transmitting station 1 a counter 2, a delay line 3, an address shaper 4, an address register 5, a gate signal shaper 6, the first And 7 element, a shift register 8, a sync signal register 9, a register 10 data, alarm signal detector 11, comparison block 12, stop signal register 13, clock generator 14, pulse driver 15, trigger 16, second element 17, NOT 18 element 18. at each intermediate station 19, counter 20, delay line 21, 22 gating driver its signal, address generator 23, address register 24, first element I 25, shift register 26, buffer register 27, receiving register 28, second generator 29 clock needle-pulses, second element 30, sync signal decoder 31, stop signal decoder 32 , the first trigger 33, the third element AND 34, the first pulse shaper 35, the first element OR 36, the first NOT element 37. the first 38 and the second 39 stop lamp registers, the stop signal shaper 40, the data register 41, the comparison circuit 42, the detector 43 alarm signals, the sync signal register 44, the first clock generator 45 output pulses, the second element is NOT 46, the fourth element is And 47, the second trigger 48, the third trigger 49, the second pulse shaper 50, the fifth element And 51, the second element OR 52, at receiving station 53 data register 54, receiving register 55, generator 56 clock pulses, trigger 57, clock decoder 58, clock decoder 59 stop signal.

The device contains at the transmitting station 1 serially connected generator 14, counter 2, line 3 delay. driver 6 strobe signal. the first element And 7 and the shift register 8, the second inputs of which through the address register 5 are connected to the address 4 adress (L

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Sa, the third input is with the counter 2 output. The fourth inputs are with the outputs of the sync signal register 9, the fifth inputs are with the outputs of the brake signal register 13, the sixth outputs are with data register 10 outputs and with the second inputs of the comparison circuit 12, the first inputs of which connected to the outputs of the detector 11 alarm signals and inputs of the data register 10, and the output to the second input of the second element 17, the first input of which is connected to the output of the element HE 18, and the output to the input of the record of the data register 10 and the setting input of the trigger 16, output which is connected to the launch input gene Ator 14 and the input of NOT circuit 18 and the reset input through pulse shaper 15 - yield shaper 6, wherein the output of the generator 14 is connected to the second input of the first element 7 1/1,

At each intermediate station, the output of the first clock generator 45 is connected to the inputs of the address register 24, the second input of the first element 25, the counter 20, the first input of the gate signal generator 22, the second input of which is connected via a delay line 21 to the counter 20 and the seventh input the shift register 26, the second input is also connected to the reset input of the first trigger 33, the third inputs - with the outputs of the address maker 23 and through the address register 24 with the second inputs of the shift register 26, the fourth input - with the third output And 34, and the output through the first And 25 element - with the clock input of the shift register 26, the third inputs of which are connected via the buffer register 27 to the outputs of the receiving register 28, the sixth inputs - to the outputs of the synchronization register 44, the fourth and fifth inputs - to the outputs the first 38 and second 39 registers of stop-signals, respectively, the first inputs with the outputs of the data register 41 and the second inputs of the comparison circuit 42, and the output with the second input of the second element OR 52, the output of which is connected to the channel input of the telecontrol, and the first input with the exit of that element TA 51, the second input of which is connected to the output of the second element HE 46, and the first input — to the output of the telecontrol channel — with the inputs of the receiving register 28, the decoders of the stop signal 32, and the sync signal 31, the output of which is connected to the installation input of the second element I 30, the output of which through the second generator 29 clock pulses connected to the input of the receiving register 28, and the first input with the first input of the third element And 34, the start input of the first generator 45 clock pulses, the output of the third trigger 49 and the input of the second element HE 46, out D which is connected to the first input of the fourth element AND 47, the second input of which is connected to the output of the comparison circuit 42, the first inputs of which are connected to the outputs of the alarm signal detector 43 and the inputs of the data register 41, the recording input of which is connected to the output of the fourth element OR 36, the output of which connected to the installation input

0 of the third trigger 49, and the second input - with the output of the first pulse shaper 35, whose input is connected via the third element AND 34 to the output of the first trigger 33, the installation input of which is connected to the reset input of the second trigger 48, the inverse output of which is connected to the third input of the fourth element 47, and the direct output is from the prohibition input of the second pulse generator 50, the output of which is connected to the reset input of the third trigger 49, and the input to the output of the gate signal generator 22, and the output of the third element 34 is connected the first element NO 37 with the first input of the first register 38 of the stop5 signal, the second input of the second register 39 of the stop signal and the second input of the buffer register 27, as well as the output of the third element 34 are connected to the second input of the first register 38, the first input of the second register 39, the third input of the buffer register 27 and with the input of the stop of the second generator 29 clock pulses. The outputs of the generator 40 of the stop signal is also connected to the inputs of the registers 38 and 39 of the stop signal,

5 At the receiving station 53, the output of the telecontrol channel is connected to the input of the receiving register 55 and the inputs of the decoders of the clock signal 58 and the stop signal 59, the output of which is connected to the reset input of the trigger 57

0 and the write entry of the register 54 data, the input of which is through the receiving register 55, the generator 56 and the trigger 57 is connected to the output of the decoder 58 clock signal.

The device works as follows,

In registers 9 and 44 the codes of synchronization signals are recorded, in registers 13, 38 and 39 - codes of stop signals, in registers 5 and 24 - the address code of the station formed (for example, manually dialed using switching elements of switches) by formers 4 and 23 . Registers 10, 41, and 54 record the information coming from the detectors 11 and 43 of the alarm signals.

5 The initial state will be considered the state of the stations when their status does not change, i.e. At the first and second inputs of blocks 12 and 42 of the comparison, the same signals are present, and at their outputs, as a result, a low potential.

The triggers 16, 33, 48, 49 and 57 are in the zero state, and therefore the generators 14 and 42 clock pulses are stopped. At the first inputs of the second 30 and third 34 elements And there are low potentials. A high potential is supplied to the second input of the fifth element AND 51 from the output of the second element NOT 46.

Information is transmitted from transmitting station 1 as follows.

When the state changes at the output of the detector 11 of the alarm signals, different codes will be present at the inputs of the comparison unit 12, which will lead to the appearance of a high potential at its output by this signal through the element 17, the first input of which has a high potential from the output of the element HE 18, trigger 16 will be set to one. At the same time, the same signal, coming through the element 17 at the input of the record of the data register 10, will record information from the outputs of the detector 11 of the alarm signals into the data register 10. At the same time, a high potential signal from the output of the trigger 16 will start the generator of 14 clock pulses. At the output of the comparison unit 12, the potential is low, since the codes at its inputs have become the same.

From the output of the generator 14, the clock pulses are fed to the input of the counter 2 with the recalculation factor of the Mz clock cycles

(m + k) N + I. where N is the total number of stations on the communication line;

n is the sync signal width;

m is the address width;

k is the data size;

I is the stop signal width.

With the arrival of the Mz clock cycles at the output of the counter 2, an impulse appears, which, entering the input of the shift register 8, permits recording of information from its information inputs. In this case, the recording is made into bits;

sync Do-Dn;

Dnni addresses - Da, where a mm;

state data Da + i - Dt, where b n + m + k;

Stop signal Oip - Dc, where c rnm + k + l.

After the time At required to record information in the shift register 8, a high potential pulse will be received from the output of the delay line 3 to enter the gate signal generator 6, allowing the formation of a high potential gate signal of length Ti. This duration is determined by the amount of information transmitted by the device in terminal station mode, and is

THn + (m + k) + I. From the output of the former 6, a pulse of length 5 T1 is fed to the first input of the first element I 7, thereby allowing the passage of clock pulses to the clock input of register 8, thus promoting digital information

0 signal to the input of the telecontrol channel.

After Mi clock cycles at the output of the imaging unit 6, a low potential appears and the reading of information stops. At the same time, with the drop from high

Level 5 to a low shaper of 8 poets, the falling edge will form a short pulse of high potential. This pulse, arriving at the reset input of trigger 16, will transfer it to the zero state, the generator

0 14 will stop. The device will return to its original state.

The devices also work in the same way from all intermediate stations provided there are no channels at their inputs, outputs

5 telecontrol digital information signal

In other cases, the devices operate at intermediate stations as follows.

0 Consider four cases.

1. At the intermediate station, its status did not change, but an information signal is received from the telecontrol station.

5 2. At the intermediate station, a change occurred, but the information signal from the channel output telecontrol began to arrive before the selection of 20 Moz clock counts by the counter. In this case, the brake light was also received before

0 counter selection 20 Moz cycles.

3. At the intermediate station, a change in state occurred, but the information signal from the channel output telecontrol began to arrive before the selection by the counter 20

5 Mz cycles. In this case, the stop signal was received after the selection of a counter of 20 Moz cycles.

4. The change in the state of the intermediate station occurred after the beginning of the arrival of the information signal from

0 channel output telecontrol. At the same time, the sync signal from the telecontrol channel has already been allocated.

 Consider the first case. Since there were no changes at the station, the low potential from the output of the third flip-flop 49 goes to the first inputs of the second 30 and third 34 AND elements. These signals prohibit the processing of the selected sync signal and stop signal. The information signal is received from the output of the telecontrol channel to the first input of the fifth element I 51. The second input of which receives a high potential from the output of the second element NOT 46, which allows information to pass to the second element OR 52 and further to the channel input of the telecontrol.

In the second case, the change at the intermediate station occurred, i.e. the high potential signal from the output of the comparison circuit 42, having passed through the elements AND 47 and OR 36 and having arrived at the installation input of the third trigger 49, will transfer it to a single state. The generator 45 begins to generate clock pulses. At the first inputs of the And 30 and 34 elements, a high potential is supplied, at the second input of the And 51 element, a low potential.

At the moment, a sync signal will be allocated from the telecontrol information channel that came from the output of the telecontrol, which, being fed to the setup input of the second trigger 48, will transfer it to a single state. The high potential signal coming from the direct output of flip-flop 49 to the prohibition input of shaper 50 will block the possibility of impulse generation, and the low potential coming from the inverse flip-flop output of 48 to the third input of the fourth element And 47 will be prevented from passing the output signal block 42 comparison. The selected clock signal, having passed through the second element I 30, arrives at the start input of the second generator 29 clock pulses, from the output of which clock pulses are fed to the clock input of the receiving shift register 28, which ensures the recording of the clock information entering the input of the clock signal

) (L-1).

where L is the number of the intermediate station that receives the information.

The signal highlighted by the decoder 32 of the stop signal flips the trigger 33 into one state, and the trigger 48 - into the zero state (for the second case, this happens until the counter has been allocated 20 Moz cycles. The signal from the trigger trigger 33, passed through the And 34 element, arrives to the input of the stop of the clock generator 29. By entering the input of the record of the buffer register 27, where an additional difcep can be installed, this signal allows the recording of information received at its second inputs from the outputs of the receiving register 28. This same signal is set The stop-signal register 38 transmits to the zero state and, having passed through the element NOT 37, prohibits the recording of information in it, and entering

The first input of the register 39 of the stop signal allows recording of information from the driver 40 of the stop signal into it.

The signal from the output of the third element And 34

also arrives at the input of the pulse shaper 35, which generates a high potential impulse on the leading edge of the incoming signal at its input.

having passed through the first element OR 36, goes to the installation input of the third trigger 49. But since the trigger 49 is already set to one state by the signal of the comparison unit 42, the changes by

it will not happen.

From the output of the third element, And 34 will also arrive at the fourth input of the driver 22 a strobe signal, which ensures that it will form, after receiving a pulse, from a pulse delay line 21 of duration T2

(rrH k) L + I t M2 t, where I is the station number (determined by the station address),

After the counting by the counter of the clock clock at its output, a signal is received that, when it enters the input of the record of the shift register 26, provides for recording information from its information inputs into it. With this record

produced in bits: the sync signal Do is the addresses D k + 1 - Da, where the data of the state is D3 + 1-Ob, where b m + n + k;

addresses and data from previous stations Ою + 1 - Dd, where (m + k) L;

stop signal Dd + rDg, where g n + (m + k) L + l. After the time At required to record information in the shift register 26, a high potential pulse will be sent from the output of the delay line 21 to the third input of the gate signal generator 22, allowing the formation of a gate signal of duration T2. Will start

transmission of information through the element OR 52 to the channel telecontrol.

Through M2 clocks at the output of the gate signal generator 22, the low potential and transmission will cease.

At the moment of transition at the output of the signal former 22 from a high level to a low one, a short pulse will be generated on the trailing edge, since a low pulse is present at its input

potential. This pulse, arriving at the reset input of the third trigger 49, sets the device to its initial state.

In the third case, the stop signal from the received information signal is allocated after the counter has counted 20 Moz clock cycles.

and writing information to shift register 26. In this case, the transfer of information about the state of the intermediate station occurs as in the first case. However, it was taken into account that a high potential (the trigger 48 is set to one state by a dedicated clock signal) enters the prohibition input of the second pulse generator 50 for a direct output of the second trigger 48, after the formation of the resolution enable signal at the output of the generator 50 does not receive a high pulse potential, and the system is not reset. The counter 20 continues to count pulses, which will ensure the operation of the device according to the algorithm described in the second case.

Consider the fourth case. If at the moment of passing the information signal from the output of the telecontrol channel to its input through the fifth element AND 51 and the second element OR 52, a change in the state of the intermediate station occurred, then a high potential signal is set at the output of the comparison block 42 But since the third input of the fourth element AND 47 the low potential comes from the inverse output of the second trigger 48, which is set to one state by the selected clock signal, then the third trigger 49 will not be transferred to the single state and the device on the intermediate station tion will remain in the original state

After the information signal passes from the output to the channel input, the stop signal to the decoder 32 will be allocated to the telecontrol. This signal will set the second trigger 48 to the zero state, a high potential will appear at the third input of the fourth element AND 47, and the signal from the output of the comparison unit 42 will will go through the elements AND 47 and OR 36 to the installation input of the third flip-flop 49 The flip-flop 49 is set to one state, and the whole device will start working as in the first case. At the end of the transfer, the device will be reset.

At the receiving station 53, the information signal is received as follows.

When a sync signal is received by the sync signal decoder 58, a signal is generated that sets the trigger 57 into one state. The high potential signal from the output of the trigger 57 starts the generator 56, the clock pulses from the output of which provide reception of the signal from the output of the telecontrol channel and its recording in the receiving register 55, After receiving the stop signal by the decoder 59, the generator 56

stops, and the data from receive register 55 is written to data register 54.

From the output of data information register 54, 5i can be fed to a display device or a device for further processing of information.

The proposed device has significant technical advantages in comparison with the known.

When the device operates on digital channels at a speed of 1200 baud and there are 10-15 intermediate stations in the communication system with a failure rate of A 3-5 / h

5, the speed of the device, as the calculations show, is increased compared with the known 5-6 times. In the event that only one station has failed, the time to bring the information about the accident is reduced by P times, where P is the number of stations from the receiving terminal to the one at which the accident occurred.

Claims (1)

Claims of the Invention Device for telecontrol of intermediate stations of a communication system, comprising in series at a transmitting station a clock generator, a counter, a delay line, a gate signal generator, an element And 0 shift register, serially connected address generator and address register whose output is connected to the second input of the shift register, the third input of which is connected to the output of the counter, whose input 5 is connected to the second input of the AND element, the sync signal register and the stop signal register, the outputs of which are connected respectively to the fourth and fifth inputs of the shift register, the output of which is 0 the communication line input, and the serially connected alarm detector and data register, output which is connected to the sixth input of the shift register, at each intermediate 5 stations - serially connected alarm signal detector, data register and shift register, serially connected first clock generator, counter, delay line, 0 the driver of the strobe signal and the first element And, the output of which is connected to the clock input of the shift register, serially connected address driver and address register, 5 whose output is connected to the second input of the shift register, the successively connected shift register and the buffer register, the output of which is connected to the third input of the shift register, the brake signal decoder and the clock decoder, the inputs of which are connected to the input of the receiving shift register, which is the output of the line shift Zi, the second clock, the output of which is connected to the clock input of the receiving shift register, the trigger, the first and second inputs of which are connected respectively to the output of the decoder stop-c and the output of the delay line connected in series the first element NOT and the first register of the stop signal, the output of which is connected to the fourth input of the shift register, the fifth input of which is connected to the output of the second register of the stop signal, the first input of which is connected to the input of the zero setting of the first the register of the stop signal, the second input of which is connected to the output of the brake light generator and the second input of the second register of the stop signal, the input of the zero setting of which is connected to the input of the installation of the zero of the buffer register and with the output p The primary element is NOT, the input of which is connected to the input of setting zero of the first register of the stop signal, with the second input of the buffer register, with the installation input of the second clock generator and the second input of the strobe signal generator, the third and clock inputs of which are connected respectively to the output of the address generator and the input counter, combined with the input of the record of the register of the address, and the register of the synchronization signal, the output of which is connected to the sixth input of the shift register, the seventh input of which is connected to the output of the counter, and receiving station - stop signal decoder and serially connected clock decoder, trigger, clock generator, receiving shift register and data register, the second input of which is connected to the second trigger input and the output of the brake signal decoder, the input of which is connected to the input of the clock signal decoder and The signal input of the receiving shift register, which is the output of the communication link, characterized in that, in order to reduce the monitoring time and reduce the load on the communication link, the output of the transmitting station is gate signal rotator through connected serially connected pulse generator, trigger, element NOT, the input of which is connected to the trigger input of the clock generator, and the second element AND is connected to the recording input data register, the output of which is through the entered comparison unit, the second input of which is connected to the output of the alarm signal detector, is connected to the second input of the second element I, the output of which is connected to the trigger installation input, and the second, third, fourth section is entered at each intermediate station and the fifth elements AND, the first and second elements OR, the first and second pulse formers, the second element NOT and the second and third triggers, and the output of the gate signal generator through successively connected second th pulse shaper, third trigger, the second element HE, the input of which is connected to the input of the first clock generator, and the fourth element I is connected to the input of the data register, the output of which through the comparison unit, the second input which is connected to the output of the alarm signal detector, is connected to the second input of the fourth element I, the output of which through the first element OR is connected to the input of the installation of the third trigger, the output of which is connected to the start input of the second clock generator through the second element I, the second input of which is connected to the output sync signal decoder and with the setup input of the second trigger, the input reset and direct and inverse outputs of which are connected respectively to the output of the brake signal decoder, the prohibition input of the second pulse driver and the third input of the fourth element And, the trigger output is connected to the input of the element NOT through the third element And, the second input and output of which are connected respectively to the output the third trigger and the input of the first pulse generator, the output of which connected to the second input of the first element OR, and the output of the shift register is connected to the input of the communication line through the second element OR, the second input of which is connected to the output of the fifth element AND, the first and second the inputs of which are connected respectively to the input of the clock decoder and the output of the second element NOT. 53 I I 23 P HIOTELb 3: UJ - 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