SU1406803A1 - Multichannel device for interfacing subscribers to common trunk line - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase throughput. The device contains data buses 1, a switch block (PSU) 2, a key block 3, a decoder 4 addresses, a buffer memory block (FBS) 5 and 8, a comparison node 6, a shift register block 7, a control unit (CU) 9 and delay delay 10. When the BP 2 contacts are set to the message transfer position, this message consisting of the subscriber's address code, subscriber's address code in the group and the data code is sent to the corresponding buses 1. The receiving device records in the The BBP 8 code of the sender’s address and the data code of the selected address code of the recipient in the group, and received information is output. When simultaneously sending messages from several devices to one of the buses, a collision and distortion of these messages occur. Then the CU 9 generates a signal and retransmits the messages until the message has been successfully transmitted. The goal is achieved by the introduction of BP 2, decoder 4, BBP 5 and 8, and BU 9. Data or execution of BBP 5 and 8 and BU 9. 4 Il. / / / W / / / /. (L O) 00 oo

Description

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The invention relates to a communication technique, in particular to a technique for transmitting information on a common data highway.

The purpose of the invention is to increase the capacity of the device.

FIG. 1 is a block diagram of a multi-channel device for connecting subscribers to a common trunk in FIG. 2 is a diagram of the first block of buffer memory; FIG. 3 is a control block diagram; FIG. 4 shows a diagram of a second block of buffer memory. The device comprises data buses 1 15 a block of 2 switches, a block of 3 keys, an address decoder 4, a first block of buffer memory 5, a comparison node 6, a shift register block 7, a second block of buffer 8 memory, control unit 9, delay element 10 and control bus 11.

The first bag 5 of the buffer memory (FIG. 2) forms the address register 12, the input registers 13-1 are 13-p, the elements 14-1 are 14-n and the triggers 15-1 are 15-p.

The control unit 9 (FIG. 3) includes the first element OR 16, the decoder 17, the counter 18 and the element OR 19.

The second block 8 of the buffer memory contains the subscriber decoder 20 and the registers 21-1 - 21-n subscriber.

The first block 5 of the buffer memory (Fig. 2 and 3) is used for permanent storage in the register 12 of the sender's address (serial number of device A), as well as for recording and storing in the input registers 13 until the successful transmission of the B code of the address of the subscriber group , code C of the address of the subscriber in the group (the serial number of the register of the subscriber 21, figure 4) and data code D Writing codes B, C, D into the input registers 13 is carried out by an external device in the presence of enabling signals (O) at the outputs of the corresponding flip-flops 15. The input registers 13 have three states at the output. When the device operates, their outputs are in the third off state and are connected only by signals from control unit 9.

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Responsibly the control unit 9, the decoder 4 (via the switch unit 2) and the unit 7.

The device works as follows.

When the device is turned on, the information in the input registers 13 of the first block 5 is absent, at the outputs of the flip-flops 15 there are zero signals prohibiting the operation of the control block 9 and allowing the external device 1 to write information to the input registers 13. The contacts of the switch block 2 are in the position of message centering. The external device, in the presence of data for transmission, writes these dorny D, the address B of the subscriber group and the address C of the subscriber in the group to one of the input registers 13 and, by sending a signal to the installation input of the corresponding trigger 15, sets at its output a single signal permitting the operation of the control unit 9 and prohibiting an external device to record information at this address. Similarly, the external device records information in the remaining input registers 13.

Single signals from the outputs of the flip-flops 15 are fed to the inputs of the decoder 17 and through the second element OR 19 enable the operation of the counter 18, which counts the number of TI pulses (arriving at its input. The decoder 17 decrypts the state code of the trigger 15, and generates a single signal, which The 1st input of the corresponding input register 13 goes to the control, connecting its outputs to the corresponding inputs of the switch block 2. Through the first element OR 16, the select signal sets the contacts of the block 2 to the position, message transmission and input em on the address decoder 4. The address decoder 4 at the address B of the subscriber group generates a signal at one of its outputs, allowing the operation of the corresponding elements of the key block 3. The message consisting of the address code A, the subscriber code C of the address of the subscriber in the group and the code D of data arrives at

Synchronization of work carried out- corresponding. Tires 1

c from a common chronizer (not shown), which generates three sequences of clock pulses, arriving at the control inputs of the corresponding sonde, a message.

The receiving device impulse TII enters h

matching. tires 1

data receiving

proper device message.

In the receiving device, the clock pulse TI enters through block 2

3

switches to the control input of the 4 address decoder, which, according to the sender's address code A, retransmits the message via the corresponding keys of the 3 key block, data bus 1 to the inputs of the 2 switch block and the 7 shift register of the transmitting device. When the clock pulse THj arrives at the control inputs of the blocks 7, the message is recorded in them both at the transmitter and at the receiver. Comparison node 6 of the transmitting device compares the codes of messages arriving at its inputs from the outputs of the first block 5 and block 7, and when they coincide, and also in the presence of a control signal from the output of the delay element 10, forms at its output a signal which through the corresponding element AND 14, sets the input register 13 and the trigger 15 to the zero state.

The same signal goes through the block -2 of switches, the block 3 of keys to the corresponding control bar 11 and to the control input of the receiver's subscriber 20, allowing the recording of the sender's address code and data code D from the shift register unit 7 to the corresponding subscriber's register 21 selected by code C address of the recipient in the group

The information received in the subscriber registers 21 arrives at the outputs of the receiving device.

. In the case of simultaneous transmission of data from several devices to one of the buses 1, a collision and distortion of these messages occur, and no signal appears at the output of the comparison node 6. The control unit 9 through a random number of cycles (discrete time intervals) again generates a single signal on the same decoding code 17, re-transmitting the message 68034

NII until this message is successfully transmitted.

Claims (1)

Claims Multichannel device for interfacing subscribers with a common magistr, ralley, containing a key block whose outputs are connected to corresponding B1, thin data buses and control buses, a block of shift registers whose outputs are connected to the first comparison nodes, a delay element different with that 5 to increase the capacity of the device, entered into it the first and second blocks of the buffer memory, the control unit, the address decoder and the switch unit, the first and Q the second outputs of which are connected to the first inputs of the key block, the second inputs of which are connected to the outputs of the address decoder, the first and second inputs of which are connected respectively to the third and fourth outputs of the switch block, the first and second inputs of which are connected to. the first outputs of the first block of the buffer memory and the second inputs of the node Comparison Q, the output of which is connected to the third input of the switch block and the first input of the first block of the buffer memory, the second inputs of which are connected to the first outputs of the control unit, the second output of which is connected to the third input of the comparison node via the delay element switch block - directly, the fifth and sixth inputs of which five 0 connected to the corresponding tires data and inputs of the shift register block whose outputs are connected to the first inputs of the second buffer memory block, the second input of which is connected to the corresponding control bus, and the outputs of the first buffer memory block are connected to the inputs of the control block. Phie.g FI.5 H fae.