SU1314361A1 - Device for transmission and reception in circular communication channel - Google Patents

Abstract

The invention relates to devices used in computing and data transmission systems, in particular, to devices that provide data transmission and reception in a circular communication channel of computer networks. The purpose of the invention is to increase the information capacity of the ring channel. In normal operation, the device provides either transmission of information over the communication channel using receiver 1, switch 18 and transmitter 24, or transmission of information recorded in shift register 34. In collision blocking mode, the device listens to the channel using element 5. When two frames of information collide, element 5 also gives a signal to the output of the device and stops the clock generator. The counter 42 records the number of collisions. The decoder 43 determines the path of the signal through the delay elements 44, 45, 46. The device provides for the elimination of collisions of frames of the transmitted information, which allows reducing the pause between receiving and transmitting information. 1 il. (L oo 4 CO o

Description

The invention relates to devices used in the field of computing technology and data non-transmission systems and, in particular, to devices providing data transmission in a ring channel of computer networks.

The purpose of the invention is to increase the information capacity of the ring communication channel.

The drawing shows a block diagram of the proposed device.

no signal inputs. Register 3 records information received in a sequential code from its input, and from the first-fourth group of outputs, it outputs to the inputs of decipherors 7-10 the contents of the information frame positions allocated in it for the opening flag, for the source address and for the closing flag, respectively. The decipheror 7 determines in a combination of pulses arriving at its inputs.

The device contains a receiver 1, an element the presence of a frame opening flag and a delay 2, a register 3 of memory, a trigger 4, element 5, element b of delay, decoders 7-10, element 11 and 11, element 12, elements 13, 14, elements OR 15-17, switch 18, element OR - NOT 19, element OR 20, element OR 21, element OR 22 and 23, transmitter 24, clock 25, trigger 26, element NOT 27, element AND 28, elements OR 29 -31, triggers 32 and 33, shift register 34, trigger

A signal to the output only if this combination of pulses unambiguously corresponds to it. Decoders 8 and 9 are determined in a combination of pulses, 12 arriving at their inputs, the presence of the address of the subscriber connected to this device, and output signals to the output only if this combination of pulses uniquely corresponds to the address of this subscriber. Descrambler 10

35, AND elements 36, 37, generator 38 also determines in combination pulses, post-duty pulses, counter 39, element OR 40, element OR 41, counter 42, decipher 43, delay elements 44-46.

The device operates in two modes: normal operation and blocking the collision of signals.

In normal operation, the device is an OS.1.1. It transmits information via a communication channel or transfers it from the subscriber connected to it. When transmitting information via a communication channel, it performs the following functions:

a) from the communication channel of a part of the frame of information that enters it as a result of a collision of signals in the information transceiver prior to this;

b) receiving from a communication channel a frame of information intended for a subscriber connected to this device and transmitting it to the channel;

c) reception from the communication channel and transmission

the presence of a close-niero frame flag and outputs an output signal only in the case e: and this combination of pulses is unambiguous:; - it corresponds to it. At this time, the delay element t after the signal delay for the time required to write the full frame of information to the register 3 and the operation of the decipherors 7-10, gives a signal to the input of the And 11 element.

In the case of the receipt from the communication channel of a part of information from the outputs of the detectors 7, 10 to the third and second inputs of the element 11, respectively, single signals or nothing; they do not arrive or only go to one of them. The signal from output 35 of the element OR 15 resets the trigger 4 to the "zero state. From the output of the element OR 16, this signal enters the third input of register 3 and erases the information in it. From the output of the element OR 17, this signal is fed to the input of the switch 18,

it contains a frame of information issued by someone who switches his first input to

Bykom subscriber of the system to any other, but not connected to this device;

d) from the channel of communication of the frame it is in a neutral position, i.e. it breaks the ring channel of communication. At this time, the element 2 after the delay of information received at its input from the output of the receiver, previously issued by the subscriber, has to be 1 for the time required for the analysis

They are connected to the Da1P1Ohm device, addressed to any of the other subscribers, and ending the passage through the entire ring communication channel.

Normal mode of operation. Transmission of information over the communication channel.

Receiver 1 receives information from the communication channel and sends it to the input of delay element 2, inputs of register 3, trigger 4, and input of element 5. The signal with a high level of logical unit establishes this information, outputs it to the first input of switch 18, and it is removed from the communication channel.

In the event that a frame of information destined to the subscriber connected to this device arrives from the communication channel, from the outputs of the decoders 7 and 10, the signals arrive at input 11 of the element 11, and from the output of decider 8, to the input of the connector 14. 11 gives a signal to the scrap of elements And 13, 14 and

triggers trigger 4 to “single state - 55 input of element NOT 12. Last to output

and it outputs a signal to the input of delay element 6. Element I 5 on the way out does not give out anything. as ei o ozgalr;

no signal inputs. Register 3 records information received in a sequential code from its input, and from the first-fourth group of outputs, it outputs to the inputs of decipherors 7-10 the contents of the information frame positions allocated in it for the opening flag, for the source address and for the closing flag, respectively. The decipheror 7 determines in a combination of pulses arriving at its inputs.

the presence of the opening frame flag and outputs a signal to the output only if this combination of pulses uniquely corresponds to it. Decoders 8 and 9 are determined in a combination of pulses arriving at their inputs, the presence of the address of the subscriber connected to this device, and output signals at the output only if the given combination of pulses uniquely corresponds to the address of this subscriber. Descrambler 10

about

the presence of a close-niero frame flag and outputs an output signal only in the case e: and this combination of pulses is unambiguous:; - it corresponds to it. At this time, the delay element t after the signal delay for the time required to write the full frame of information to the register 3 and the operation of the decipherors 7-10, gives a signal to the input of the And 11 element.

In the case of the receipt from the communication channel of a part of information from the outputs of the detectors 7, 10 to the third and second inputs of the element 11, respectively, single signals or nothing; they do not arrive or only go to one of them. The signal from the output 5 of the element OR 15 reset the trigger 4 to the "zero state. From the output of the element OR 16, this signal enters the third input of register 3 and erases the information in it. From the output of the element OR 17, this signal is fed to the input of the switch 18,

0 which switches its first input to

“The neutral position, i.e., the ring link is broken. At this time, element 2, after delaying the information arriving at its input from the receiver of this information, outputs it to the first input of the switch 18, and it is removed from the communication channel.

In the event that a frame of information destined to a user connected to this device arrives from the communication channel, from the outputs of the decoders 7 and 10, the signals arrive at input 11 of the element 11, and from the output of decider 8, to the input of the connector 14. 11 gives a signal to the scrap of elements And 13, 14 and

gives nothing, and from AND 13, 14 elements only AND 14 output the signal. This signal goes to the inputs of the OR elements OR 20-23, the input of the OR element is NOT 19 and the input of the OR element is 15. From the output of the OR 15 element, it enters to the trigger input 4 and sets it to the "zero state. Element OR NOT 19 on the output does not give anything. From the output of the element OR 20, this signal is fed to the input of the switch 18, and it switches its input to the output, i.e. it closes the ring communication channel. At this time, element 2, after delaying the frame of information, sends it in serial code through switch 18 to the input of transmitter 24, which, in turn, provides it to the communication channel. From the output of the element OR 15. From the output of the element OR 15, it enters the input of trigger 4 and sets it to the "zero state. From the output of the element OR 16, this signal goes to the input of register 3 and erases the information in it. The elements OR 20, 22, 23, the element 2 delay, the switch 18, the transmitter 24, the clock 25 and the element NOT 27 work in this case in the same way as discussed above.

In the event that a frame of information previously issued by a subscriber connected to this device is sent to the address of any of the other subscribers and has completed its passage through the whole channel,

That OR 21 the specified signal arrives at the 15th target communication channel, the signals arrive at the input of register 3, and it outputs to the parallel outputs of the decoders 7, 10, respectively

AND

the main code for all of its outputs on the first outputs of the device information recorded in it earlier. At the subscriber, this frame of information is compared with the last one transmitted to the ring channel and, if the result of the comparison is negative, it is perceived as a frame of information intended for it. Otherwise, it is destroyed together with the inputs of the element 11 and from the output of the decoder 9 to the input of the element 13. The element 11 outputs a signal to the inputs of the elements 13 and 14 and the input of the element 12.20 Nz elements 13 and 14 You only get the element And 13. This signal goes to the inputs of the elements OR 17, 21, the input of the element OR 15 and the input of the element OR NOT 19. From the output of the element OR 21

the last, given by the subscriber to the channel sv - 25, the specified signal is fed to the input of the cut. From the output of the element OR 22, this signal is fed to the input of the chroniser 25, which starts counting the time necessary and sufficient for issuing a frame of information from the delay element 2 through

gistra 3, and it issues in parallel code on all its outputs to the outputs of the device information recorded in it earlier. The elements OR 15, 17, element 2 delay, trigger 4, switch 18, element

the switch 18 using the transmitter 24. 30 OR - NOT 19 operates in the same way as in the case of the output element OR 23, this signal is received from the communication channel of a part of the input frame to the input of the trigger 26 and the setting.

casts him in a “single state. C out-Normal operation mode. Non-output of the Indus Trigger 26 signal arrives at the input from the subscriber connected to the NOT 27 Element, and it removes the high level of the signal from the input of the element 28, 35 thereby prohibiting the signal from the first input of the device to pass through it, i.e. transmitting a frame of information to the release of information from this subscriber connected to it. Chronically device.

The torus 25, after counting the indicated time, outputs to the trigger 26 a signal, which sets it to the "zero state" and removes a high signal level from the HE element 27, which, in turn.

40

When a subscriber receives information intended for transmission to another subscriber of the system, he issues a signal at the device input to the second input of the And 28 element. If the device is not occupied by the transmission of information over a communication channel, then a high level of the signal was applied to the input of the And 28 element, so it issues a signal to the first inputs of the OR elements 29-31. With the release of the element OR 29 this

sets a high signal level to, with the signal arriving at the inputs of the flip-flops 32,

the input element And 28, thereby allowing the passage of the signal from the first input of the device.

In the event that a frame of information sent by any subscriber to any other but not connected to this device arrives from the communication channel, the signals are received only from the outputs of decoders 7, 10, respectively, to the inputs of AND 11. The latter outputs the signal to the inputs of AND 13 elements , 14 and the input element is NOT 12. As a result, the element OR-NOT 19, to which the outputs of these elements are connected, outputs a signal to the inputs of the elements OR 16, 20, 22 and 23 and the input ele33 and the input of the register 34, and from the output of the element OR 31 - to the trigger input 35. Triggers 32, 33, 35 upon receipt This signal goes to the "single state," and the register 34 records the information frame filed from the terminal in parallel code through the second inputs of the device. The signal from the output of the trigger 35 is fed to the input element And 36, and from the output of the trigger 32 - to the inputs of the elements And 5, 36 and the input of the switch 18. The latter switches its input to

55 output, and the elements And 5, 36 on the output do not give anything, since there are no signals on their other inputs. The signal from the output of the trigger 33 is fed to the input element And 37.

or 15. From the output of the OR 15 element, it enters the input of trigger 4 and sets it to the “zero state. From the output of the element OR 16, this signal enters the input of register 3 and erases the information in it. The elements OR 20, 22, 23, the element 2 delay, the switch 18, the transmitter 24, the clock 25 and the element NOT 27 work in this case in the same way as discussed above.

In the event that a frame of information, previously issued by a subscriber connected to this device, is sent to the address of any of the other subscribers and has completed its passage through the entire ring

AND

to the inputs of the element 11 and from the output of the decoder 9 to the input of the element 13. And the element 11 gives a signal to the inputs of the elements 13, 14 and the input of the element NOT 12. 0 Nz elements And 13, 14 a signal to the output gives only the element AND 13. This signal goes to the inputs of the elements OR 17, 21, the input of the element OR 15 and the input of the element OR NOT 19. From the output of the element OR 21

to the device.

When a subscriber receives information intended for transmission to another subscriber of the system, he issues a signal at the device input to the second input of the And 28 element. If the device is not occupied by the transmission of information over a communication channel, then a high level of the signal was applied to the input of the And 28 element, so it issues a signal to the first inputs of the OR elements 29-31. With the release of the element OR 29 this

the signal arrives at the inputs of the trigger 32,

33 and the input of register 34, and from the output of the OR element 31 - to the input of the trigger 35. Triggers 32, 33, 35, upon receipt of this signal, go to the “single state, and register 34 records the received from the subscriber in the parallel code through the second inputs of the device frame information. The signal from the output of the trigger 35 is fed to the input element And 36, and from the output of the trigger 32 - to the inputs of the elements And 5, 36 and the input of the switch 18. The latter switches its input to

output, and elements 5, 36 do not give anything to the output, since there are no signals at their other inputs. The signal from the output of the trigger 33 is fed to the input element And 37.

At this time, the signal from the output of the element OR 30 is fed to the input of the heater 38 clock pulses, and it begins to issue clock pulses to the inputs of the AND 5, 37 elements, the input of the register 34 and the input of the AND 36 element. The And 5 element does not output anything, so as to its input from the output of receiver 1, signals are not received, and the element 37, with the arrival of each clock pulse, outputs signals 39 to the input of the counter and the latter starts counting the clock pulses. The register 34 sequentially (one after the other) outputs from its output to the input element AND 36 the content of the positions of the frame of information with the arrival at its input of each clock pulse. Element And 36 provides the content of these positions to the input of switch 18, from the output of which they are fed to the input of transmitter 24 and further to the ring channel. The counter 29, after counting the number of clock pulses necessary to issue a full frame of information from the register 34, outputs a signal to the output of the device, the inputs of the elements OR 40, 41, and is reset to its original state. From the output of the element OR 40, this signal is fed to the input of the generator 38 clock pulses and stops its operation, and from the output of the element OR 41 to the input of the trigger 32 and sets it to the "zero state. The signal, issued on the second output of the device, informs the subscriber about the end of the transmission of the information frame from it.

SigPal collision blocking mode.

In the process of transmitting information from the subscriber connected to it, the device with the help of the element And 5 listens to the channel. At the appearance of at least one signal with a high level of a logical unit at the input, and consequently, at the output of receiver 1, indicating the transmission of information as a sequence of frames, conducted by a neighboring or other network subscriber, this signal is fed to the input of the And 5 element. the inputs of the element And 5 filed a signal with a high level and receives clock pulses from the generator 38 clock pulses, indicating the transfer of information from the subscriber connected to this device. If these events occur simultaneously, then there is a collision in the device of two information frames, and element 5 outputs a signal to the inputs of counter 39, trigger 33, inputs of trigger 35, elements OR 40, 41, register 34, input of counter 42, and device output . The counter 39, upon receipt of this signal, is reset to the initial state and does not give a signal to the output. The triggers 33 and 35 switch to the "zero state" and remove the high potential from their outputs, and hence from the inputs of the And 37 and 36 elements, respectively. Ele

the cops OR 40, 41 give it to the input of the generator 38 clock pulses and the input of the trigger 32, respectively. The clock generator 38 stops the output of pulses to the output, and the trigger 32 is set to the “zero state” and removes a high potential from the input of the element 5. When the signal arrives, this register 34 erases the information. The same signal, arriving at the output of the device to the subscriber connected to it, requires re-preparation for issuing a frame of information previously transmitted from it. The subscriber prepares it and issues it in parallel code using the second inputs of the device.

The counter 42 when the signal from the output of the element And 5 captures the number of collisions and it to the input of the decoder 43. In accordance with the contents of the counter 42, the decoder 43 selects one or another path in the group of elements 44, 45,

46 delays. For example, in the first collision (the position of the counter 001), the first delay is selected (1T), in the second - the second (2T), and in the third - the third (3T). At the same time, the delay time of the signal in the first delay is chosen so as to ensure that the device outputs information arriving at its input from the output of the communication channel, since at that time the device operates as previously discussed (the normal operation mode when transmitting information over the communication channel ).

After a delay in the group of delay elements 44-46, this signal arrives at the inputs of the elements OR 29-31, and the device continues to work as discussed above (normal mode of operation when transmitting information from the subscriber connected to this device).

The technical and economic effect from the application of the proposed device is that, compared to the known ones, it allows to significantly increase the payload of the ring communication channel, because, first, it provides for the removal of a part of the information frame from the communication channel. which got into it as a result of collision of signals in the same device preceding it; secondly, in case of collision of signals, it carries out the further transmission of information coming from the communication channel; thirdly, in any case, it ensures that the information frame is removed from the communication channel after this frame passes the ring communication channel only once. These factors significantly reduce the likelihood of information colliding in a ring link.

Claims (1)

Invention Formula An apparatus for transmitting in an annular communication channel comprising a receiver. the output of which is connected to the first input of the first element I, the switch, the output of which is connected to the transmitter input, the memory register, the output of the first trigger connected to the first input of the second element I, the output of the second trigger connected to the second input of the first element I and the first input of the third element I , the output of the first element And is connected to the first inputs of the first and third triggers, the output of the third trigger is connected to the second input of the third element And, the third input of which is connected to the output of the shift register, the output of the first counter with connected to the input of the decoder, the first output of which is connected to the input of the first delay element; the second and third outputs are connected to the first input of the second and third delay elements, respectively; the outputs of the first and second delay elements, respectively, with the second inputs of the second and third delay elements, that, in order to increase the information capacity of the ring channel, a second counter, fourth and fifth delay elements, a clock, a clock generator, a second, third, four Fifth and Fifth decoders, the element OR NOT. the first and second elements are NOT, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth elements OR, the fourth, fifth, sixth and seventh elements And, the fourth and fifth triggers, the receiver output is connected to the first inputs of the fourth trigger and memory register and through the fourth delay element is connected to the first input of the switch, the second input of the fourth trigger is connected to the output of the first OR element, the first input of which is connected to the first inputs of the second and third OR elements and elements nta ORI- NOT and is connected to the output of the first element NOT, the output of the fourth element AND is connected to the second inputs of the power unit OR- NOT, the first and third elements OR, and the first input of the fourth element OR, the second input of which is connected to the third inputs of the first element OR and the element OR - NOT and the first inputs of the fifth, sixth and seventh elements OR are connected to the output of the fifth element AND, the output of the OR element is NOT connected to the second inputs of the second, fifth, sixth and seventh elements OR and the fourth input of the first element OR, the outputs of the second and the fourth element OR are connected respectively with the second and third inputs Compiled by V. Buti and Editor A. L akowska Tehred I. VeresKorrektor N. Korol Order 2007/50 Circulation 544 subscription VNIIPI USSR State Committee for Inventions and Discoveries 1 13035, Moscow. G-35. Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Design. four 0 five 0 five 0 five 0 five 0 the memory register, the outputs of which are connected to the corresponding inputs of the respective second, third, fourth and fifth decoders and are the first outputs of the device; the outputs of the second, third and fourth decoders are connected respectively to the first inputs of the sixth, fifth and fourth elements AND This decoder is connected to the second input of the HjecToro element I, the output of the fourth trigger through the fifth delay element is connected to the third input of the niecToro element AND, the output of which is connected to the input of the first element NOT and the second inputs of the fourth and fifth elements AND, the outputs of the third and fifth elements OR, the third element AND and the second trigger are connected respectively to the second, third, fourth and fifth inputs of the switch, the output of the sixth element OR is connected to the input of the clock, the output of which is connected to the first input of the fifth trigger, the second input of which is connected to the output of the seventh element OR, the output through the second element is NOT connected to the first input of the seventh element AND, the second input of which is the first input of the device, the output of the seventh element AND connected to the first inputs of the eighth, ninth and tenth elements OR, the second inputs of which are combined and connected to the output of the third delay element, the output of the eighth element OR is connected to the first inputs of the shift register, the second trigger and the second input the OR element is connected to the second input of the third trigger, the outputs of the tenth and eleventh OR elements are connected to the corresponding inputs of the clock generator, the output of which is connected to the second inputs of the shift register and the fourth element and the third input of the first element AND, the output of the first element AND is connected to the third input of the shift register, the first inputs of the eleventh element OR, the second counter and the twelfth element OR, the input of the first counter and is the second output device, the second input of the second counter is connected to the output of the second element AND, the output of the second counter is connected to the second inputs of the eleventh and twelfth OR elements and is the third output of the device, the information inputs of the Stra shear are the second inputs of the device, the output of the twelfth OR gate coupled to a second input of the second flip-flop.