RU1774363C - Device for data reception and transmission in ring communication channel - Google Patents

Abstract

The invention relates to computer technology and data transmission systems, in particular to devices for receiving and transmitting information in a ring communication channel of computer networks. The aim of the invention is to increase the reliability of information transfer and expand the scope by organizing priority polling and increasing reliability. Based on the results of the comparison, the priority of transmission is established, which allows you to monitor and receive from the subscriber a response message containing information about the correct reception. The device contains a receiver, four registers, a delay element, a switch, a transmitter, eight decoders, six triggers, two counters, 13 AND elements, a clock generator, a comparator, four OR elements, three NOT elements. 1 ill.

Description

The invention relates to computer technology and data transmission systems, in particular to devices for receiving and transmitting information in a ring communication channel of computer networks.

A device is known comprising a receiver, a transmitter channel switch, first and third AND elements, first and third triggers, a pulse distributor, a parallel to serial converter, an information storage device, a group of delay elements, a counter, a collision decryptor, and an information source. The disadvantages of the device are that it does not exclude the possibility of a part of the frame damaged after a collision getting into the communication channel, the information frame is not removed from the communication channel after passing this frame along the ring only once, there is no possibility of multicast addressing and operational polling of interaction participants .

A device containing a receiver is also known, the first is the fifth delay elements, the register, the first is the fifth triggers, the first is the seventh AND element, the first is the fifth decoders, two NOT elements, the first tenth OR elements, switch, OR element NOT, transmitter, clock, shift register, clock, first and second counters.

The device provides the removal from the communication channel of the part of the frame that fell into the Nego as a result of a collision in the device prior to this, receiving information from the communication channel of the frame intended for the subscriber connected to this device and transmitting it to the CE channel. and transmitting a frame of information issued by any subscriber to anyone other than connected to this device, removing from the communication channel a frame of information issued previously by the subscriber;

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connected to this device, and passed through the ring only once.

The device does not exclude the possibility of a part of the frame damaged during a collision getting into the communication channel, there are no multicast and ring testing capabilities to determine the composition of potential interaction participants.

Closest to the proposed device for receiving and transmitting information in an annular communication channel, comprising a receiver, first to fourth registers, a delay element, a switch, a transmitter, first to seventh decoders, first to twelfth AND elements, first to sixth triggers, first -th third elements OR, the first-fifth elements are NOT, the first and second counters, a clock generator.

The device prevents collision of information frames in a communication channel due to channel capture equipment, implements the possibility of multicast addressing of transmitted information frames and operational testing of possible interaction participants.

The device has the following disadvantages:

The channel capture equipment does not sort messages by the degree of their importance, i.e. channel acquisition is performed without regard to message priority. There is no feedback in the device, i.e. the correct reception of the packet by the recipient is not confirmed. These shortcomings reduce the reliability of information transfer.

The purpose of the invention is to expand the scope by limiting priority polling and increasing reliability.

The drawing shows a structural diagram of the device.

The device contains a receiver 1, first register 2, delay element 3, switch 4, transmitter 5, first - seventh decoders 6-12, fourth element 13, second register 14, seventh element 15, second counter 16, third register 17 , the eighth element And 18, the first trigger 19, the fifth element And 20. the fourth element NOT 21, the sixth element And 22, the sixth trigger 23, the fifth trigger 24, the third element NOT 25, the second element NOT 26, the first element And 27, the fourth trigger 28, the first element NOT 29, the eleventh element AND 30, the third element OR 31, the fourth element NOT 32, the third element AND 33, rety trigger 34, the twelfth AND gate 35, the second flip-flop 36, a first OR gate 37, AND gate tenth

38, the second AND element 39, the third register 40, the ninth AND element 41, the clock generator 42, the first counter 43, the third OR element 44, the comparator 45, the thirteenth AND element 46, the fifth OR element 47, the fourteenth AND element 48, the eighth decoder 49, p the thirteenth element AND 50, the fourth element OR 51,

Collision avoidance of information frames in a communication channel occurs due to a channel capture operation performed by a device having a frame of information for transmission. A channel capture procedure taking into account the priorities of transmitted messages is performed as follows.

If the channel is not captured by any other device of the ring, a signal with a high logic level is taken from the output of trigger 28 and fed to the input of AND 33 through the element NOT 32. If the device has an information frame prepared for transmission, high-high signals from the outputs of triggers 19 and 36 the level of the logical unit is fed to the input of the And 27 element, from the output of which the level of the logical unit is fed to the second input of the And 38 element. The group of decoders 6-12, 49 constantly analyzes the state of the communication channel. If no messages are transmitted via the channel, the decoder 6 generates a logical unit signal, which is fed to the third input of the And 33 element, from the output of which, through the OR 44, 31 elements, is fed to the first input of the register 17, allowing the reading of the calling word containing the addresses of subscribers who should make a copy of the frame, and the priority of the message, which is a combination code, to the communication channel. If at this point in time the call word from another device is also transmitted via the communication channel, the decoder 7 generates a logical unit signal, which is fed to the first inputs of the AND elements 46, 48. The comparator 45 compares the message priorities contained in the received and proper call words, which are read respectively from the outputs of registers 2 and 17, If the priority of the own message is higher, a logical unit signal is received from the second output of the comparator to the fourth input of AND element 46. If the calling word is not sent by this device, the sender's address field is not its address, and at the output of the decoder 9 there is a low-level signal, which, passing through the element HE 21, goes to the second input of the element And 46, the third input of which is fed a high level from trigger output 19. Signal

logical unit from the output of the element AND 16 is fed to the third input of the element OR 31, allowing the reading of the ringing word into the communication channel. If the priority of the own message is not higher than the priority contained in the received call word, the comparator 45 generates a signal of a logical unit at the first output connected to the second input of the And 48 element. At the third and fifth inputs of the And 48 element, high logic levels are applied, and since the device does not go at this moment of transmitting its frame of information, and trigger 24 is reset, the signal from its output through the element HE 26 with a high logical level comes to the fourth input of the element And 48, from the output of which the signal is high VHV is applied to a first input of OR gate 47, the output signal of which is fed pas trigger input 28, switches it to a single state. In each of the ring devices, upon receipt of the call word, the output of the decoder 7 shows the level of the logical unit, which is fed to the input of the And element 20. If the call word is not sent by this device, the address of the sender is not its address, and the output of the decoder 9 there is a low-level signal, which, having passed through the element 21, is fed to the input of the And element 20. If the device itself does not transmit its information frame at this time, the low-level signal is removed from the output of trigger 24, which the first through the element 26 is fed to the third input of the AND 20 element and through the OR element 47 to the input of the trigger 28, switching it to the single state.

Upon receipt of the information frame, the subscriber checks the correct reception by calculating the checksum and generates a response receipt to the sender of the frame containing the packet number and information about the correct reception.

When transmitting a receipt that is short reported, no channel acquisition operation is performed. The subscriber loads the receipt into register 17 and sets the trigger 36. When a high-level signal appears at the output of the decoder 6, the output from the output of the And 39 element is removed, the signal arriving at the inputs of the elements 37, 44 and the switching switch 4. The signal from the output of the OR element 37 resets the trigger 36 and the signal from the output of the OR element 44 through the OR element 31 allows the output from the register 17. The receipt enters the communication channel and is transmitted by each device, in addition, whose address is specified as the recipient address. Upon receipt of the receipt at the output of the decoder 49 - a high level signal supplied to the input of the And 50 element. If the receipt is intended for this device, the second input of the And 50 element also receives a high level signal from the output of the decoder 9. From the output of the And 50 element, the level of the logical unit goes to the input of the OR element 51, the output signal of which gates the record in register 40 and switches the switch 4, prohibiting further transmission of the receipt.

Thus, the device carries out the capture of the communication channel, taking into account the priority

5 transmitted messages and monitors the correct reception of information on the transmitting side.

Claims (1)

SUMMARY OF THE INVENTION A device for receiving and transmitting information in an annular communication channel, comprising a receiver, the input of which is the information input of the device, the output of the receiver is connected through the first register to the inputs of the first to sixth 5 decoders and through the delay element - with the first inputs of the switch and the second and third registers, the output of the switch is connected to the input of the transmitter, the output of which is the information input of the device, the first and second triggers, the first inputs of which are respectively the first and second inputs of the device, the output of the first trigger is connected to the first input of the first element And through the first element NOT-to the first input of the second element And, the output of the third decoder is connected to the first inputs of the third and fourth triggers q of the first decoder is connected to the second input of the second element And and the first input of the third element And, the output of the second decoder is connected to the first inputs of the fourth and fifth elements And, the output of the fourth decoder is connected to the second input of the fourth 5 element And, the first input of the sixth element And, the output of the fifth decoder is connected to the first input of the seventh element And, the output of the sixth decoder is connected to the first input of the eighth element And, the seventh de0 encoder, the output of the fourth element And is connected to the first input of the fifth trigger, the output which is connected to the first input of the first OR element, and through the second element NOT to the second input of the fifth element 5 And, the sixth trigger, the input of which is connected through the third element NOT to the second exit of the seventh element AND, the output of the fourth trigger is connected through the fourth element Н Е to the first input of the third element And, the output of which is connected to the first input of the second OR element, a clock pulses, the output of which is connected to the first input of the ninth AND element, the output of which is connected to the first input of the first counter and the third OR element, the output of the first counter is connected to the second input of the first trigger, the second counter, the first output it is connected to the first input of the sixth trigger, the second output of the second counter is connected to the second input of the second register, the output of the second AND element is connected to the second inputs of the first and second OR elements and the second input of the switch, the output of the third trigger is connected to the second inputs of the sixth trigger and the eighth element AND the output of which is connected to the first input of the second counter and the second input of the second register, the output of the seventh element And is connected to the second input of the third trigger, the output of the first OR is connected to the second inputs of that element AND and the second trigger, the output of which is connected to the third input of the second element AND and the second input of the first element AND, the output of which is connected to the third input of the third element AND, the output of the second element OR is connected to the second input of the third element OR, the output of the tenth element And connected to the second input of the first counter and the first input of the fourth register, the output of which is connected to the third input of the switch, the second input of the second counter and the third input of the second register are combined and are the third input of the device a, the output of the third OR element is connected to the fourth input of the switch and the second input of the fourth register, the second output of the first counter is connected to the third input of the fourth register, the fourth input of which is the fifth input of the device, tenth, eleventh and twelfth elements of And, the first input of that element 1/1 is the fourth input of the device, the second input of the tenth element And is combined with the first input of the second element And, the fourth element is NOT, the outputs of the second and third registers are respectively the first and second the outputs of the device, the output of the sixth togger is the third output of the device, characterized in that, in order to expand areas of application due to the organization of priority polling and increasing reliability, the thirteenth, fourteenth and fifteenth element And are introduced into it, the fourth and fifth elements OR, the sixth trigger, the eighth decoder, comparator, the first output of the comparator is connected to the first input of the thirteenth element And, the output of which is connected to the third input third element OR. the output of the sixth AND element is connected to the first input of the fourth OR element, the output of which is connected to the first input of the switch and the second input of the third register, the output of the fourth register is connected to the first input of the comparator, the second output of which is connected to the first input of the fourteenth AND, the output of which is connected to the first input of the first item OR, output which is connected to the third input of the seventh element And and the second input of the fourth trigger, the output of the fourth decoder is connected to the first input of the eleventh element And and through the fourth element NOT to the third input of the fifth element And, the first input of the twelfth element And and the second inputs of the thirteenth and fourteenth AND elements, the output of the fifth AND element is connected to the second input of that OR element, the output of the seventh decoder is connected to the second inputs of the sixth and twelfth elements AND, the output of the twelfth element AND is connected to sixth switch input, first register output connected to the second input of the comparator and through the eighth decoder - with the first input of the pth of the eleventh element And, the second input of which is combined with the first input of the fourth element of And, the output of the pth the AND element is connected to the second input of the fourth OR element, the output of the third decoder is connected to the second input of the eleventh element AND, the output of which is connected to the second input of the fifth trigger, the output of the second decoder is connected to the third inputs of the thirteenth and fourteenth elements And, the output of the first trigger is connected to the fourth inputs of the thirteenth and fourteenth elements And, the fifth input of the fourteenth element AND is combined with the second input of the fifth element of I. Inf. departure. Inf Out Vdh.j