SU1444796A1 - Multichannel device for exchangge of data between modules of computing system - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in multi-machine and multiprocessor computer systems with a backbone structure, processing large amounts of data. The purpose of the present invention is to expand the functionality of the device of conflict-free information exchange between subscribers of the computing system along two common routes. The goal is achieved by the fact that the device contains M channels (by the number of computing modules in the system), each channel contains two memory blocks and a priority block. Each of the channels may input information from either of the two free highways. 4 il.

Description

4 1

about:

The invention relates to the field of computer technology and can be used in multi-machine and multiprocessor computer systems with a backbone structure.

The purpose of the invention is to expand the functionality of the device.

FIG. 1 shows a block diagram of the device; FIG. 2 is a block diagram of a priority block; in fig. 3 - structural diagram of the pulse generator; in fig. 4 shows an example of the execution of a pulse former.

The device contains channels 1, -1 (the number of which is equal to the number of modules of the computing system), one of which contains four triggers 2-5, two elements NOT 6.7, four elements 8-11 of the delay, priority block 12, generator 13 pulses, two blocks 14, 15 buffer memory, four counters 16-19, two circuits 20, 21 comparisons, ten items AND 22-31, an AND-OR element 32, a block of 33 elements, four-way block 34-37 ele, cops And, four elements AND-NOT 38-41,

two decoders 42, 43, two pulse drivers 44, 45 pulses, six elements OR 46-51, first input 52 channel polling, first output 53 channel polling, second input 54 channel polling. second exit 55 polling channel, vpsod

56 signal resolution, input

57 channel signals, information channel input 58, information channel output 59, channel request permission input 60, output, 61 channel cut-off signals, channel request signal input 62, first device polling line 63, second device polling line 64, first gating input 65, device gating second input 66, first device response response output 67, second device response output 68, first device inhibit output 69, second device inhibit output 70, first device data input 71, first device address input 72 Second input .73 dan-- nps device, the second input 74 the device address.

The priority block 12 (FIG. 2) contains two AND 75, 76 elements, two AND-NE 77, 78 elements, one delay element 79.

The elements of the device (figure 1) are connected as follows. In each channel, the output of the AND element 22 is connected to the input of the trigger 2, the direct output of which is connected to the first input of the OR 46 element, the output of the delay element 8 is connected to the first input of the AND 23 element, the output of which is connected to the trigger input of the pulse generator 13, the output of the element 9 delays are connected to the first input element AND 24, the output of which is connected to the first gate input device 65, the output of the element OR 47 is connected to the reset input of trigger 2, the inverse output of which is connected via the first output 69 of the device prohibition th inverse input element And 22, the second inputs of the elements OR 46, 47 M-th channel 1 is connected via the first line 63 of the survey with the output of the element OR 46 (M-1) -th channel 1, the output element And 25 is connected to the input of the counter 16, the recording input of the buffer memory block 14 and the trigger setup input 3, the direct and inverse outputs of which are connected respectively to the first inputs of the AND-NE 38.39, the output of the AND-HE 38 are connected to the second input of the AND-25 element and to the output 56 of the resolution signal of the module, the first input of the element I 25 is connected to the input 57 of the output signal channel , The first input element | 1 and 26 is connected to the generator 13 output of pulses, and the output to the reset input of trigger 3, the count input of the buffer memory block 14 and the counter input 17, the output group of which is connected to the count input of the buffer block 14 and the first group of inputs of the circuit 20 comparing the second group of inputs of which is connected to the group of outputs of the counter 16 and with the input of the write address of the block 14 of the buffer memory, whose information input is connected to the information input of the device, the output of the comparing circuit 20 is connected to the second inputs of the elements AND - H E 38, 39, the output of the NAND element 39 is connected to the direct input of the element AND 22 and the inverse input of the element OR 47 and the second input of the element And 26, the output of the element And 27 is connected to the input of the counter 18, the input 15 of the buffer memory and the input reset the trigger 4, the direct and inverse outputs of which are connected respectively to the first inputs of the elements AND-NOT 40, 41, the output of the element AND-NOT 41 is connected to you

The module request permission signal WAIT 60 and with the first input of the AND element 27, the second input of which is connected to the module request signal input 62, the output group of the counter 18 is connected to the read address input of the buffer memory block 15 and the first group of comparison circuit 21 inputs whose output is connected with the second inputs of the elements AND-NOT AO, 41, the output of the element IS-NO 40 is connected to the output 61 of the channel interruption signal, the group of outputs of the counter 19 is connected to the second group of inputs of the comparison circuit 21 and to the write addresses of the block 15 of the buffer memory, information the stroke of which is connected to the information input of the module, the output of Pulse Shaper 45 is connected to the first output 67 of the device response 67, the information and gate inputs of the decoder 42 are connected respectively to the first input 72 of the address and the first input 65 of the gate of the device, the input of the delay element 10 is connected to the output of the element AND-NOT 39, and the output with the direct input of the element AND 28 and with the inverse input of the element OR 48, the output of which is connected to the reset input of the trigger 5, the inverse output of which is connected through the second output 70 of the device inhibit the first inverse input of the element 28 and the second inverse input of which is connected to the direct output of the trigger 2, the output of the element 28 and connected to the input of the installation of the trigger 5, the direct output of which is connected to the first input of the element OR 49, with the first input of the element AND-OR 32, with the second inverse input of the element AND 22 and with the first input of the element OR.50, the second input of which is connected to the direct output of trigger 2, the first input of the element OR 46, the second input of the AND 30 element and the second the input element AND-OR 32, the output element OR 50 is connected to in by the delay element 8 and with the second input of the element AND 23, the direct input of the element OR 48 and the second input of the element OR 49 of the M-th channel are connected to the output of the element OR 49 (M-1) -th channel through the second polling line 64, the second inputs elements 29 and 30 are connected to the generator output — 13 pulses; the output of element 30 is connected to the input of the delay element 9, the second input of the element 24, and the control

96

the inputs of blocks ZD, 36 elements And, the output of element And 29 is connected to the second input of element And 31, the control inputs of blocks 35, 37 of elements And and the input of element 11 of delay, the output of which is connected to the first input of element And 31, the output of which is connected to the second input 66 of the device gating, the third and fourth inputs of the AND-OR element 32 are connected respectively to the first 67 output and the second 68 output response of the device, and you - to the control input generator 13 gt pulses, information inputs of the blocks 34, 35 elements And are connected with the second group of inform the output outputs of the block 14 of the buffer memory, and the outputs, respectively, with the first and second inputs 72, 74 of the device address, the information inputs of the blocks 36, 37 of the AND elements are connected to the first group of information outputs of the block 14 of the buffer memory, and the inputs Actually, the first 71 and second 73 data inputs of the device, the information and gate inputs of the descrambler 43 are connected respectively to the second input 74 of the address and the second input 66 of the gate of the device, and the output to the second input of the priority unit 12, the first input of which is connected to the output the decoder 42, the control input - with the output of the element AND-NOT 40, the first output - with the first input of the element OR 51, the first control input of the block 33 of the elements AND-OR, the input of the imaging unit 44 pulses, the second output - with the second input of the element OR 51 , the second control input of the block 33 of the AND-OR elements, the input of the pulse driver 45, the output of which is connected to the second response 68 of the device response, the output of the OR element 51 is connected to the installation input of the trigger 4, the recording input of the buffer memory block 15 and the input of the counter 19, the first and second informational inputs of the block 33 AND-OR elements are connected to the first 71 and second 73 data inputs of the device, respectively, and the output to the information input of the buffer memory block 15.

In each unit 12 pribriteta elements are connected as follows. The control input of the priority block 12 is connected to the first inputs of the And 75, 76 elements, the second input of the And 75 element is connected to the first input of the block 12

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the priority and direct entry of the element -, 5 are two-address

memory, can be executed, for example, on the BIS type KR 1802 IR1 and coI-HE 78, the inverse input of which is connected to the second priority output 12, the output of the delay element 79

, .. -. .. - g then t of two channels of recording-counting and the first input of element 77 AND-NOT, the second “p channel of channels using the input of which is connected to the second input of the priority unit 12 and the second

the input element And 76, and the output with the third input element And 75, the output element AND IS 78 is connected to the third input element And 76, the output of which is connected to the input of the element 79 delay, the output element And 75 is connected to the first output of the block 12 priority. The pulse generator 13 contains (FIG. 3) a pulse shaper 80, an AND 81 element, an OR 82 element, a trigger 83, two delay elements 84, 85

is for recording and another for reading data.

Counters are intended for

10 indicate the addresses at which data is written (read) in each of the memory channels of blocks 14 and 15, after the next access to one of the memory channels of blocks 14 and 15

 the corresponding counter increases its state by one. Having reached the maximum value equal to the number of cells in the buffer memory block, the counter after the next call

The shapers of 44, 45, 80 pulses are set to the zero state, they contain a delay element 86, an element (, the counters 16-19 work — HE-87-cycling, and the And 88 element (Fig. 4).

In each canape, information input 58 and output 59 of channel 1, as well as output 56 of the output permit signal, output 57 of the output signal, output 60 of the request permission signal, exit exit 61

chesky).

Comparison circuit 20 generates a coincidence signal with equal content of J counters 16 and 17, and comparison circuit 21 with equal content counters 18 and 19. Decoders 42 and 43 are designed to decrypt addresses assigned respectively

My counters 18 and 19. Decoders 42 and 43 are designed to decrypt addresses assigned respectively

interrupt signal, input 62 signal

requests are connected to one module

(to the source of requests for data exchange), 0 to the first and second inputs 72, 74, which are injected into the computer system, and in each of the tapping channels Triggers 2 are designed to forcibly output the decoder signals of the world of the prohibition signal on the first

exit 69 of the ban after the selection, the most priority channel 1 before ob42 and 43, corresponding to the channel number The remaining outputs of the decoders 42,

35 43 channels are not used. .

exchanging data through the first data input 71 and capturing the first line with this channel for the duration of data exchange

The triggers 3, 4 are intended for storing the mode in which the blocks 14 and 15 of the buffer memory are accessed.

The triggers 5 are designed to generate a prohibition signal on the second prohibition code 70 after selecting the most priority channel 1 before exchanging data via the second data input 73 and capturing the second highway

d) 5 counters 16 and 17 are equal to zero, and the trigger 3 is in the zero state; at the output 56, a single signal is set using the AND-HE element 38, which indicates the presence of

this canape for the time of the exchange of data of free cells in block 14 of the buffer

Blocks 14 and 15 of the buffer memory. If there are 56 ka at output, they are intended for temporary xpaHSiinH data, which, respectively, from the source of a single signal, the source outputs an output signal 57, which through input 25 to input 55 of the counter 16, the recording input of the block 14 of the buffer and the single input trigger 1. Lapnma and the address of the receiver, KOTOPOMV they p -, (assigned, through info mlrsh-imL pass

 The first and second data pockets 71, 73 are received and received, and the memory cells of block 14 have additional bits for storing the address of the module to which the data is intended,

is for recording and another for reading data.

Counters are intended for

indicating the addresses at which data is written (read) in each of the memory channels of blocks 14 and 15, after the next access to one of the memory channels of blocks 14 and 15

the corresponding counter increases its state by one. Having reached the maximum value equal to the number of cells in the buffer memory block, the counter after the next call

is set to the zero state (, the counters 16-19 work-cycle

it is set to zero (the counters 16-19 work- cycle

chesky).

Comparison circuit 20 generates a coincidence signal with equal content of J counters 16 and 17, and comparison circuit 21 with equal content counters 18 and 19. Decoders 42 and 43 are designed to decrypt addresses assigned respectively

only decoder outputs are addressed to the first and second inputs 72, 74

42 and 43, corresponding to the channel number. The remaining outputs of the decoders 42,

43 channels are not used. .

The device works as follows.

Initially, triggers 2-5, counters 16-19 are in the zero state.

If data is required, the information source analyzes the state of output 56 of its channel 1. In the initial state, since the contents

counters 16 and 17 is zero, and trigger 3 is in the zero state; at output 56, a single signal is set using the IS-NE element 38, which indicates the presence of

free cells in block 14 buffer

memory If there are 56

the source of a single signal, the source generates an output signal 57 to the input 57, which, through element 25, enters the input of counter 16, the record input of block 14 of buffer and the single trigger input 1. Lapnm and the address of the receiver, KOTOPOMV they n -, (assigned, through info

It goes to the first poll 53 polling this channel, etc., until the flip-flops 2 of all channels of lower priority are reset. A single signal from the output of trigger 2 through the SHSh 50 element is fed to the input of the element 8 delayed CI, which after the transition processes are over, when a higher priority request is selected, and a single signal appears at the start of the I 23 element, which indicates the resolution of the data in the trunk. This signal is fed to the trigger input of the generator 13 pulses.

The pulse generator 13 (FIG. 3) operates as follows.

Single trigger signal

58 are written in parallel code in the memory cell of block 14, whose address is determined by the contents of the counter

16 (at the first call - in the zero cell). On the back fy signal front, Counter 16 increases its state by one, and trigger 3 is set to one. After that, the source either proceeds to the execution of the main program, or similarly writes the address and data into the next memory cell of block 14.

Since the contents of the counters 16 and 15

17 is different, then the output of the comparison circuit 20 is a zero signal, and the output of the NAND 39 element is a single signal, which indicates that there is a requirement to capture the 20 input to the input of the main driver for data exchange, Unity-80 pulses, which produces the same signal at the output of the element NAND

38 is saved. Single signal with

output element AND-NOT 39 through the element

And 22, since its inverse inputs 5 from the direct output of the flip-flop 83 post-zero receive zero potentials from the pulse generator 13 output

first exit 69 of the ban and with one and is present there until

which trigger output 5, sets to the control input of the generator 13

pulses will not receive a single pulse, which from the control input of the generator 13 enters through the delay element 85, the delay time of which is calculated equal to the time reached for writing data to the block ,, (- 15 buffer memory of the receiving channel, to the reset input of the trigger 83, thus setting it to the zero state. The zero signal from the output of the trigger 83 arrives at the output of the generator 40 13 pulses and is present until the pulse from the output of the delay element 85 passes through the delay element 84, calculated for the backward time The rails are equal to the time g is written to the block 15 of the buffer memory by a single pulse that sets the trigger 83 through the element OR 82 to the unit state.

} 0

trigger 2 in one state. At the same time, using the NOT element 6, a prohibition signal is set at the first output 69 of the prohibition, which, entering the inverse inputs of the AND elements 22, blocks further recording of requests in channels 1 for the capture of the first data transmission line. During this time, the triggers 2 of the other channels 1 can also be fixed requirements for data exchange.

From this moment, the selection of the highest priority request begins, as a result of which the trigger 2 in the channel, which has the highest priority of all requesting trunk for exchange, remains in single state (the channel priority decreases with increasing its number, i.e. the first channel has the highest priority ). Trig- repbi. 2 is set to the zero state using a polling signal, which is generated at the first polling output 53 of the priority channel 1 (from among those requesting the trunk) and through the first polling line 63 arrives at the first polling input 52 of the neighboring -d channel 1 ( with a lower priority), which sets the trigger 2 to the zero state via the SHSh 47 element and simultaneously via the OR 46 element of the postunal receiver. The pulse from the output of the delay element 84 arrives at the first input of the AND 81 element and, if the second input of the AND 81 element contains a single signal from the triggering input of the generator 13, sets the trigger 83 to the single state through the OR 82 element, thereby setting the single signal to output of the generator 13. A single signal from the output of the generator of 13 pulses through the element And 26 enters the input of the resolution to receive the block 14 of the buffer memory, the input of the counter 17 and zeroes on the first interrogation 53 of this channel, etc., until the trigger clears S 2 all channels of lower priority. A single signal from the output of trigger 2 through the SHSh 50 element is fed to the input of the element 8 delayed CI, which after the transition processes are over, when a higher priority request is selected, and a single signal appears at the start of the I 23 element, which indicates the resolution of the data in the trunk. This signal is fed to the trigger input of the generator 13 pulses.

The pulse generator 13 (FIG. 3) operates as follows.

Single trigger signal

the input is fed to the input of the imager 80 pulses, which produces

the input is fed to the input of the imager 80 pulses, which produces

a single impulse that establishes through trigger element 82 or 82 the trigger 83 into a single state. Single signal

, (- 0 g

} 0

pulses will not be received by a single pulse, which from the control input of the generator 13 enters through the delay element 85, the delay time of which is calculated equal to the time reached for recording data in block 15 of the buffer memory of the receiving channel 83, thus setting it to zero state. The zero signal from the output of the trigger 83 arrives at the output of the generator 13 pulses and is present until the pulse from the output of the delay element 85 passes through the delay element 84, calculated for the delay time equal to the data recording time in the channel buffer memory block 15 -receiver. The pulse from the output of the delay element 84 arrives at the first input of the AND 81 element and, if the second input of the AND 81 element contains a single signal from the triggering input of the generator 13, sets the trigger 83 to the single state through the OR 82 element, thereby setting the single signal to output of the generator 13. A single signal from the output of the generator 13 pulses through the element And 26 is fed to the input of the resolution to receive the block 14 of the buffer memory, the input of the counter 17 and the zero input of the trigger 3 and through the element 30 and the control inputs of the blocks And FOR, 36. According to the read signal, the data and the address of the receiver are entered through the blocks of elements 36 and 34, respectively, to the first data input 71 and to the first input 72 of the address. Through the delay time of the delay element 9, calculated for the maximum signal propagation time in tires, at the output of the element 24, a single signal arrives through the first gates 65 of the gating to the inputs of the decoder 42 of all channels,

Thus, channel 1, which has the highest priority for the release of information, began to feed information to channel 1 — the receiver through the first input 71 data and the first input 72 addresses.

Since at this time, the remaining channels 1 may also contain single signals at the outputs of the AND-HEN 39 elements, indicating that there are requirements for the seizure of the trunk, these single signals go through the delay element 10 to the first direct input of the AND 28 element, The second direct input of which receives a single signal from the zero output of flip-flop 2, and its inverse input receives a zero signal from the second prohibition output 70. Since, in several channels 1, triggers 5 can be set to one state, among these channels, the highest priority request is also selected, which will result in trigger one 5 having the highest priority among the channels that continue to achieve access to highway. The triggers 5 of all the other channels will be set to the zero state using a polling signal, which is formed at the second output 55 of the priority channel and the second polling line 64 goes to the second input 54 of the channel 1 with lower priority and resets through the OR element 48 trigger 5 and simultaneously through the element OR 49 enters the second output 55 of polling this channel, etc., until the flip-flops 5 of all channels of lower priority are reset. The single signal from the output of trigger 5 through the element OR 50 is fed to the input el ment 8 delays which Burst

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five

After the termination of transient processes, when selecting a higher priority request, and at the output of AND 23 in the highest priority channel 1, a single signal appears from among those who continue to gain access to the trunk, which indicates that data is allowed to be issued to the trunk. This signal arrives at the trigger input of the generator 13 pulses, at the output of which a single signal appears, which through element 26 enters the input resolution of the block 14 of the buffer memory, the input of counter 17 and the zero input of trigger 3 and through element 29 enters To the control inputs of blocks 35, 37 elements I. According to the read signal, the data and the address of the receiver are output through the blocks 37, 35 elements AND, respectively, to the second data input 73 and to the second input 74 of the address. Through the delay time of the delay element 11, calculated for the maximum signal propagation time in batches. At the output of the element I 31, according to a Vits, a single signal arriving through the second gate input 66 to the inputs of the construction of the decoders 43 of all channels 1.

The address inputs of the decoders 42 and 43 receive the addresses from the first 72 and second 74 ad5 res inputs, respectively. In the channel receiver, the address of which coincides with the address transmitted at the first input 72 of the address, a single signal from the decoder 42 is fed to the first input of the priority block 12. In the channel receiver, the address of which corresponds to the address transmitted to the second input 74 of the address, a single signal from the output of the decoder 43 is fed to the second input of the block 12 priority.

Unit 12 priority works as follows.

On the first and second inputs of block 12, the following situations are possible.

A single signal arrives at the first input of block 12. At the same time, the zero signals at the second input and the second output of block 12 through the IS-NE 77 element and the single signal from the control input of block 12 allow the single signal to pass through the And 75 element to the first input block 12.

A single signal arrives only at the second input of block 12;

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five

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the left signal from the first input of block 12 through the element IS-NE 78 and the single signal from the control input of block 12 allow the passage of a single signal through the element AND 76 to the input of delay element 79 and through the delay time calculated for the end of transients after writing information to the block 15 buffer memory, a single signal for Wits at the second output of block 12. Single signal; From the second output and the second input of the block 12, entering the AND-NE 77 element, prohibits the passage of a single signal from the first input of the block 12 through the AND 75 element.

Single signals arrive simultaneously at the first and second inputs of block 12, and the second output of block 12 contains a zero signal. At the same time, the zero signal from the second output of block 12 through the AND-NE 77 element together with a single signal at the control input of block 12 allows the single signal to pass through the element 75 to the first output of block 12. The zero signal from the second output of the block is 12; at the inverse entry of the element IS-NE 78, prohibits the passage of a single signal through the element AND 76. Thus, with simultaneous receipt of single signals at the first and second inputs of block 12, a single signal is received only at the first output of block 12.

A single signal from the first output of the priority block 12 is fed to the first input of the OR 51 element, the first control input of the AND-OR 33 block and to the input of the pulse shaper 44, which produces a single pulse that arrives at the answer 67 output.

If a single signal is received at the second output of the priority block 12, then it arrives at the second input of the OR 51 element, the second control input of the block of AND-OR elements 33 and the input of the pulse generator 45, which has a single pulse arriving at the output 68 answer.

A single signal from the output of the element OR 51 is fed to the recording resolution input of the buffer memory block 15, the input of the counter 19 and the single trigger input 4. According to the recording signal, the data set either in the first input 71 dan Hbtx or in the second input 73 data

612

(in connection with the input from this channel 1 is received), through a block of I-33 elements, 33 are recorded in the memory of block 15 of the buffer memory of the receiving channel whose address is determined by the contents of counter 19 (at the first call - in the zero cell). The response pulse from the first 67 from the second response output 68 (depending on whether the source channel provides information to the first or second data inputs 71, 73) goes through element 32 to the control input of the pulse generator 13. After a delay time sufficient to write data to the receiver-channel unit 15, a zero signal is set up at the output of the pulse generator 13, thereby setting, through element 26, the zero signal at the read enable input of the buffer memory unit 14, the input of the counter 17 and the trigger 3 input The counter t7 in this case increases its state by one, and the trigger 3 goes to the zero state. A zero signal from the output of the generator 13 pulses through the AND 24 element, if the given source channel carried out the output of information to the first data input 71, is set at the first gate input 65 or via the I-31 element, if the source channel has carried out the output of the second the data input 73 is set at the second gate input 66. Zero signals at gating inputs 65, 66 prohibit address decoding in decoders 42, 43 of receiver channels. At the same time, a zero signal is established at the first or second output of priority block 12 (depending on whether data is received from the first 71 or second 73 data inputs) into the receiving channel. Thereby, data is not allowed to pass through the block of AND-OR elements 33 to the information input of the buffer memory block 15.

In addition, through the OR 51 element, a zero signal is set at the input of the recording resolution of the block 15 of the buffer memory, the inputs of the counter 19 and the trigger 4. The counter 19 increases its state by one, and the trigger 4 is set to one. Thus, in the receiver channel, the states of the counters 18 and 19 became different, therefore, at the output of the comparison circuit 21, a zero

a signal, and a single signal is set at the output of the NAND 41, which indicates the presence of data in the block 15 of the buffer memory. This signal is fed to the input element And 27 and the output 60 of the signal resolution. Request. The information receiver periodically analyzes the state of output 60 of its channel 1. If there is a single signal at output 60, the information receiver sends to the input 62 a Request signal, which, through element 27, enters the send resolution of the block 15 of the buffer memory, the inputs of counter 18 and trigger 4

The data from the memory cell of the block 15, whose address is determined by the state of the counter 18 (at the first

channel receiver. If after the transmission of the next data word, the contents of the counters 16 and 17 turn out to be the same, a single signal is output at the output of the comparison circuit 20, and an output of the IS-HE element 39 provided that the trigger 3 is in the zero state, i.e. . produced

reading from the buffer memory block 14, a zero signal is generated, indicating that the buffer memory block 14 is empty. This signal will pass through the inverse inputs of the elements OR 47 and 48 and sets trigger 2 or trigger 5 (depending on which of them is cocked in this channel) to the zero state. At the same time through the element NOT 6 on the first

25

thirty

35

Circulation is from the zero cell), and the 2-bar inlet 69 is set to zero via information outlet 59 to the information receiver. On the falling edge of the signal request, the counter 18 increases its state by one, and the trigger 4 is set to the zero state. In the event that a source of information from the source of information to the block 14 of the buffer channel of the source channel has arrived, it did not. Since the number of data words to be transmitted (and the addresses of the receivers may be different), the contents of the counters 16 and 17 after the first transmission remain different. At the same time, a zero signal is present at the output of the comparison circuit 20, and a single signal is set at the output of the AND-HI element 39, which, arriving at the inverse input of the OR element 47, does not reset the trigger 2, similarly, the source 5 is in the one state, and trigger 2 is in the zero state. In this case, a single signal from the output of the AND-NOT element 39 passes through the delay element 10 and, arriving at the inverse input of the element OR 48, does not reset the trigger 5. into the zero state. Since the trigger 2 (or trigger 5) of the source channel remains in one state, a single signal is stored at the trigger input of the generator 13 pulses and after a time sufficient for recording data in the block 15 of the buffer memory of the source channel, at the output of the generator 13 pulses, set the single signal again and the next data word will be transferred to the buffer memory block 15 in the same way

40

45

50

55

if the given channel has carried out the data output to the first data input 71 or through the element NOT 7, it has been set; A zero signal is applied to the second barring input 70 if the channel has sent data to the second data input 73. Thus, it is permitted to capture a trunk by another source.

The following situations are possible during the data exchange process.

When issuing data from the information source to channel 1, all the cells of the buffer memory block 14 are occupied. The contents of the counters 18 and 19 are equal, i.e. at the output of the comparison circuit 21, a single signal is present, and the trigger 3 is in the single state (for this purpose, recording was performed in the buffer memory block 14). In this case, a zero signal is output from the output of the element IS-NE 38 to the input of the element 25 and the output 56, which prohibits recording in block 14, the output of the element IS-NOT 39, a single signal is received, which comes as a request signal for the capture of the trunk to the input element And 22 to the input element 10 delay.

When data is output from the block 14 of the source channel to the block 15 of the receiver channel, all the cells of the block 15 of the buffer memory are occupied. The contents of the counters 18 and 19 are equal, i.e. At the output of the comparison circuit 21, a single signal is present, and the trigger 4 is in a single state (before this, recording was made in block 15). In this case, the output element AND-NOT 40

five

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five

on entry 69 prohibition is set to zero

0

five

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five

if the given channel has carried out the data output to the first data input 71 or through the element NOT 7, it has been set; A zero signal is applied to the second barring input 70 if the channel has sent data to the second data input 73. Thus, it is permitted to capture a trunk by another source.

The following situations are possible during the data exchange process.

When issuing data from the information source to channel 1, all the cells of the buffer memory block 14 are occupied. The contents of the counters 18 and 19 are equal, i.e. at the output of the comparison circuit 21, a single signal is present, and the trigger 3 is in the single state (for this purpose, recording was performed in the buffer memory block 14). In this case, a zero signal is output from the output of the element IS-NE 38 to the input of the element 25 and the output 56, which prohibits recording in block 14, the output of the element IS-NOT 39, a single signal is received, which comes as a request signal for the capture of the trunk to the input element And 22 to the input element 10 delay.

When data is output from the block 14 of the source channel to the block 15 of the receiver channel, all the cells of the block 15 of the buffer memory are occupied. The contents of the counters 18 and 19 are equal, i.e. At the output of the comparison circuit 21, a single signal is present, and the trigger 4 is in a single state (before this, recording was made in block 15). In this case, the output element AND-NOT 40

a zero signal is output which is fed to the control input of priority unit 12, prohibiting the appearance of a single signal at the outputs of unit 12, thereby prohibiting the issuance of a response signal using the 4A, 45 drivers and prohibiting recording through block OR 51 to write to the buffer storage unit 15 . The zero signal from the output of the K-NE 40 element also goes through the output 61 to the information receiver. On this signal, the information receiver interrupts the data processing program and reads the data recorded in block 15 of the buffer memory by issuing a signal Request to the input 62 of the receiver channel. In this case, a single signal is output from the output of the element NE 41 to the input of the element 27 and the output 60 of the request permission signal.

Since, in the first case, downtime of information sources is possible, and in the second case, the receivers of information are interrupted, this can lead to a decrease in the performance of the computing system. Therefore, the capacity of blocks 14 and 15 of the buffer memory must be calculated in such a way that the probability of overflow of blocks 14 and 15 is sufficiently small.

The technical advantage of the proposed invention as compared with the basic (. Prototype) is IB that the basic device does not allow the non-conflicting exchange of information between subscribers of the computing system via two common routes. The use of the proposed device allows conflict-free information exchange between subscribers of the computing system via two common routes m. This significantly increases the functionality of the device, since when using the basic stroystva for providing information exchange between subscribers of two general highway m be required to use two kana fishing for providing a single subscriber access to two main line m. Additionally, the need razrascheni conflict with the exchange of the two highways m administration requires additional equipment relno. Thus, when using a basic device to provide conflict-free exchange between subscribers

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796 6 system by two lines will require an increase of equipment more than 2 times.

Claims (1)

Invention Formula A multichannel device for data exchange between computer system modules, containing M channels, each of which contains three flip-flops, two blocks of buffer memory, four counters, and two circuits. neither, the four elements NAND, a pulse generator, two delay elements, the pole of the elements AND, two elements OR, the first terminal NOT, the first driver of the pulses, the first descrambler, and in each channel the output of the first element I is connected to the input of the installation of the first trigger, my output is connected to the first input of the first OR element, the output of the first delay element is connected to the first input of the second element AND, the output of which is connected to the trigger input of the pulse generator, the output of the second delay element is connected to the first input The third AND element, the output of which is connected to the device’s first gating input, the output of the second element OR, is connected to the reset input of the first trigger, the inverse output of which is connected through the first element NOT to the first prohibition output of the device and the first inverse of the first element and the direct input of the second element OR of the M-th channel is connected via the first interrogation line to the output of the first element OR of the (M-1) -th channel, the output of the fourth element I is connected to the input of the first counter, the input of the recording of the first block the buffer memory and the installation input of the second trigger, the direct and inverse outputs of which are connected respectively to the first inputs of the first and second AND-NES elements, the output of the first AND-NOT elements are connected to the second input of the fourth element. Both with the input signal of the device output, the first input of the fourth element I is connected to the input of the channel output signal, the first input of the fifth element I is connected to the output of the pulse generator, and the output to the reset input of the second trigger, the read input of the first block of the buffer memory and the input of the second counter, the group of outputs of which is connected to the input of the read address of the first block of buffer memory and the first group of inputs of the first comparison circuit, the second group of inputs of which is connected to the group of outputs of the first counter and The address of the recording of the first block of the buffer memory, whose information input is the in-boiled output of which is connected through the second element NOT, to the second output of the device inhibit and to the first inverse input of the seventh element. And the second inverse input of which is connected to the forward the output of the first trigger, the output of the seventh element I is connected to the installation input of the fourth trigger, the direct output of which is connected to the first INPUT of the fourth electric cutter the second element NOT to the second output of the device inhibit and to the first inverse input of Fourth Element And the second inverse input of which is connected to the direct output of the first trigger, the output of the seventh element And is connected to the installation input of the fourth trigger, the direct output of which is connected to the first INPUT of the fourth element input of the device, the output of the first comparison change is connected to the second inputs of the first and second elements NID, the output of the second element NID is connected to the direct input of the first 15 element AND, the inverse input of the second element OR and the second input of the fifth element AND, the output of the sixth element AND connected to the input ohm of the third counter, the read input of the second 20 ment fflI, with the first input of the eighth block of the buffer memory and the reset input of the And element, with the first input of the third trigger element, the forward and inverse outputs of which are connected respectively to the first inputs of the third and fourth elements AND-NOT, the code of the fourth element AND-NOT is connected to the request permission input and to the first input of the sixth element AND, the second input of which is connected to the device request output, the output group of the third element OR is connected to the first and the counter is connected with the input of the first delay element with the second read address of the second block, the inputs of the second element, the forward memory and the first group of inputs of the second comparison circuit, the output of which is connected to the second inputs of the third and fourth elements AND IS, NOT This AND-OR, with the second inverse input of the first Element X, the first input of the glutinous OR element, the second input 25 of which is connected to the direct output of the first trigger, the first input of the first OR element, the first input of the ninth AND element, and the second input of the I-IPI element, way out the input of the third and second input of the fourth element 1W of the M-th channel is connected through the second polling line with the output of the fourth element OR (M-1) of the channel; the output of the pulse generator is connected to the second inputs of the eighth and ninth elements AND of the wipe element AND- NOT connected to the output of the channel interrupt signal, the group of outputs of the fourth counter is connected to the second group of inputs of the second comparison circuit and to the input of the write address of the second block of the buffer memory, whose information output is the information output The device, the output of the first form-45 output of the eighth element And the pulse coupler is connected to the first output from the second input of the tenth element of the response of the device, information AND, the control inputs of the second terminator and the gate inputs of the first decoder are connected with and the fourth block of elements And through the fourth element of delay with the first inputs of the address and gating, gg, the first input of the tenth element And, nid device, characterized by the fact that, in order to expand the functional capabilities of the device, a fourth trigger, a second decoder, a second pulse driver, four ITS elements, four I elements, two delay elements, and OR, the second element is NOT, the unit of whose output is connected to the second input gate of the device, the third and fourth inputs of the AND-OR element are connected to the first and second outputs of the device response, respectively, and to the control input of the pulse generator, information The ion inputs of the first and second blocks of the AND elements are connected to the second group of information AND, the priority block, the block of AND-OR elements, with each channel containing the second AND-NOT element through the third delay element to the direct input of the seventh AND element and the inverse input the third element OR, the output of which is connected to the reset input of the fourth trigger, the invarified output of which is connected through the second element NOT, to the second output of the device inhibit and to the first inverse input of the seventh element AND the second inverse input of which It is united with the direct output of the first trigger, the output of the seventh element I is connected to the installation input of the fourth trigger, the direct output of which is connected to the first INPUT of the fourth element fflI, to the first input of the eighth element I, to the first input of the element element OR is connected to the first and through the first the delay element with the second inputs of the second element And, my ment fflI, with the first input of the eighth AND element, with the first input of the OR element, is connected to the first and through the first delay element with the second inputs of the second AND element, direct the AND-OR, with the second inverse input of the first Element X, the first input of the glutinous OR element, the second input of which is connected to the direct output of the first trigger, the first input of the first OR element, the first input of the ninth AND element and the second input of the I-IPI element, output p that ment fflI, with the first input of the eighth AND element, with the first input of the OR element, is connected to the first and through the first delay element with the second inputs of the second AND element, direct the input of the third and second input of the fourth element 1W of the Mth channel is connected via the second polling line to the output of the fourth element OR (M-1) of the channel; the output of the pulse generator is connected to the second inputs of the eighth and ninth elements AND, the output of the ninth element AND connected to the first and through the second delay element with the second inputs of the third element And, as well as with the control inputs; first and third blocks of elements  the output of the eighth element And is connected to the second input of the tenth element And, the control inputs of the second and the fourth block of elements And through the fourth element of delay with the first input of the tenth element And, the output of which is connected to the second input gate of the device, the third and fourth inputs of the AND-OR element are connected respectively to the first and second outputs of the response of the device, and the output to the control input of the generator. pulses, information inputs of the first and second blocks of elements I are connected to the second group of information codes of the first block of buffer memory, and outputs, respectively, with the first and second inputs of the device address, information inputs of the third and fourth blocks of elements of I are connected to the first group of information outputs of the first the buffer memory block, and the outputs, respectively, with the first and second inputs of the data device, the information and gate inputs of the second decoder are connected respectively with the second inputs addresses and gating the device, and the output - with the second input of the priority block, the first input of which is connected to the output of the first decoder, the control input - with the output of the third NAND element, the first output - with the first input of the sixth OR element, the first control input of the block elements AND-OR, the input of the first pulse generator, the second output - with the second input of the sixth PNI element, the second control yogdim input block of the AND-OR elements, the input of the second pulse former, the output of which is connected to the second code the device response, the output of the sixth element OR is connected to the installation input of the third trigger, the recording input of the second block of the buffer memory and the input of the fourth counter, the first and second the information inputs of the I-ILRG element block are connected respectively to the first and second data inputs of the device, and the output to the information input of the second buffer memory block, I p Ш37 Otgz Fig.z R 86 HZ6, Z9.30 otzg 4 (45.80) R