SU1336118A1 - Buffer storage unit - Google Patents

Abstract

The invention relates to computing technology, namely to recording devices, and can be used in systems for collecting, transmitting and processing information. The aim of the invention is to increase the speed with the co ot 00

Description

rodensity device. The device contains a drive 1, registers 2, the counter 3 address records, counters 4.-4. readout, task block 5

1 m Priority calls, counters pn WORDS. Elements 7, triggers, control of the access signal, decryptors, trigger formation control triggers, additional elements AND 1C-11, blocks 12 — AND elements, delay elements, blocks of NOT elements,

one

The invention relates to computing technology, namely, to memory 1 (it has devices, and can be used in systems for collecting, transmitting and processing information.

The purpose of the invention is to increase the speed of the device.

The essence of the invention is as follows. Filling the accumulator is carried out by the words written; - sequentially formed addresses When a first word appears for one of the directions, its address is recorded in the corresponding 15 read address counter, and the value of its one accumulator is recorded in the word counter (in words ), the limits of which the information of this direction will be recorded in the TA-20 way, when reading the information on one of the requests (directions) there is no need to go through all the addresses, starting from zero, It is enough vit search, beginning with the address of the first 25 words of the na--, rule.

The drawing shows a functional diagram of the device.

The device contains a drive 1, 30 registers 2.1-2p, a counter 3 of the write address, counters 4.1-4 of read addresses, block 5 of defining the priority of calls, counters 6.1-6 of words, elements AND 7.1-7t, triggers 8.1–8 mt in the control of the reference signal, decoders 9.1–9m, the trigger IOl-IOm control the formation of the address schipervyy 15 and second control 16 - the device inputs, the access inputs. The device may carry out any sets of information words to each of the directions as they receive requests for information. At the same time, in order to service one of the directions, it is not necessary to view the entire volume of the accumulator — the search for the necessary information is carried out starting from the address of the first word of the corresponding direction. 1 il.

pulling, additional elements And 11,1-11t, blocks And 12,1-12t element elements 13,1-13t delay, blocks 14,1-14t elements NOT, first 15 and second 16 control inputs of the device, inputs I7, I -17m requests.

The number of registers 2, counters 4 addresses of a link, counters 6 words of elements AND 7, triggers 8 of control of a call signal, decoders 9, triggers 10 of control of formation of a read address, additional elements of AND II, blocks 12 of elements And, delay elements 13, blocks 14 NOT elements, request inputs 17 corresponds to the number of directions m in which information from the buffer storage device is provided.

The number of elements in blocks 12 and 14 is, where n is the number of words that can be written to the drive,

The device works as follows

In the initial state (at the beginning of the next exchange session), the read address formation control triggers 10 are set to one, and all counters are reset (the chains are not shown). The word belongs to the corresponding output information direction by the code of several bits, which arrive at the decoders 9 from accumulator 1,

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When writing information to drive 1, the word is accompanied by a control signal at the first 15 control input of the device.

For example, the received word is intended for the i-ro direction of issuing information. In accordance with the code and the control signal, a high level signal is generated at the first output of the decoder 91, which is fed to the second input of the additional element I lli, the first input of which contains a high level signal from the output of the trigger IOi to control the formation of the read address. The high level signal from the output of the additional element I 111 enters the input of the element 131 delay and the control inputs of the block 121 of the elements I, where it allows receiving information from the output of the counter 3 write addresses. When a signal arrives at the first control input 15 of the device, a high level signal is generated at the first output of the priority setting block 5, which is fed to the input of the write address counter 3 and allows its contents to be transferred to the drive input 1 and the information inputs of the 12 elements I. The first word is recorded at the zero address, the address code of the first word record of the 1st direction from the outputs of the block 121 of the elements I is fed to the second inputs of the counter 41 of the read address and the inputs of the block 141 of the elements NOT. From the outputs of the block 141 elements NOT the reverse code of the address of the record goes to the second inputs of the counter 61 words.

Thus, in the read address counter 41, the address of the first word intended for the first direction (in this case 00 ... 0) will be fixed, and in the counter 61 words the number of words among which information 1-direction can appear (in this case 11, .. 1).

The signal from the output of the delay element 131 (the delay time is chosen sufficient to store information in the write address counters and word counters, but shorter than the signal on the input of the write address counter) is fed to the input of the read address formation control trigger 101 and converts it to the zero state. Low level signal with

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five

0

five

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the output of the trigger 101 is fed to the first input of the additional element I 111. Thus, the recording of the information of the write address counter 3 into the write address counter and the word counter when recording the next (not first) word for the 1st direction is excluded. On the falling edge of the signal arriving at its entrance, the counter 3 of the write address increases its content by one. The next word is recorded at the new address.

Recording information can be given either in separate words or as a group of words for different directions. For example, for the 1st direction there are ten words .-, a subgroup, and then the word for the k-ro direction. In accordance with the code and the control signal, a high level signal is generated at the first output of the decoder 9k, which is fed to the second input of the additional element AND Ilk, the first input of which contains a high level signal from the output of the 1 Ok control triggering the formation of the read address. The high level signal from the output of the additional element And Ilk is fed to the input of the delay element 13k and the control inputs of the I2k element I block, where it allows the reception of information from the output of the counter 3 write addresses. When a signal arrives at the first control input 15 of the device, a high level signal is generated at the first output of the priority setting unit 5, which enters the input of the write address counter 3 and allows its contents to be transferred to the address input of drive 1 and information inputs of the 12 elements And, Word is recorded at this address. The address code of the record of the first word of the k-ro direction from the outputs of the 12k block of elements And is fed to the second input1 1 of the 4k counter of the address of the account. Washout and block inputs 14 elements are NOT. From the outputs of the block 14k elements NOT the reverse address code of the entry goes to the second inputs of the 6k word counter.

Thus, in the read address counter 4k, the address of the first word intended for the k-ro direction (in this case 0. ,, 01010) will be fixed, and in the 6k-counter, the number of words, including

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there may be k-ro direction information (in this case 1 ... 10101 Among previously. k-ro direction words recorded before the first word of the k-ro direction can not be) The signal from the output of the delay element 13k is fed to the trigger input 10k controls the formation of the read address and translates it to the zero state. The low level signal from the output of the trigger 10 is fed to the first input of the additional element I 1 Ik. Thus, the information of the 3.address address is written to the record address counter and the word counter when zap B next word k-ro direction. The further operation of the device when recording to HDD inforatsii similar consideration.

During the recording, the addresses of the first words are recorded in the 4.17t4t counters, and in the 6.1-6t counters - the number of words, information of the corresponding directions can be found within the limits of the code.

As soon as the value of the counters 6 becomes non-zero, the enable signals from their outputs arrive at the second inputs of the corresponding elements AND 7 - the presence in the memory 1 of the information for the corresponding directions is confirmed. When requests are received at the inputs of the 17 requests, the corresponding triggers 8 are transferred to the single state and the high level signals from their outputs go to the third inputs of the corresponding elements AND 7.

When a signal appears at the second control input 16 of the device (it arrives at the first inputs of the AND 7.1-7t elements), the high level signals from the outputs of the And 7 elements, corresponding to the directions for issuing information from which the request came, and KOTOpbix has information in the storage device arrive at the corresponding inputs of the block 5. set the priority of calls. The priority setting unit 5 selects from the incoming signals the highest priority (the most priority direction) and generates a signal at the corresponding output.

For example, the k-e direction is the highest priority. C signal

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One of the outputs of block 5, specifying the priority of calls, enters the first inputs of the 6k word counters and 4k read address counters and the input of the decoder 9k. This signal is performed by connecting a 4k counter to the address inputs of accumulator 1 and reading the first word of the k-ro information. The read word from the output of accumulator 1 is fed to the first inputs of the registers 2.1-2t, and the code of the word - to the inputs of the decoders 9.1-9t. In the presence of a signal from the corresponding output of block 5, setting the priority of calls, the decoder 9k generates a signal at the second output. The signal from the second output of the decoder 9k is fed to the second inputs of the register 2k and the trigger 8k. The trigger 8k is switched to the zero state. It is allowed to receive a word in register 2k (information in the k-th direction). On the falling edge of the signal arriving at the first inputs, the read address counter 4k increases, and the 6k counter of the readout counter reduces its content to the receiver. . Thus, a single exchange with the highest priority direction, the formation of the next address to the drive and the removal of the request are made. Prior to the next request, the k-ro direction has the opportunity to arrange a one-time exchange with the next priority direction. Upon receipt of the next request of the k-ro direction, with the appearance of the next signal at the second 16 control inputs of the device, the search for the next word of the k-direction information begins. If the information is recorded as a group of words, the next word is read in the same way as the first is read.

If the information is recorded as separate words for different directions, it may turn out that the next word read does not belong to the k-th direction. In this case, in this cycle, at the second output of the decoder 9k, the read signal is not formed, the word in the register 2k is not accepted and the trigger 8k is not transferred to the zero state. The content of the read address counter 4k is increased, and the content of the word counter 6k is reduced by one. In the next cycle, the query x-r6 directions remains the highest priority and the search continues - the next word of information is read. The reading is performed until the word for the k-ro direction is read or the contents of the 6k word counter become zero, which means No k-ro information is available in drive 1. When the counter 6 is in zero, the signal from its output closes the AND 7k element and blocks the ability to service requests for the k-ro direction.

The proposed device may issue any sets of information words to each of the directions as they receive requests for information. At the same time, to service one of the directions, it is not necessary to view the entire volume of the accumulator — the search for the necessary information is carried out starting from the address of the first word of the corresponding direction.

F

the invention

about rmu l and

Buffer memory containing a drive, information outputs of which are connected to the information inputs of registers, and address storage - to the outputs of the write address counter and read address counters, word counters, access control triggers, And elements and access priority setting block, whose address output is connected with the input of the write address counter, the information outputs of the block

addressing priorities are connected to information inputs of readout address counters and word counters; the control input of the priority priority block is the first control input of the device; the information inputs of the priority priority block are connected to the outputs of the AND elements, the first inputs

Compiled by V.Fokin Editor A. Kozoriz Tehred I.Popovich

4051/50 Circulation 589

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Rauschska nab, 4/5

Correct Subscribe

Production and printing company, Uzhgorod, st. Project, 4

ten

thirty

40

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which are combined and are the second control input of the device, the second inputs of the elements I are connected to the outputs of the corresponding word counters, the third inputs are connected to the outputs of the corresponding access control triggers, the installation inputs of which are the inputs of the device outputs of registers, characterized in that, in order to increase the speed of the device,

15 decoders trigger the formation of the address of the readout, additional elements AND, blocks of elements AND, delay elements, blocks, elements NOT, the outputs of which are connected to the counting inputs of the corresponding counters, words, and inputs to the counting inputs of the corresponding readout address counters blocks of elements And,

25 the first inputs of which are combined and connected to the output of the write address counter, and the second inputs with the outputs of the corresponding additional elements AND and the inputs of the corresponding delay elements, the outputs of which are connected to the inputs of the corresponding readout address control triggers, the outputs of which are connected to the first inputs of the corresponding additional elements , And, the second inputs of which are connected to the first control outputs of the respective decoders, the second control outputs of which are connected to the inputs reset the corresponding triggers and control inputs of registers, the first information inputs of the decoders are connected to the information

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on the secondary outputs of the J power, the second information inputs to the first control input of the device, and the third information inputs to the information outputs of the unit for specifying the priority of calls.

Proofreader S. Cherni Subscription

Claims (1)

Claim A buffer storage device containing a drive, the information outputs of which are connected to the information inputs of the registers, and the address outputs are connected to the outputs of the write address counter and read address counters, word counts, access signal control triggers,. element ^: contacts And the priority setting block, the address output of which is connected to the input of the recording address counter, the information outputs of the address priority setting block 40 are connected ¹ to the information inputs of the reading address counters and word counts, the control input of the priority setting block is the ₄₅ first control input devices, information inputs of the unit for setting priorities for calls are connected to the outputs of AND elements, the first inputs