SU1213502A1 - Buffer storage - Google Patents

Description

Ш1Уфраторы, groups of elements And from the first to the fourth, third and fourth. the OR elements, registers and the second group of OR elements, and the outputs of the second decoder are connected to one of the inputs of the AND elements of the first group, the outputs of which are connected to the inputs of the third OR element and with one of the inputs of the AND elements of the second group, the outputs of which are connected to one of the I9 inputs. registers, the outputs of the third decoder are connected to ONE ne of the inputs of the elements AND the third group, the outputs of which are connected to

The invention relates to computing, in particular, to storage devices.

The purpose of the invention is to increase the speed of the device.

Figs, 1 and 2 depict structural schemes of the buffer storage device and storage device, respectively.

The device (FIG. 1) contains the first trigger 1, the first element OR 2, the first counter 3, the first 4 and second 5 elements AND, the first 6 and second 7 drives, the second counter 8, the first decoder 9, the second element OR 1.0, the third counter 11, the second trigger 12, the third 13 and the fourth 14 elements AND, the first group of elements OR 15.

Drive (figure 2) 6 (7) contains the second decoder 16, the first group of elements And 17, the second group of elements And 18, the third element OR 19, the registers 20, the third section 21, the third group of elements And 22, the fourth group of elements And 23 , the fourth element OR 24, the second group of elements OR 25.

In addition, the device contains the first 26, second 27 and third 28 inputs, the first 29, the second 30 and the third 31 outputs, and the storage device contains the first 32, second 33 inputs, input group 34 ,. group of outputs 35, third 36, four of the fourth element OR, and with one of the inputs of elements AND of the fourth group, the other inputs of which are connected to the outputs of registers, and the outputs to the inputs of the elements of OR of the second group, whose outputs are one of the outputs of the accumulator, the other . Their outputs are the outputs of the third and fourth OR elements, and the inputs are the inputs of the second and third decoders and other inputs of registers and AND elements of the first, second and third groups.

There are 37 inputs, the first 38, the second 39 and the third 40 outputs, and it also has the fourth input 41.

Buffer storage device operates as follows.

Before the device starts operating, a single signal is sent to its input 41, which zeroes out all elements of the registers 20, drives 6 and 7, triggers I and 12. The left decoder 9 decrypts the zero state of counter 8 and generates a signal at output 30 of the device. are free, and from the device output 31, the signal level is zero. Signal Stores free prohibits the reading of information from the device. Zero signal level Zan then allows the recording of information in the device.

In the recording mode, the input 26 of the device receives information. Each word of information is accompanied by a signal Record, input to the device input 27. When writing the first word 1 from the inverse output of the trigger 1, the signal input is enabled. Write through. the first element 4 at input 33 of accumulator 6. After that, from the address 3 to the entrance 32 of accumulator 6, the i-record (rf "O, I -1, where I is the number of registers 20) is registered 20 drive 6. Soder, 3

Counter 3 presses are in the range from O to and -1.

When writing to drive 6, the recording address received at its input 32 is decrypted by decoder 16, Next 1 from the j-th output of the decoder 16, together with the signal Recording from input 33 of drive 6, goes to j-th And 17. A single signal from the output This element allows writing through the Jth element AND 18 words to the corresponding register 20. A single signal from the output of the J element of the AND 17 is a sign that an entry has been made to the corresponding p-master 20. This one. the signal arrives at the j-th input of the element OR 19, at the output of which the signal is written. The latter, from output 39 of accumulator 6, through the OR element 2 enters the counting input of trigger 1 and the summing input of counter 8. As a result, the state of trigger 1 is switched to the opposite, and the contents of counter 8 are increased by unit. After the first word is written to the device, the direct output of trigger 1 will be 1, and the inverse will be O. When the second word of information arrives, a single signal from the direct output of trigger 1, entering the input of the And 5 element, allows the signal to be received. to the input of the accumulator 7, after which a record is written in the j-th register 20 of the accumulator 7. When recording the second word in the device, j for the second accumulator is zero. The process of writing information to the second drive 7 is similar to writing to the first drive 6. After the word is written to the second drive 7, a signal is written from its output. The latter arrives at the counting input of the counter 3 and u.elichivaet its contents by one. In addition, the Cash Recorded through the OR element 2 enters the counting input of trigger 1 and the summing input of counter 8. As a result, the state of trigger 1 is switched to the opposite, and the contents of counter 8 are increased by one. The third word is recorded in the same way as the first word, with the only difference that the first word is written to the zero register 20 of the first accumulator.

five

3502

l 6, and the third - in the first register of this drive. The fourth word is written to the first register 20 of the second accumulator 7, and so on.

5 The recording process continues until the stream of incoming information is examined or the 6 and 7 accumulators are filled. 6) In the latter case, the contents of the counter,

 ka 8 is 2n-1, i.e. its maximum value. Such content is decrypted by the decoder 9, and from the output of this decoder, through the output 31 of the device, a signal Zan -

5 that prohibits the recording of information into the device.

The operation of the device in the reading mode is possible only if there is information in the accumulators, i.e. The content of meter 8 is not zero. In this case, from the output of the decoder 9 through the input 32 of the device, the signal level is zero. The accumulators are free, which allows reading information from the device. In the read mode, the input 28 of the device receives a request to read information — the Read signal. When reading the first

0 va.information I from the inverted Output of the trigger 12 is fed to the input element And 13 and allows receipt of the signal Read to the input 36 of the drive 6. After that, the address,

5 arriving from counter II to input 37 of accumulator 6, reading from j-th register 20 of accumulator 6 occurs. The contents of counter 11 lie in the range from O to I-1.

0 When reading from accumulator 6, the reading address is decrypted by decoder 2. Then it is equal to zero from the j-th (when reading the first word j) output of the decoder 21 together with the signal Read, -.

5 arriving from the input 36 of the accumulator 6., arrives at the jth element AND 22. A single signal from the output of this element permits reading through words AND 23 of the word from the jth register 20.

0 Then this word is transmitted to outputs 35 of accumulator 6 through elements SH-25, and from it through elements OR 15 to output 29 of the device. A single signal from the output of the j-th element And 22 V5 is indicated by a sign that the reading from the j-th register 20 has occurred. This signal, arriving at the j-th input of the element OR 24, forms on its

output signal read. The last one from the first output 38 of the accumulator b through the element OR 10 is fed to the counting input of trigger 12 and the subtracting input of counter 8. As a result, the state of trigger 12 is switched to the opposite, and the contents of counter 8 are reduced by one. After reading the first word from the device, at the forward output of the trigger 12 will be 1, and at the inverse, O. When the second word arrives at the readout, a single signal from the direct output of the trigger 12, entering the input of the And 14 element, allows the signal to be read. 7, after which the readout from the j-th register 20 of accumulator 7 occurs. When the second word of device j is read, for accumulator 7, it is zero. The process of information from accumulator 7 is similar to reading from accumulator 6. After reading the second word from accumulator 7, a Read signal is output from its output. The latter enters the counting input of the counter II and increases its contents by one. In addition, the signal Read through the element OR 10 enters the counting input of the trigger 12 and the subtracting input of the counter a 8, as a result, the state of the trigger 12 switches to the opposite, and the contents

counter 8 is decremented by one. Reading the third word is exactly the same as reading on the first request, with the only difference that the first word was read by the zero register 20 of drive b, and the third one from the first register 20. Accordingly, the reading of the first

the words will be from the zero register 20 of accumulator 7, and the fourth from the first register 20.

Thus, for odd requests to read words, they are read from register 20 of accumulator b, and for even requests from read-from. bodies 7. The reading process continues until no more read requests are received.

or until all information is read from drives 6 and 7. In the latter case, the contents of counter 8 are zero. The zero state of this counter is decrypted by the decoders.

9 and generates a signal at the output 30 of the device. The accumulators are free. The latter prohibits the reading of information from the device.

Thus, the presence of separate counters 3 and 11 dL of the write address and the read address, respectively, and counter 8 for counting the number of words forma and stored in the device, allows for simultaneous reading and reading.

Schaat Order 783/59 544 Podds ое sh «a ShSh, Uzhgorod ul. Project, 4

Claims (2)

1. Buffer storage device containing the first, second and third counters, the first and second drives, the first and second elements OR, the first decoder, the output of the first counter connected to the first input of the first drive, the output of the second counter connected to the input of the first decoder, the output of the first of the OR element is connected to the summing input of the second counter, the output of the second OR element is connected to the subtracting input of the second counter, characterized in that, in order to increase the speed of the device, the first and second are introduced into it flip-flops, elements of IS first pr fourth, the first group of AND elements, and the group of drive inputs is the first input of the device, the first inputs of the first and second elements AND are the second input of the device, the third input of which is the first inputs of the third and fourth elements AND, the first outputs of the drives are connected with the inputs of the first OR element, the first output of the second drive is connected to the counting input of the first counter, the output of the first OR element is connected to the counting input of the first trigger, the inverse output of which connected to the second input of the first element And, the output of which is connected to the second input of the first drive, the direct output of the first trigger is connected to the second input of the second element And, the output of which is connected to the second input of the second drive, the output of the first counter is connected to the first input of the second drive, second outputs drives are connected to the inputs of the second OR element, the second output of the second drive is connected to the counting input of the third counter, the output of the second OR is connected to the counting input of the second trigger, inverse output q the second trigger is connected to the second input of the third element, the output of which is connected to the third input of the first drive, the direct output of the second trigger is connected to the second input of the fourth element And, the output of which is connected to the third input of the second drive, the output of the third counter is connected to the fourth inputs of the drives, groups drive outputs are connected to the inputs of the OR elements of the first group, the outputs of which are the first output of the device, the second and third outputs of which are the outputs of the first decoder, four the fourth output are the setup inputs of the trigger counters and the fifth inputs of the drives. 2. The device according to claim 1, wherein each drive contains a second and third decryptors, groups of AND elements from the first to fourth, third and fourth OR elements, registers and a second group of OR elements, the outputs of the second decoder connected to one of the inputs of the AND elements of the first group, the outputs of which are connected to the inputs of the third OR element and to one of the inputs of the elements of the second group, the outputs of which are connected to one of the inputs of the registers, the outputs of the third decoder are connected to one * of the inputs of the elements AND the third gr ppy whose outputs are connected to inputs of a fourth OR gate with ^one input of one of AND gates of the fourth group, the other inputs of which are connected to the outputs of the registers and the outputs - to the inputs of the OR elements of the second group, the outputs of which are one of the storage outputs dru-. the anthem whose outputs are the outputs of the third and fourth OR elements, and the inputs are the inputs of the second and third decoders and other inputs of the registers and elements of the first, second and third groups.