SU1183975A1 - Interface for likning computer devices operating with different speeds - Google Patents

Abstract

A DEVICE FOR PAIRING MULTI-SPEED COMPUTATIONAL DEVICES, containing the first trigger, the first and second delay elements, the memory block, the reversible counter, the zero decoder, the read and write counters, two groups of elements AND, a group of elements OR whose outputs are connected to the address input of the memory block , and the first and second inputs of the elements OR of the group are connected respectively to the outputs of the elements of the first and second groups, the first inputs of the elements of the first group are connected to the outputs of the corresponding bits of the write counter, The first inputs of the elements of the first group are interconnected and connected to the input of the first delay element, the counting input of the record counter and the summing input of the reversible counter, the subtractive input of which is connected to the counting input of the read counter, with the input of the second delay element and , the output of the reversible counter is connected to the input of the decoder zero, and the read input of the device is connected to the first input of the first trigger, the outputs of the first and second delay elements are connected to In correspondence with the write and read inputs of the memory block, the output of which is the information output of the device, the output of the read counter is connected to the second inputs of elements AND of the second group, characterized in that, in order to expand the scope of application, a register is entered into the device, the second and third triggers , two elements NOT, the third and fourth elements. delay and the element And, the first and second inputs of which are connected respectively to the output of the decoder zero and VYSP the course of the first trigger, the second input of which is connected to the output t of the delay element, whose input is connected to the output of the second delay delay element, and the device's recording input is connected to the first input of the second trigger and to the gate input of the pe0000 Tuner, whose information input is the information input CO of the device, and the output of the register is connected to J It is connected to the information input of the paSp mA block, the output of the AND element is connected to the first input of the third trigger, the second input of which is connected to the output of the second trigger, and the first and second outputs of the third trigger are connected respectively to in the strokes of the first and second elements NOT, the outputs of which are connected to the inputs of the second and first delay elements, the output of the first delay element is connected to the input of the fourth delay element, whose rise is connected to the second input of the second trigger.

Description

The invention relates to computational and information-measuring technology and can be used to organize the exchange of information between devices operating at different speeds. The aim of the invention is to expand the field of application of the device. The drawing shows the structures on the scheme of the proposed device. The device contains elements 1 of group memory, elements AND 2 groups second delay element 3, read counter 4, reversible, counter 5, first trigger 6, first delay element 7, write counter 8, decoder 9 zero, elements 10 AND of the second group, AND elements 11 of the first group; elements OR 12 groups controlling the inputs 13 of the record and inputs 14 of the readout of the device; information inputs 15 and outputs 16 of the device; memory block 17 with the first 18, second 19 control and address 20 inputs; second trigger 21 , register 22, element And 23, fourth 24 and third 25 delay elements, the third trigger 26, performed on the elements 27 and 28 AND-NOT, the first 29 and second 30 elements NOT. The device operates as follows. In the initial state, the counters 8 and 4, the reversible counter 5, the triggers 6 and 21 are cleared, the potential corresponding to O is found at the address input 20 of the memory block 17, and the locking potential is output at the decoder 9. When a parallel code arrives at the input 15, a signal arrives at the input 13, which enters the code from the input 15 into the register 22 and sets the trigger 21 to one state, meaning a request to record information in the device memory 17. A write request with a high potential arrives at the second input of trigger 26, and if at that moment there is no read request at the first input of this trigger, then a low potential is established at its second output and a write signal at which the information is rewritten from register 22 to memory block 17 at zero address. The address code that is being recorded is inputted to the input 20 of the memory block 17 from the output of the counter 8 through the elements 11. The length of the recording signal at the input 19 of the block 17 is determined by the delay element 24. By resetting the write signal, the writing of the code in the memory block 17 is completed, the contents of the counter 8 and the reversible counter 5 are increased by one. This completes the write request service cycle. When the next code arrives at input 15 and the signal at input 13, the service cycle of the write request is repeated. When a read signal is applied to the input 14, the trigger 6 is set to one state, meaning a request to read information from the device memory 17. A read request with a resolving potential at the first input of element 23 from the output of the decoder 9 zero enters through this element AND to the first input of trigger 26, and if by this time there is no write request at the second input of this trigger, low potential, and the output element 39 is NOT a read signal. This signal with the delay provided by the delay element 3 is fed to the input 18 of the memory block 17, permitting the reading of information and the output of a code to the output 16 of this block. Moreover, the code of the first address (zero), which is read, is fed from the output of counter 4 through elements 10 AND of the group. The duration of the read signal at input 18 of block 17 is determined by delay element 25. By resetting the read signal, the reading from the memory block is completed, the contents of counter 4 are increased, and the reversible counter 5 is reduced by one. This completes the read request service cycle. When the next read signal arrives at device 14, the read request service cycle is repeated. When reading all the information from the memory block, the content of the reversible counter becomes equal to zero, as a result of which the decoder 9 zero forms a signal that blocks

I element 23I. A read request received after this into the device is not served, but is stored in trigger 6.

After writing at least one code, the lock is released and the service for a previously received read request is allowed.

If the read signal at the device input 14 arrives during the write request service, the read request signal is disabled until the write request service is terminated, i.e. before resetting trigger 21. After resetting trigger 21, the read request service cycle begins. Similarly, if the write signal to the device input 13 enters during the read request service, then the write request service will begin after the end of the read request service, i.e. after resetting the trigger 6.

With simultaneous recording and reading signals, trigger 26 is set to one of the two sockets. Let, for example, this be a state when the potential of

a logical zero output from element 30 is NOT the service potential of the write request. Upon completion of the service cycle of the write request, trigger 21 will be set to the zero state, thereby permitting the execution of the service cycle of the read request. At the end of the service cycle of the request, the trigger 6 is also set to the zero state. This completes the service procedure for simultaneously entering and reading requests to the device.

Thus, the proposed device receives and distributes information without distortion at any time position of the write and read signals at the device input relative to each other, including when they coincide. The normal operation of the device is not disturbed even when an attempt is made to read from the device when there is no information in it. This also increases the functional reliability of the device for pairing with a slight complication of the design.

Claims (1)

DEVICE FOR MATCHING OF DIFFERENT COMPUTER DEVICES, containing the first trigger, the first and second delay elements, a memory unit, a reversible counter, a zero decoder, counters for writing and reading, two groups of AND elements, a group of OR elements, the outputs of which are connected to the address input of the memory unit, and the first and second inputs of the elements OR groups are connected respectively to the outputs of the elements AND of the first and second groups, the first inputs of the elements AND of the first group are connected to the outputs of the corresponding bits of the recording counter, the second inputs The elements of the And elements of the first group are interconnected and connected to the input of the first delay element, the counting input of the write counter and the summing input of the reverse counter, the subtracting input of which is connected to the counting input of the read counter, with the input of the second delay element and with the first inputs of the And elements of the second group, the output of the reversible counter is connected to the input of the zero decoder, and the read input of the device is connected to the first input of the first trigger, the outputs of the first and second delay elements are connected respectively to The write and read odes of the memory block, the output of which is the information output of the device, the output of the read counter is connected to the second inputs of the elements of the second group, which requires that, in order to expand the scope of application, a register is entered into the device, the second and the third triggers, two elements NOT, the third and fourth elements. delays and the element And, the first and second inputs of which are connected respectively to the output of the zero decoder and the output of the first trigger, the second input of which is connected to the output of the third element LCD, the input of which is connected to the output of the second delay element, and the recording input of the device is connected to the first input of the second trigger and to the gating input of the register, the information input of which is the information input of the device, and the register output is connected to the information input of the memory block, the output of the And element is connected to. the first input of the third trigger, the second input of which is connected to the output of the second trigger, and the first and second outputs of the third trigger are connected respectively to the inputs of the first and second elements NOT, the outputs of which are connected to the inputs of the second and first delay elements, the output of the first delay element is connected to the input of the fourth delay element, the output of which is connected to the second input of the second trigger. SU, „. 1183975