SU1238091A1 - Information output device - Google Patents

Abstract

This invention relates to the field of computing. The aim of the invention is to increase the speed by recording an image array in a memory block by simultaneously recording several image points located at different addresses. The goal is achieved by introducing a group of memory blocks and switches into the device. 3 il.

Description

I

The invention relates to computing technology, is intended for outputting information from a computer, and can be used in design and construction automation systems, in automated data processing, in dialog systems.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows the scheme of the proposed device; in fig. 2 is a block diagram of the control; FIG. 3 - time diagram.

In the figures, the following symbols are accepted: memory block 1, television indicator 2j converter 3 codes; control unit 4; synchronization unit 5; switch 6; the first group of elements And 7, the first register 8; second register 9; the decoder 10, the first trigger 11, p "pvj and the second elements And 12 and 13, the second and third groups of elements And 14 and 15; the second and third triggers 16 and 17: the fourth group of elements And 18; third element and 19; group of memory blocks 20, switch group 21.

The device works as follows.

The synchronization unit 5 generates pulses, corresponding to the required screen rasterization of the television indicator 2, and controls the development of the latter. The pulses arrive at the control unit 4, making it temporarily tied to the television clock signal.

The memory block 1 and the group of memory blocks 20 form the P one-bit rulers. Switch 6 and a group of switches 21 consist of both switches and provide connection of their independent address from the device inputs to the corresponding memory block. The control unit 4, under the action of the information signals D ;, supplied from the device inputs and control signals from the device inputs, generates the necessary pulse sequence for operation of memory blocks 1 and 20, switches 6 and 21, and code converter 3. In the information reading mode, the signals from the outputs of the synchronization unit 5 through the switch 6 and the group of switches 21 are connected to the memory block 1 and the group of memory blocks 20, and the bits VI3 of them are read simultaneously 80912

Variable from each block to one address. The read-out of the blocks of the P-bit word enters the converter 3, where it converts to a television levy video signal, which, together with the sync pulses from the synchronization unit 5, goes to the TVHRfi indicator 2.

When recording information on inputs

0 devices are respectively. (1 addresses A, n bits of information signs and control signals, under the influence of which the control block 4 switches the switches

5 in such a way that the corresponding addresses arrive at the inputs of the corresponding blocks 1 and 20 of the memory, and the corresponding information signs D {. At the same time, a time diagram of the recording cycle is formed, using which information attributes DJ (O or 1) are recorded into the corresponding memory blocks at addresses A 5 (i 1, n). The selection of the memory blocks to which the recording is to be made is made using the and-bit code recorded from the computer to register 8 via the input buses of the first register 8. To allocate the allowed lines, a group of 7 elements AND is used, the first inputs of which are received signals from the outputs, register 8, and to the second inputs combined between

5 is a recording signal from control unit 4. .

The pulse distributor 4 operates as follows. In the mode of reading information from memory blocks, it

 generates a timing diagram of the read cycle and controls the operation of converter 3. Signals of the counting cycle time diagram are generated at the outputs of the bits of the second register 9, which during the read cycle activates bit 1, and at the end of the cycle it is reset to the zero state of the signals from the decoder 10, which generates a time sequence of pulses over the read cycle. With the same end-of-cycle signal, the first trigger 11 is transferred, which determines which

The 55 register and multiplexer of the converter 3 receive recording signals from the outputs of the first 12 and second 13 elements And and the control signals of the multiplexers from the outputs of the second 14 and third 15 groups of elements I.

The timing diagram of the information recording mode is shown in FIG. 3. At the write request signal (Diag.2), the second trigger 16 is set to the logical 1 state (Diag.4). The third trigger 17, under the control of the signal from the decoder 10 (diagram 3), allocates the next cycle of accessing the group of memory blocks 1 (diagram 5) and clears the second trigger 16. The signal of the loop separation allows the information (diagram 6) to pass through the fourth group elements 18 to the information inputs of the gr. upp of memory blocks 1 (diagram 7) and passage of the recording strobe (diagram 8) through the third element AND 1 to the inputs of the group of elements AND 7 (diagram, 9), performed a write cycle. information in memory blocks.

In this way; The use of the invention allows to increase the speed of the device by independently recording information on each point of the raster array.

Claims (1)

Invention Formula A device for outputting information containing a memory unit, a switch, a synchronization unit, a code converter, a television indicator, the first output of the synchronization unit is connected to the synchronous input of the television indicator, the output of the memory unit is connected to one input of the code converter, the output of which is connected to the information converter. the television indicator input, the second and third outputs of the synchronization unit are connected to the control inputs of the switch, the information inputs of which are the address inputs of the device, and the output port Inen with the address input of the memory unit, characterized in that, in order to increase the speed of the device, a group of switches, a group of memory blocks, a first register, a first group of elements And and a control unit containing the second register, a decoder, with the first to the third triggers, the first to the third elements And, from the second ps the fourth group of elements And, the fourth output of the synchronization unit is connected to the synchronous input of the second register 5 ff 15 20 25 s r p r five and with the first input of the deptfrarator, the fifth output - with the second input of the decoder, with the first inputs of the elements of the second and third groups, the second inputs of which are connected to the outputs of the first trigger, which are connected to the first inputs of the first and second elements And, the second inputs of which are connected to the first output of the decoder, the second output of which is connected to the input of the first trigger and to the reset input of the second register, whose data input is a bus unit of the device, the third output of the decoder is connected to the same setup input the third trigger, another setup input of which is connected to the output of the second trigger, one installation input of which is connected to the inverting output of the third trigger, the non-inverting output of which is connected to the first inputs of the third element I, elements of the third group and to the building inputs of the switch and switches of the group, the other input of the second trigger setup is the control input of the device, the second inputs of the elements of the fourth group are the information inputs of the device, and the outputs are connected to the information To the functional inputs of the memory block and the memory blocks of the group, the read-write inputs of which are connected to the first output of the second register, the second output of which is connected to the second input of the third element And, the output of which is connected to the first inputs of the elements of the first rpjm-type, the second inputs of which are connected with the outputs of the first register whose inputs are the code inputs of the device, and the outputs are connected to the building inputs of the memory block and the memory blocks of the group, respectively, the outputs of the first and second And elements and the outputs of the And second and third elements Network groups are connected to the control inputs of the code converter, the information inputs of the group switches are the corresponding address inputs of the device, the control inputs are connected to the second and third outputs of the synchronization block, and the outputs are connected to the address inputs of the group memory blocks whose outputs are connected. to the corresponding inputs of the code converter.