SU1287237A1 - Buffer storage - Google Patents

Abstract

The invention can be used as a buffer memory of the systems for controlling the functioning of automation and computer facilities. The purpose of the invention is to extend the functionality by introducing into the device containing a memory block, a decrypter of write signals, a read signal shaper, a second forwarder of read signals, a counter, two registers, an NL element, a synchronization unit, and two: AND-OR elements. This will allow one to organize once: smart modes of reading information from a memory block at the expense of cyclic reproduction of information. 5 il.

Description

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The invention relates to computing and can be used as a buffer storage device for systems controlling the operation of computer equipment and automation.

The purpose of the invention is to expand the functionality of the device by cyclically reproducing information.

FIG. 1 shows a block diagram of a buffer storage device; in fig. 2 is a block diagram of a memory unit; in fig. 3 is a block diagram of the first reading signal generator; in fig. 4 is a block diagram of a second reading signal generator; in fig. 5 - block diagram block diagram.

The buffer memory contains a memory block 1 with information inputs 2 and outputs 3, a decoder 4 write signals, address inputs 5, first control input 6, first read signal generator 7, second read signal generator .8, first register 9, second register 10 , the first decoder 11, the second decoder 12, the third decoder 13, the counter 14, the first element AND-OR 15, .. the second element AND-OR 16, the element 18, the synchronization unit 18, the second control input 19 and the control outputs 20-22 .

Memory block 1 contains registers 23 and AND 24 elements.

The read signal generator 7 comprises a counter 25 and a decoder 26, and the read signal generator 8 a counter 27 and a decoder 28.

The synchronization unit 1B contains the driver 29, the elements OR 30-34, the delay elements 35-39, the elements NOT 40-43, the trigger 44, the elements AND 45-52 and the switch 53. The synchronization unit 18 can be made in the form of a firmware.

The device works as follows.

The device can operate in the data recording mode and in the data reading mode.

In the data recording mode, the information inputs: 2 receive data recorded in memory block 1, accompanied by an address code on address inputs 5 and a signal at control input 6. The signal at the input 6 control

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arrives at the gating input of the depfrrator 4, the output of which records data from the busses 2 to the register 23, whose address code is present at the inputs 5 of the device. Writing data to other registers 23 of memory block 1 is similar.

The memory unit 1 is functionally divided into two fields: a field for storing command information and a field for storing data that accompany the command information. Each field consists of a set of registers with 1x consecutively increasing addresses. Thus, when using the proposed device for testing devices for controlling accumulators on a magnetic tape, command codes READ, SEE, STEP TO FORWARD, RECORD MARKER OF ZONE GROUP, etc. can be recorded in the command information field, and codes entered in the data field data accompanying some of the commands, such as the RECORD command. The number of information words in the data field is significantly less than the number of information words in the data block accompanying the command information. Thus, in the described example with testing tape drive control devices, there can be only two information words in the data field, each with zero and one bits, and the length L of the data block can be different (16, 32, ..., 1024 words) and significant transcending L 2.

The data block length codes and the number of command words used in the current test cycle, along with the sign of their cyclic execution, are written to register 9. Data is written to register 9, which has its own address, is made similarly to writing to registers 23 of memory 1 . Upon completion of writing data to registers 23 and 9, the device is ready to perform a read operation.

The reading mode begins with a high level of the signal at the control input 19 of the device, which is fed to the input of the synchronization unit 18. The signal at the control input 19 is fed to the input of the shaper 29 of the synchronization unit 18, which generates a signal on the leading edge.

arriving through the OR 30 element to the setup inputs of the formers 7 and 8 and the trigger 44 of the synchronization unit 18 and through the OR 34 element to the installation input of the counter 14, setting them to the initial zero states. The signal at the output of the OR element 30 through the OR element S1 and the delay element 35 enters the gating input of the decoder 26 of the generator 7, the output signal of which reads the data from the first register 23 of the command field of the block 1 through the corresponding elements AND 24 informational outputs 3. The counter 25 modifies its contents on the falling edge of the signal at the output of the delay element 35. The leading edge of the signal at the output of the delay element 35, which is delayed on the delay element 37, writes the control word to the register 10, the specified signal arrives at the output 22 of the device as the identifier of the control word. The decoder 13 and the element OR 17 determine the need to transfer the data set for the previously read command word. If there is such a need, then the output of the element OR I7 is a high signal level, which through the element 45 of the synchronization unit 18 allows the signal from the output of the delay element 36 to pass through the element OR 33 to the gate input of the decoder 28 of the driver 8, the output of which reads information outputs 3 of the data word device from the first register 2 of the data field of memory block 1 through the corresponding AND 24 elements. The output signal of the delay element 39 is the identifier of the data word and the post falls on the control output 21 of the device. The signal delayed by the delay element 38 arrives at the inputs of elements 47 and 48, at which the condition for the end of the transmission of the data block is satisfied. The data transmitted in the block is counted by a counter 14, which changes its state according to the falling edge of the signal at the output of the element OR 33. The decoder 1I produces the corresponding states of the counter 14, which are compared with those specified on the second group of outputs of the register 9. The comparison is made on the element AND-OR 16. In

In the case of the transfer of the required volume in the data block, a high signal level is present at the output of the I-ШШ 16 element. Otherwise, the high level of the signal at the output of the NOT element 43 will allow the passage of the signal from the delay element 38 through the element AND 48 to the input of the element OR 33 and the cycle of issuing data to the information outputs 3 of the device will repeat. The data will then be read from the next in order register 23 of block 1 of the memory. At the end of the data block transmission, the high level of the signal according to the input of the And 47 element and the signal from the output of the delay element 38 through the And 47 element and the OR 34 element will reset the counter 14 to the zero state. At the same time, the signal from the And 47 element output through the OR element 32, to the second input of which the signal from the output of the delay element 36 is sent through the AND 46 element if the previous read command word did not require data transmission, goes to the inputs of AND 51 and 52, where the condition for issuing command words is checked. The counts are transmitted from command words at counter 25 of driver 7, which changes its state along the falling edge of the signal at the output of delay element 35. The signals from the outputs of the counter 25 are sent to the decoder 12, which highlights the corresponding states of the counter 25, which are then compared with those specified on the first group of outputs of the register 9. The comparison is made on the I-III cell 15. In the case of transmitting the required number of command words AND-OR 15 there is a high signal level. Otherwise, the high level of the signal at the output of the element NOT 41 will allow the passage of the signal from the output of the element OR 3 through the element AND 52 to the input of the element OR 31 and the next command word will be issued. In this case, the command word will be read out of the next order register 23 of the command field of the memory block 1. Upon completion of the transfer of the required number of command words, a high level of the signal at the input of the And 51 element will allow the signal from the output of the OR 32 element to pass through the And 49 and 50 elements, where it is checked

fulfillment of the condition of cyclic execution of the previously transmitted set of command words. Cyclic execution of a set of command words is set by a high level of the signal at the output of one of the bits of register 9. At the same time, high levels of signals at the inputs of the And 50 element (the duration of the cyclic execution of a set of command words is determined by the time of the read signals, first and second high the input 19 of the control unit allows the passage of the signal from the output of the element AND 51 through the element 50 and the input of the element OR 30, which will lead to the repetition of the issuance of a set of command words. Otherwise, in the absence of the condition of cyclic execution of command words, the high level of the signal at the output of the element NO 42 will allow the signal through the element 49 of the output from the output of the element 51, which will set the trigger 44 into the unit state, and the output 20 of the device will turn high signal level indicating a reading of the information reading mode. In loop reading mode, command word trigger 44 is not set.

the gistra, the first, second and third de encoders, the first and second AND-OR element, the counter, the IL element, and the synchronization unit, the outputs of the second t5 read signal generator are connected to other read control inputs of the memory unit, the setup inputs of the first and second forms the read signals are connected to the fifth output of the synchronization unit, the control inputs. the second form of the read signals and the counter are connected to the second output of the synchronization unit, the third output of which is connected to the control input of the first signal generator reading fishing, m and n yyhody sixth timing unit are respectively the first ring and outputs a control device eni

in one state, and the window is the seventh seventh output of the synchronization unit

The reading of the reading mode is determined by removing the high level of the signal at the control input 19 of the device.

The switch 53 is set to a position in which the transmission of signals through the element 45 is blocked in the event that the operation does not require the tracking of command words with data.

The invention makes it possible to more efficiently use hardware in the process of controlling the functioning of computer equipment.

Claims (1)

Invention Formula A buffer memory device containing a memory block whose information inputs and outputs are respectively, information inputs 50 respectively to information inputs and device outputs, a signal decoder ... a recording whose gate input is the first control input of the device, one of the inputs of the recording signal decoder is the address input of the device, the write control inputs of the memory block are connected to the outputs decoder the write signals, one of the read control inputs of the memory unit are connected to the corresponding outputs of the first read signal generator, characterized in that, in order to expand the functionality of the device by cyclically reproducing information, it contains a second driver the gistra, the first, second and third decoders, the first and second AND-OR elements, the counter, the IL element and the synchronization unit, the outputs of the second read signal generator are connected to other read control inputs of the memory unit, the setup inputs of the first and second read signal generators are connected to the first output of the synchronization unit, the control inputs of the second signal conditioner of the read signal and the counter are connected to the second output of the synchronization unit, the third output of which is connected to the control input of the first one The read signals, the fifth and sixth outputs of the sync block are the first and second control outputs of the device, respectively. the seventh output of the sync block connected to the write input of the second register and is the third control output of the device, and the first input of the synchronization unit is the second the control input of the device, the second, third, fourth and fifth inputs of the synchronization unit are connected respectively to the output of the first AND-OR element, the output of the second AND-OR element, the output of the OR element and, the output of the first register, one input of the second AND-OR element are connected to the corresponding outputs of the first decoder, the inputs of which are connected to the corresponding outputs of the counter, the other inputs of the second element AND-OR are connected to the corresponding outputs of the first register, the information inputs and outputs of which are connected I will give the device and one of the inputs of the first AND-OR element, the other inputs of which are connected to the corresponding outputs of the second decoder, the inputs of which are connected to the corresponding outputs of the first read signal generator, the write input of the first register connected to the output of the write decoder signals, the information inputs of the second register connected to the information outputs of the memory block; the outputs of the second register are connected to the corresponding lean inputs of the the decoder, the outputs of which are connected to the corresponding inputs of the OR element, and the fourth output of the synchronization unit is connected to the address input of the counter. Fi.Z From train 19 Established „0 dk} rmiro 8.7 three wagons From item srig.5