SU1368919A1 - Arrangement for converting data format in domain memory - Google Patents

Description

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The invention relates to computing technology and can be used in cases where the memory blocks of the jamming device on cylindrical magnetic domains (CMD) have a series-parallel storage structure and contain a number of defective storage registers.

The aim of the invention is to improve the reliability of the device by self-diagnosing failures.

The drawing shows a block diagram of the device.

The device is used for a group of memory blocks on the CMD 1 (with a series-parallel arrangement), the first inputs of which are connected to the read-write bus 2, and the second inputs to the first bus 3 of synchronization.

A device for converting a data format contains a random access memory block 4. Information for storing a defective register card, first counter 5, second counter 6, NOT element 7, first element AND 8, second synchronization bus 9, reading register 10, first multiplexer 11 , second element 12, third element 13, record register 14, buffer register 15, data input buses 16, fourth data transfer request element 17j, tire 18, data output bus 19, third counter 20, trigger 21, data transfer confirmation bus 22 , a group of elements And 23, the first control bus 24, a triple multiplexer 25, a group of control buses 26 and a second control bus 27.

The device works as follows.

In the write-read mode, firstly, the control field is turned on in the M memory blocks on the CMD 1, the frequency of which f is set by the clock signals on the first sync bus 3. In the recording mode (high signal level on buses 2, 24 and 27), a high signal on bus 22 transmission confirmation at the output of logic element 17 produces a data reception signal, which sends data from the controller to data input buses 16 to buffer register 15 Each period of the control field on the counter 5, a clock pulse is received via the bus 3 of the synchronization.

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specifying the next address of the random access memory block 4, storing the card of defective registers (defective register - state O, defect-free - state 1). The information from the outputs of the random access memory units 4 is fed to the inputs of the first group of multiplexer (M-1) 11, which performs parallel-serial code conversion. The multiplexer 11 is controlled by the counter 6 modulo M.

Each period of the control field after the arrival of M sync pulses of the frequency Mf via the second synchronization bus 9 via the AND element 8 to the counting input of the counter 6, the transfer signal of the unit level is transmitted through the NOT element 7 to the AND element 8 and prohibits further receipt of these sync pulses to the counter 6j by the clock pulse on the bus synchronization 3, the counter 5 6 is reset to zero.

The supply of Mf clock pulses to the sync-input -discharge buffer register 15 occurs through the And 12 element only at a single signal level at the first output of multiplexer 2 () 11, i.e. at that; if the next register of the memory block on the CMD 1 is faultless. As a result, the information from the N-bit buffer register 15 through the element And 13 is rewritten into the M-bit register 14 of the record.

If the next register is defective, the clock pulse Mf goes to the 0 N-bit buffer register 15, but goes to the M-bit register 14 of the record. As a result, O is written to the M-bit register 14, which corresponds to the skip of the defective 5 register of the memory block on the CMD 1. The information from the M-bit register 14 record goes in parallel to the inputs of the M group of memory blocks on the panel 1. .

The counter 20 modulo N counts the number of bits transmitted from the N-bit buffer register 15 to the M-bit register 14 of the record. After counting the N sync pulses Mf, the transfer output of the counter 20 generates a transfer signal, which arrives at the data transfer request trigger 21, which generates a data transfer request on the corresponding bus 18.

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From the controller, the data input buses 16 receive the next N-bit information word, which is written into the M-bit buffer key 15 on a high signal level on the data transfer confirmation bus 22; wherein the data request trigger 21 is reset to zero.

In the read mode (low signal level on buses 2 and 24, high level on bus 27), each period of the control field information from the outputs of the group of M memory blocks on the CMD 1 goes to the M-bit read register 10. From the output of the M-bit register 10 reading information is fed to the inputs of the second group of multiplexer () 11, which performs its parallel-serial conversion. From the second output of multiplexer 2 () 11, information is fed to the second of the inputs of the first group of multiplexer 25 and from its output to the serial input of the N-bit buffer register 15.

In the N-bit buffer register 15, data is received only from the defect-free registers of memory blocks on the CMD 1, since the arrival of sync pulses .Mf to the sync input of this register occurs only at a single signal level at the first

 the multiplexer output () 11, C of the outputs of the N-bit buffer register 15, after forming the N-bit information word on the data signal from the data request trigger 21, the information is fed to the data output buses 19. The reception of the information word is confirmed by a transmission confirmation signal on the bus 22.

In the first test mode (low signal on buses 2, 24 and 27), the first input of the first input group of multiplexer 25 is supplied with a defect map from the first output of the multiplexer () 11. Information from the output

Multiplexer 25 is accepted into the buffer register 15. Since the arrival of the clock pulses to the synchronous input of this register occurs only when the signal level is single at the first output of the multiplexer (M-) 11, the code FFf, j ,, generated on the signal from trigger 21 is generated in the buffer register 15 data transfer request

on tires 19 data output. The difference of the transmitted code from the FF,.,. Indicates a malfunction of the device.

In the second test mode (low signal on buses 2 and 27 and high on bus 24, code XX.- .X on control buses 26), random access memory 4 is turned off and a high level is set at the first multiplexer output. The signals from the outputs of counter 6 through the group of elements And 23 are fed to the inputs of the second group (address) of multiplexer 25. At the output of multiplexer 25, the code XX is generated. X1 is written to the buffer register 15. The difference between the output of the code transmitted to bus 19 XX..X1

Claims (1)

indicates a malfunction of the device. , Invention Formula five 0 five 0 five ABOUT five A device for converting a data format into a domain memory containing a random-access memory block, counters, the counting input of the first of which is the first synchronization input of the device, and the information outputs are connected to the corresponding address inputs of the random-access memory block, element The NOT whose input is connected to the overflow output of the second counter, the AND elements, the first input of the first of which is connected to the output of the NOT element, the second input is the second synchronization input of and the output is connected to the counting input of the second counter and the first input of the second element AND, the record register, whose information input is connected to the output of the third element AND, the synchronization input 11I with the output of the first element AND, and the outputs are the information outputs of the first group of device, the register reads, the inputs of which are the data inputs of the first group of the device, the buffer register, the information inputs of the parallel reception of which are the data inputs of the second group of the device, the synchronous input, the input of data reception and input The data transfer request of the buffer register is connected respectively to the output of the second element AND, the output of the fourth element AND, and the output of the trigger, the outputs of the buffer register are information outputs of the second group of the device, with the output of the lower bit of the buffer register connected to the first input of the third element AND, first a multiplexer, the inputs of the first group of which are connected to the corresponding outputs of the reading register, the inputs of the second group - with the corresponding outputs of the memory block with a random selection of information and, the inputs of the third group are with the corresponding outputs of the second counter, the first output of the first multiplexer is connected to the second input of the second element And the second input of the third element And, the counting input of the third counter is connected to the output of the second element And, the first and second inputs of the fourth element And are the first and second control inputs of the device, the trigger, the installation input of which is connected to the overflow output of the third counter, the reset input of the trigger is connected to the second input of the fourth And element, the installation input of the second wow counter 68919 nen With a counting input of the first counter, characterized in that, in order to increase the reliability of the device by self-diagnosis of failures, it contains a second multiplexer and a group of elements And, the first inputs of a group of elements And connected to the outputs of the second counter, the second 10 inputs are the control inputs of the device and are connected to the control input of the memory block with a random selection of information, the first and second information inputs of the second The g multiplexer is connected to the first and second outputs of the first multiplexer, respectively, and the remaining information inputs of the second multiplexer are constant inputs. 2Q devices, the first address input of the second multiplexer is the control input of the device, and the remaining address inputs of the second multiplexer are connected to the outputs of the AND elements 25 groups, and the output of the second multiplexer is connected to the input of the sequential reception of the buffer register.