SU1615725A1 - Device for monitoring running of programs - Google Patents

Abstract

The invention relates to computing and can be used in debugging programs, devices controlling the correctness of the execution of DVM programs. The aim of the invention is to simplify the device. The goal is achieved due to the fact that a device containing AND 3 and AND 9 elements, delay elements 4 and 6, counter 5, trigger 7, comparison circuit 8, OR elements 10 and 11, registers 14 and 15, introduced two groups of comparison circuits 12 and 13. 1 ill.

Description

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The invention relates to computing and can be used in program debugging devices and devices controlling the correct execution of DVM programs.

The purpose of the invention is to simplify the device.

The drawing shows a diagram of the device. The device contains the input 1 of the command reading attribute, the address input 2, the second element AND 3, the delay element 4, the counter 5, the delay element 6, the trigger 7, the comparison circuit 8, the first element AND 9, the first 10 and the second 11 elements OR, the first 12i -12n and the second 13i-13n groups of the comparison circuit, the first 14 and second 15 blocks of registers and the output 16.

The device works as follows.

In the initial state, the counter 5. was reset. The i-th register of block 14 of registers contains the code of the address of the digital computer command counter, corresponding to the first i-ro command of the linear portion of the program being monitored. In 1-1 register of block 15 of registers, the code of the address of the command counter of the digital computer is written, corresponding to the last command of the i-ro linear. Site of the controlled program. The write inputs of blocks 14 and 15 registers are not shown.

The address code of the next command from the counter of the address of the computer commands (not shown) on the input 2 of the device enters the first inputs of the comparison circuits 12i-12n and 13i-13n. At input 1 of the device, an impulse is received to read the command from the computer memory. If the address of the next command corresponds to the address of the first i-ro command of the linear section, then at the output of the i-th comparison circuit 12i, an impulse appears which, passing through the OR 10 element, sets trigger 7 to one state, as well as passing through 4 delays permits writing the code from the input 2 of the device to the input of the installation of the counter 5. The high potential from the single output of the trigger 7 opens AND elements 3 and 9. The address of the next command is fed to the input of the comparison circuit 8. The read pulse of this command from the input 1 of the device through the open element I 3 enters the counting input of the counter 5, increasing its state by one. The pulse from input 1 also enters the input of delay element 6, which delays it for the response time of element 3 and counter 5. The pulse from the output of delay element 6 arrives at input of element 9. The signal is not equal from the output of the comparison circuit 8 to the other input element And 9, and if this signal is equal to one, which corresponds to the presence of different

codes at the inputs of the comparison circuit 8, a pulse appears at the output 16 of the device. This pulse signals an error when executing the linear section of the program.

If no errors were detected during the control of the i-ro linear section, then the code of the last command of the 1st liner1 section is compared in circuit 13 by comparison with the reference code recorded in the 1st register of the register block 15, and, passing through the OR 11 element, zeroes trigger 7, thereby setting the device to its original state.

The control operation of any other J-ro linear section of the OO program is similar to the control operation of the i-ro segment.

Thus, the proposed device allows monitoring the correct execution of linear program sections.

Claims (1)

Invention Formula A device for monitoring the progress of the program, containing the first and second blocks of registers, the first and second delay elements, the comparison circuit, the first and second elements OR, the counter, the trigger, the first and second elements AND, the address input of the device connected to the first input of the comparison circuit, the output the first delay element is connected to the first input of the first element AND, the output of which is the output error of the device, the output of the first element OR is connected to the single input of the trigger, the direct output of which is connected to the first input of the second element This AND, characterized in that, for the sake of simplicity, the device contains two groups of comparison circuits, with the read input of the device being connected to the input of the first delay element and to the second input of the second And element whose output is connected to the counting input of the counter; with the first inputs of the first and second groups comparison circuits and with the information input of the counter, whose information output is connected to the second input of the comparison circuit, the inequality output of which is connected to the second input of the first element And, the output first and second register units are connected to second inputs of the comparison circuits, respectively, first and second groups, outputs of equality of each circuit comparing the first group are connected to respective inputs of the first OR member, which output is via a second delay element coupled to the counter entry input; the equality outputs of the comparison circuit of the second group are connected to the corresponding inputs of the second OR element, the output of which is connected to the zero input of a trigger, the single output of which is connected to the third input of the first element I.