SU1683019A2 - Program debugger - Google Patents

Abstract

The invention relates to digital computing and can be used when debugging programs of specialized digital computers that contain in their J / composition regular blocks of permanent memory with work programs. The purpose of the invention is to expand the functionality by providing an operational substitution of several information zones located in a fixed memory unit with information located in a random access memory unit. The device for debugging programs contains three blocks of random access memory 1, 2, 23, block 22 of permanent memory, blocks 3, 4 of comparison, elements 5 - 8 delays, elements AND 9-18, D-flip-flop 19, elements OR 20, 21, address counter 24, two-digit binary counter 25, first 26 and second 29 decoders, first 27 and second 28 registers. 1 il.

Description

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Yu

Yu

The invention relates to digital computing, can be used when debugging programs of specialized computer computers that contain regular blocks of permanent memory in their remaining work programs, and is an improvement to the device according to the author. St. No. 1198525.

The aim of the invention is to expand the functionality of the device by providing a quick substitution of several information zones located in a fixed memory block corresponding to information zones located in the RAM block.

The drawing shows an example of the implementation of the device, which depicts the second RAM block 1, the third RAM block 2, the second and first comparison blocks 3 and 4, delay elements 5-8, AND elements 9-18, D-flip-flop 19, elements OR 20 and 21, constant memory unit 22, first RAM unit 23, address counter 24, two-digit binary counter 25, first decoder 26, first register 27, second register 28, second decoder 29, device inversion 30, device address input 31, device information input 32, device clock input 33, the input 34 of the initial installation of the device, the input 35 of the installation mode of the device, the output 36 of the device.

The device works as follows.

In the initial state, in which the device is installed when the initial setup signal is applied to the input 34, information is only readable from the fixed memory unit 22 via the AND element 17 at the time of the appearance of the clock pulses fed to the input 33 of the clock pulses, therefore 36, the device displays the information located in the permanent memory unit 22. At the time of the appearance of the signal at the device input 30, a bit memory is sampled from block 1, corresponding to the lower bits of the address supplied to the address input 31 of the device. In the case of reading the zero bit from memory block 1, which is interpreted as no need to replace information zones of the fixed memory block 22 for all addresses with the specified value of k least significant bits, the passage of clock pulses is prohibited through AND 9 and resolved through AND 10. Thus, information is still being read from the block.

22 of the permanent memory at the output 36 of the device. In the case of reading a bit other than zero, from memory block 1, which is interpreted as having addresses with specified k lower-order bits in the address list of the replacement points and corresponding jump instructions located in memory block 2, it is not allowed pulses through AND 10 element and resolved through AND 9 element. Thus, after the arrival of each clock pulse, information is retrieved from the RAM memory block 2 after reading the information from the RAM block 2 This is provided by the delay elements 5, 7, the increment of the contents of the address counter 24, and the clocking of the comparison unit 3. In the case of reading from the first exit

0 block 2 of the RAM of the zero transition command, which is interpreted as the end of the list of addresses of the replacement points and the corresponding transition commands, triggers comparison block 3 and prohibits matching block 4 comparison, thus, the information is still read from block 22 constant memory output device 36, in the case of reading the transition command, other than zero, with

0, the first output of the main memory unit 2, the number read from the second output of the main memory unit 2, is interpreted as the full address of the replacement point of the information zone from the permanent memory unit 22, in this case the comparison unit 3 allows the clocking of the comparison unit 4. If the full address supplied to the input 31 of the device coincides with the number from the second output of block 2 of the operating memory, block 4

Comparison 0 generates a signal at the output, which through the element And 13 sets to 1 D-flip-flop 19, therefore, it is forbidden to read information from the block 22 of the permanent memory, passing the signal from the output

5 of the comparator unit 4 through the AND element 13, the operation of the counter 25 is permitted. When the clock pulses of the first clock pulse arrive at the input 33, the clock pulse is compared

0 passing the command of the transfer control command through the element 14 from the first output of the RAM block 2 to the device output 36 and the state of the device address input 31 on the first is remembered

5 register 27. Consequently, instead of the next program command located in the permanent memory unit 22, a control transfer command is issued to the device output 36 and the address of the replacement point is stored in the first register 27. By command

transferring control to the next cycle, the contents of the command counter are loaded onto the stack. In this cycle, the second after detecting the replacement point, the passing of the control transfer code through the AND 14 element to the device output 36 is prohibited and the state of the address input 31 in the second register 28, i.e. the value of the stack pointer of the program located in the constant memory block 22, in the third control point after detection of the displacement point, is transmitted to the address uniquely determined by the control transfer command code, the clock pulses to the counting input of the counter 25 are forbidden through the And 12 element, work is allowed the second decoder 29 and reading the information from the RAM block 23 to the device output 36 through the element I 18, In the device described, the functionality has been expanded in terms of replacing an arbitrary The number of information zones located in the constant memory block 22 corresponding to the number of information zones of the RAM block 23, which reduces the number of program debugging cycles by combining several different types of debugging operations defined by the RAM in one debug cycle. ti.

Claims (1)

The invention device for debugging programs for auth. St. M 1198525, characterized in that, in order to extend the functionality by providing a quick substitution of several information zones located in the fixed memory block with the corresponding information zones located in the RAM memory block, it contains the second and third RAM blocks , from the eighth to the tenth And elements, four delay elements, the second comparison unit, the address counter and the second OR element, and the output of the second RAM block is connected to the first input of the eighth And element and with the investment With the rs input of the ninth element And, the output of the eighth element And connected to the inputs of the first and second delay elements and with the clock course of the third block memory, the output of the first delay element is connected to the counting input of the address counter, the information output of which is connected to the address back of the third memory block, the device access input is connected to the second input of the second memory block and through the third delay element with inputs returning the constant unit and the first memory unit and the second control input of the second decoder, the output of the second delay element is connected to the clock input of the second comparison unit and after vertical element 5 delays with a direct input of the tenth element And, the output of the second comparison unit is connected to the inverse input of the tenth element And, and with the first direct input of the second OR element, the output of which is connected to 0 reset input address counter, the clock input device is connected to the second input of the eighth element And the direct input of the ninth element And the output of which is connected to the first inputs of the fourth and fifth 5 And elements, with the first control input of the second decoder, with the third input of the first element And, and with the second input of the second element And, the address input of the device is connected to the address input of the second 0 of the RAM, the input of the initial installation of the device is connected to the second direct input of the second OR element, the output of the field of the transition instruction code of the third RAM is connected 5, the third input of the fifth element I and the first information input of the second comparison unit, the second information input of which is connected to the device zero potential bus, the output of the code field 0 the address of the replacement point of the third RAM block is connected to the second information input of the first comparison block, the inverse output of the D-flip-flop is connected to the inverted input of the second element OR, the output of the tenth And element is connected to the clock; m input of the first comparison block, the mode setting input and the information input of the device is connected respectively to the recording inputs and 0 information inputs of the second and third blocks of RAM.