SU1608675A1 - Device for monitoring running of programs in computer - Google Patents

Abstract

The invention relates to computing, in particular, computer-controlled devices for monitoring the correctness of program execution. The purpose of the invention is to expand the functionality of the device due to the possibility of changing the interval of program execution. For this, the address decoder, the checkpoint register, the second delay element, the second and third AND elements, the mask register block, the counter block, the first and second comparison circuits, and the timer are entered into the known device. The device provides continuous monitoring of the execution of program branches with the number of control points limited only by the size of the counters of control points of the block of counters, algorithmic control of the correctness of transitions from the current controlled branch to the next one, control of the duration of the entire program. 1 il.

Description

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The issue is related to computer technology, in particular, to wind-driven computer devices for monitoring the correctness of program execution.

The purpose of the invention is the expansion of the functional capabilities of the device, the ability to control the execution of individual branches of the time interval program.

The drawing shows the functional scheme of the proposed device, contains a control VM 1, a decoder 2 addresses,) 3 control points, a triaxial OR 4, the first element is the AND 6 element, the first delay element 7, the third And 8 element, the second delay element 9, the counter 10, the processor 11, the mask register register 12, the first comparison circuit 13, the counter block 14, the second comparison circuit 15, the clock generator 16 and the timer 17.

The device works as follows.

The program being monitored is naturally divided into branches with sequential addressing of commands. The transition from one branch of the program to another takes place by the commands of conditional and unconditional transition, referring to a subprogram, i.e. programmatically, or if an interrupt from an external device occurs in the process of execution

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properties. Subroutines and programs for handling interruptions are also naturally divided into branches, as is the main program. At the beginning of the program execution, as a whole, the transfer command sets timer 17 to the timer 17, ravgg for the maximum program execution time. At the beginning of each program branch, the mask register of the controlled branch of block 12 of the mask registers selected by the decoder 11 sends the standard of the mask of the controlled branch — the code that identifies the controlled branch — to the corresponding counter of the control points of block 14. counters (control points) - the number of control points on the controlled branch. Since the block 12 of the mask registers and the block of 14 counters have on the bus 18 one. And the same address, the mask. . is transmitted in the higher bits of the machine word, the number of control points in the younger ones.

A checkpoint is a write command B register of 3 checkpoints. The maximum number of: control points in the branch is defined; it is done only by the size of the counter points checkpoint counter 14 counters and when these counters are N, the programmed program branch after the standard of the branch mask and the number of control points on the branch is entered into the corresponding blocks of the device each time the control point compares the current mask value of the monitored program branch with the reference stored in the current control level register. Thus, the execution of the current program branch is continuously monitored. At the end of the branch execution in the device, the procedure of controlling the passage of all control points of the branch, that is, the correctness of the transfer to the next branch, is performed. This procedure is initiated by two computer commands — a command to write to a dummy external register, which initiates the operation of comparing the remaining number of control points with O, and the next read operation from the dummy register. The last command is necessary because the enable signal is equal to

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Neither the remaining number of control points from the output of the first element I 5 simultaneously generates, through the second element 9, a signal for the reverse switching of the control level, and for a correct transition to the next controlled branch, its restoration is necessary.

When a program is interrupted from an external device by the reading command, a signal is generated from the fictitious external register And 6 to the incremental input of counter 10, its content is increased by 1 and the current mask register of the monitored branch of the mask register 12 and the counter of control points of the meter counter 14 is switched next order free register and counter. The contents of the current register of the mask of the monitored branch and the counter (checkpoints) are saved to return from the interrupt handling program, and the selected register and counter provide control at the next level. The depth of attachment of monitored, interrupt handling programs, i.e. the number of control levels is equal to the number K of the register of masks of the monitored branches of the program of the block 12 of the registers of masks and counters of the controlled points of the block of 14 counters. In the code from the processing program of the command to write to the dummy external register, the first element 5 generates a signal to the decrement input of the counter 10 (control level), its content decreases by 1, and the control level of the program branch is restored. .

In parallel with the execution of programs using the clock generator 16 and timer 17, the duration of its execution is monitored.

The device as a whole has, in comparison with the known, expanded functionality and can provide continuous monitoring of the execution of program branches with the number of control points limited only by the counter size of the block of counters (control points), the algorithmic control of the correctness of transitions from the current controlled

branches to the next, control the duration of the entire program. In the case of a wrong execution, a programmatic analysis of the causes can be made, and the nepesanynjeHa program from any point, and not just from the beginning. In addition, the advantage of the device is the ability to programmatically disable monitoring by masking interrupts from the device, which is necessary in debug modes.

F o

rmula of invention

A device for monitoring the execution of computer programs containing a clock generator. / Counter, the first element is a decoder, the first element is E. And e; OR, which differs from the fact that, in order to expand the functional capabilities of devices due to the possibility of monitoring BBI-polienn of separate branches of the program and changing the execution interval, the second delay element, the second and third And elements, address decoder, test points, two control circuits, mask register block, counter block, timer, the device information for connecting to the data of the controlled computer soy, 1 with the information inputs of the address decoder and the register m-poniHbK, the first to fifth address decoder outputs are connected to the checkpoint register entry input, the first input of the first element, And, the counter recording input, the first input of the second element, And, the sampling input of the timer, the first output of the address decoder through the first delay element is connected to the resolution input of the first comparison circuit, the first and second information inputs of which are connected respectively to the register register output

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hotspots n output of the mask register unit whose information input is the device input for connecting the controlled computer to the data source, the sample input group and the mask register block recording input are connected to the decoder output group and the output of the second element, respectively, the second input of which is combined with the second the input of the first element And is connected to the corresponding unit of the input of the device for connection to the data bus of the controlled computer, the output of the first element And through the second delay element is connected to, The incremental input of the counter, the incremental input of which is connected to the output of the third element AND, the first and second inputs of the third element AND are connected respectively to the second output of the address decoder and the corresponding input input of the device for connection to the data bus of the controlled computer, the output of the first element AND is connected with the resolution input of the second comparison circuit, the first and second information inputs of which are connected respectively to the output of the counter block and the logical zero bus of the device, the inequality outputs of the first and the second comparison circuit and the timer output are connected to the corresponding "inputs" of the OR element, the output of which is -; with the output of the device for connecting to the interrupt input of the controlled computer, the information outputs of the counter are connected to the inputs of the decoder, the outputs of which are connected to the sample inputs of the block by the counter, the decrement input and input of the record are connected respectively to the equality output of the first comparison circuit and the output of the second element I, information inputs of the counter, block counters, timer. connected to the input of the device for connection to the data bus of the controlled computer, the output of the clock generator is connected to the synchronous input of the timer.

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Claims (1)

the role points and the output of the mask register block, the information input of which is the device input for connecting to the data bus of the controlled computer, the group of sample inputs and the write input of the mask register block are connected respectively to the decoder outputs group and the output of the second AND element, the second input of which is combined with the second input of the first element And is connected to the corresponding bit of the input of the device for connecting to the data bus of a controlled computer, the output of the first element And through the second delay element is connected to by the input of the counter, the incremental input of which is connected to the output of the third element And, the first and second inputs of the third element And are connected respectively to the second output of the address decoder and the corresponding bit of the input of the device for connecting to the data bus of a controlled computer, the output of the first element And is connected to the permission input the second comparison circuit, the first and second information inputs of which are connected respectively to the output of the counter block and the logical zero bus of the device, the inequality outputs of the first and second circuits m comparison and the timer output is connected to the corresponding inputs of the OR element, the output of which is the output of the device for connecting to the interrupt input. of a controlled computer, the information outputs of the counter are connected to the inputs of the decoder, the outputs of which are connected to the sample inputs of the counter block, the decrement input and the recording input of which are connected accordingly, with the output of the equality of the first comparison scheme and the output of the second AND element, the information inputs of the counter, block of counters, timer. connected to the input of the device for connecting to the data bus of a controlled computer; the output of the clock generator is connected to the timer sync input. 1608675