SU1471195A1 - Program debugger - Google Patents

Abstract

The invention relates to computing, namely, devices for software control, and can be used in the development and debugging of computer programs. The purpose of the invention is to improve the speed when debugging programs. The device for debugging programs contains registers 1-3 of the base address, comparison circuits 4 and 5, element OR 6, elements 7 and 8, memory block 9, input 10 of the zone memory zone address, device input 11, memory block 12, delay element 13, base address register 14, memory block 15, decoder 16, device access input 17, interrupt signal output 18. 1 il.

Description

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The invention relates to computing technology, namely, devices for programmed control, and can be used in the development and debugging of computer programs.

The aim of the invention is to improve the speed when debugging programs.

The drawing shows a block diagram of the proposed device.

The device for debugging programs contains the first 1, second 2, third 3 registers of the base address, the first and second 5 comparison circuits, the element 6 of the first 6, the first 7 and the second 8 elements the first memory block 9, the input 10 of the memory zone address. , device address input 1, third memory block 12, delay element 13, fourth base address register 14, second

a memory unit 15, a decoder 16, a device access input 17 and an interrupt output 18.

Device operation: em as follows.

Previously, the first register 1 records the cell address of block 9, which is distorted due to an error in the program. Register 14 is loaded with the address, the second corresponds to the address of block 15, Register 3 is loaded with the cell address of block 12, which contains the address of the zone that contains the distorted cell. For example, it is known that in cell A the cell C is distorted; When accessing block 9, a reference signal appears at the input 17 of the device, and a zone address appears at the input 10. Block 12 contains the initial addresses of all operational areas located in block 9,

Structurally, block 12 is a block of permanent and semi-permanent memory, working only on coupling. Information is entered into it on some special equipment that is not part of the proposed device.

If the address occurs at any address that does not match the address typed in register 3, the base address is read from block 12. The read address passes through the open element (group of elements) .And 7, through, the element (group of elements)

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OR 6 and is fed to the input of the second register 2. To the input of the register -1 register, there is a callback signal from the input 1 7 of the device, which, having passed through the element 13, will write to the register 2 the information read from block 2. The delay time of the element 13 is equal to the reading time block 12 and passing through the elements And 7 and SH b. Element And 7 is open, since the output 4 has a zero potential (no comparison).

The decoder 16 decrypts the contents of register 2 and generates a reversal signal, which is fed to the input of block 15. At the input 11 of the device there is the cell address of block 9, which is read (written). information If there is a call to the zone that is of interest to the debugger (whose address is typed in register 3), a single potential appears at the output of circuit 4, which blocks the passage of information from the output of block 12 through AND 7 and allows the passage of information from register ID 14 through AND 8 and the item ШШ 6 on the register input 2.

The decoder 16 signals the access to the block. 15, i.e. if it is known that in block 9 there is zone A in which cell B is located, this zone from block 9 is excluded and transferred to block 15. All programs that legally refer to zone A are turned to block 15. If in some then programs due to errors (no basis) incorrect, unplanned access to zone A, input 11 will contain the address of the cell B of zone A. block 9, which is an error. The addresses of zone A of block 9 should not be addressed at all. In this case, circuit 5 records the moment of comparison of the current address with the address dialed on register 1 (cells B of zone A), and outputs a signal to input 18 of the device, which will be received as an interrupt signal or a stop signal.

Claims (1)

Thus, the interrupt signal is not grabbed at every call to this operator, but only when an unplanned call occurs. Invention Formula Device for debugging programs; containing three registers of the base address, two comparison circuits, two AND elements, an OR element, the first information input of the first comparison circuit is connected to the input of the zone address of the device, the output of the first comparison circuit is connected to the control input of the first And element, the first and second information inputs of the second Comparison circuits are connected respectively to the address input of the device and the speed of the first register of the base address, characterized in that, in order to improve speed when debugging programs, the device contains three blocks of AM, decoder, fourth base address register, the address inputs of the first and second memory blocks are connected to the address input of the device; the first output of the decoder is connected to the access input of the first memory block and the resolution input of the second comparison circuit; the second output and the decoder input are connected respectively the access input of the second memory unit and the output of the second register of the base address, the recording input and the information input of which are connected respectively to the output of the delay element and the output of the OR element, the output Another storage unit is connected to the information input of the first AND element, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the second AND element, the control and information inputs of which are connected respectively to the output of the first comparison circuit and the code of the first register of the base address , the second information input of the first comparison circuitry is connected to the output of the third register of the base address, .address input of the third memory block is connected to the address input of the device zone, the input is about The memory is connected to the access input of the third memory block and the input of the delay element, the outputs of the first and second memory blocks are the first and second information outputs of the device, the output of the second comparison circuit is the output of the device interrupt.