SU1247877A1 - Device for debugging microcomputers - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to configure, debug, and test the operation of specialized microcomputers. The aim of the invention is to expand the functionality due to the ability to make a shutdown at the address depending on the type of httiKpo3BM cycle performed. The device contains a data bus control switch, a direct memory access unit, a trunk amplifier, a display unit, a switch, an input register, a readiness block, two AND elements, two OR elements, a comparison circuit, a stop register, a group of AND elements, and a block of addressing modes , read only memory, toggle switching device. 2 З.П.Ф-ЛЫ, 5 Il., 1 tab. from S to to 4ib vj 00 a

Description

The invention relates to computing and can be used to set up debugging and test the performance of specialized microcomputers,

The purpose of the invention is to expand the functionality by providing a shutdown at an address depending on the type of microcomputer performed.

FIG. 1 shows a functional diagram of a device for debugging a microcomputer, FIG. 2 and 3 are diagrams of a readiness block and a block of addressing modes, respectively; in fig. 4 is a diagram of the algorithm of operation of the device in various shutdown modes; in fig. 5 diagram of the algorithm of the device in step mode.

The microcomputer device (Fig. 1) contains a data bus control switch 1, a memory access enable output for the microcomputer 2 being debugged, a memory direct access access unit 3, a capture input-output microcomputer 4, a trunk amplifier 5, data bus 6 to be debugged microcomputer, display unit 7, address bus 8 to be debugged microcomputer, control bus 9 to be debugged microcomputer, output confirming capture of microprogram to be debugged microcomputer 10J output resolution inputs t1 and output 12 to be debugged microcomputer, switch 13, input register 14, readiness unit 15 -, entrance of debugging microcomputer 16, first input of device 17 mode setting, device 18 start input, first element AND 195 stop control input at device address 20, comparison circuit 21, stop register 22, AND 23 element group, second element 24, block addressing modes 25, memory access address for the debugging microcomputer 26, ROM 27, RAM 28, the first element OR 29, the second element OR 30, the output resolution of the record of the debugging microev 31, the synchronization output of the microprocessor being debugged by the microevm 32, the second task input device mode and 33, the output of the clock generator of the microcomputer being debugged 34, the output of the sign of the beginning of the command of the microcomputer being debugged 35, the interface unit with external devices 36, the interface bus with the external devices 37 of the microcomputer being debugged,

The readiness block (Fig. 2) contains the unit for forming a single impulse 38, the readiness trigger 39, the first element AND 40, the element OR 41,

the second element is AND 42, the element is NOT 43, the element is OR-NOT 44.

The block of addressing modes (Fig. 3) contains the first element And 45, the second element NOT 46, the third element And 47, the first element OR 48, the seventh element And 49, the second element And 50, the first element NOT 51, the fifth element And 52, the sixth element And 53, the second element OR 54, the third element is NOT

55, the eighth element And 56, the quarter element is NOT 57, the fourth element is And 58, the fifth element is NOT 59.

In the quality of ROM, ROM chips can be used, the sampling time and which does not exceed the duration of the microprocessor operation cycle in the microcomputer being debugged. The structural organization of the RAM is similar to the ROM. The memory cells in the RAM are toggle registers.

The microcomputer debugging device provides the following hardware debug modes: shutdown by address. General, stop at the recording address

in the microcomputer RAM, stop at the address when reading from the RAM, stop at the address when entering information from an external device, stop at the address when outputting information to an external device

program walk, smart command mode, direct memory access, microprocessor status indication.

five

Shutdown at the common address occurs when the shutdown toggle breaker at address 20 is turned on, if the addresses supplied to the comparison circuit 21 from the address bus 8 and the RAM 28 and the toggle switches on the stop register 22 match. In this case, the high level signal from the second element 24 is output to the second element OR 30 and from its output enters the input of the first element AND 19, n-but which also receives high-level signals from the comparison circuit and from the stop switch to address 20. From the output of the first element AND 19, the signal goes to the readiness unit 15, then on to hsde readiness 16 cal The signal is low level. Ad0 stops

pecy, when writing and reading from, inputting and outputting information to an external device, occurs when a corresponding signal of the same name appears on one of four control inputs 31.2., 12.11 and the corresponding toggle-stop mode is turned on in the stop-register 22. In these In these modes, the high-level potential is supplied to the second element of the IL 30 from one of the elements And the group of elements And 23

Work in a step-by-step debugging mode of the program becomes possible at high potential at the first input of mode setting 17. Moreover, at high potential at the second input of task 33, a stop is made at the beginning of each cycle of the command being executed using signals from the output of 32 micro computers, and at low only at the beginning of the command. According to the signals coming from the output of the sign of the beginning of the command, 35 micro computers. The transition to the execution of a new cycle or command is provided by pressing the start button 18.

In the mode of direct access to the memory, it is possible to record and read information from the first microcomputer without the participation of the micropressor. The address of the memory location where information is written or read is dialed in the toggle registers of the RAM 28. Information is entered from input register 14. The direct memory access unit 3 issues a high level signal to interrupt request 4 bus, which also goes to the control switch data bus 1, allows information on the data bus b through the main amplifier 5c register in

About About X X

110 111

Oh oh

1 o

one

about

0

S

0

about

five

five

Yes 14. After receiving the confirmation signal from the output of the 10 micro computers, the direct access memory unit 3 controls writing, reading information from the memory, and writing or reading signals to the control bus 9. When data is transferred from the memory to the register 14, it is produced only, its indication with the help of the display unit 7. The display unit 7, besides the data bus, allows to indicate. signals on the address. 8 and control 9 tires.

In addition, debugging modes are provided using various programs recorded in ROM 27 or dialed onto ROM 28. In this case, one can refer both to the entire memory field addressed by the microprocessor and only to its individual zones. The block of addressing modes 24 allows accessing the microcomputer memory only to the RAM 38; to ROM 27 and macro memory; to ROM 27; TZU 28 and microcomputer memory. The addressing modes are set by the toggle switches T1 and T2 in addressing unit 25, which operates according to the table.

1 - It- In table A “A. and A. .. A. -

 6 i-d 2 t; .р 1

the signals generated by the first 45 and second 50 elements, respectively. And in the block of addressing modes 25. As can be seen from these expressions, the RAM 28 and ROM 27 occupy the initial zone in the addressed microteute norte memory, therefore with simultaneous reading to ROM 28, ROM 27 and the memory of the microcomputer is not addressed to the cells with the start addresses of the latter.

about 1

about 1

oh oh

Memory microcomputer

TZU only

ROM and MicroMB memory

Also

RAM, ROM and microcomputer memory

Also

In Table X, it means that the signal can take the value of both O and 1.

The microcomputer debugging software provides the following debugging modes: manual byte entry of information into the system memory, testing of microcomputer nodes, cyclic command execution, input - output of information from external devices.

Manual byte entry of information can be made either from input register 14, or from RAM 28, the input program is typed in ROM 28, or the one used in ROM 27. In this mode, the block of addressing modes 25 allows access to RAM 28, ROM 27 and microcomputer memory. The selection of I / O register 14 produces a switch 13. Signals for allowing access from addressing unit 25 also go to element OR 29, from its output one of them is output to data bus switch 1, which controls connection to data bus 6 of RAM 29 or ROM 27 or input register 14.

The test check of the nodes is performed using specialized programs written in accordance with the specifics of the tested microcomputer nodes. and recorded in ROM 27.

Cyclic execution of any command of the microprocessor is performed when the block of addressing modes 25 allows accessing only the RAM 25. In this case, the code of the command being checked must be entered on all toggle registers of the RAM 28.

Input - output of information from external devices is carried out using the interface unit with external devices 36 via the interface bus with external devices 37. External devices are accessed when signals appear at 11 or 12 micro-computers and the address of an external device on the address bus 8. In this case, the switch 13 outputs to the interface with external devices 36 a permission signal for accessing the corresponding external device. As an external device, a perforator and a photo reader can act.

The algorithm of operation of the device in various shutdown modes is shown in FIG. 4. Sled is used here.

five

designations: (ША) - the contents of the address bus 8; (A (OZU) - the contents of the registers of the OZU 28, where the stop address is set; T. stop. - stop switch to the address (control input - stop address at 20), (T.Rg. Stop) - contents toggle register - stop register 22, DO, D1, D2, DZ - Q zero, first, second and third bits of the toggle stop register 22.

The operation algorithm of the device in the step mode is shown in FIG. 5. Here, the & denotes the conjunction of signals at the corresponding outputs of the device (indicated in parentheses).

Claims (3)

1. A device for debugging a microcomputer containing a data bus control switch, a trunk amplifier, a display unit, a direct memory access block, a block of addressing modes, an input register, a switch, a comparison circuit, a readiness block, And element the first information input of the data bus control switch is connected to the memory access output of the debugged  microcomputer, the second information input of the data bus control switch is connected to the capture output of the direct memory access unit, also connected to the capture input of the microcomputer being debugged, the information output of the direct memory access control unit is connected to the bi-directional bus . data of the ivaemoy microcomputer to which the first input is also connected . the display unit and the output of the main amplifier; the control input of the main amplifier is connected to the output of the data bus switch; the output of the direct memory access unit mode is connected to the second input of the display unit and to the input bus of the read and write microcomputer, the output is the direct memory access unit is connected to the bi-directional bus of the address of the microcomputer being debugged, the third input of the display unit is connected to the bi-directional bus of the address of the microcomputer being debugged and the enable input of the direct-access unit second memory access circuit connected to the output of an acknowledgment capture debugged mikro0 five 0 five 0 The computer, outputs of the input and output resolution of the microcomputer being debugged are connected to the first and second control inputs of the switch, respectively, the first output of the switch is connected to the input enable input of the input register and the first input of the readiness block, the output of which is connected to the readiness input of the microelectric, the second input of the readiness block is connected with the output of the first element And, the third and fourth inputs of the ready block are the first input of the mode setting and the start input of the device, respectively, the first input of the first element is control of the stop at the device address, and the second input is connected to the output of the comparison circuit, the first input of which is connected to the bi-directional address bus of the microcomputer being debugged, which differs from the fact that, in order to expand the functionality by providing a stop at the address, depending on the type of microcomputer cycle, the device contains a stop register, a group of elements And, the second element And, permanent memory (ROM), toggle memory device (RAM), the first and second elements OR, and The first information output of the RAM, the information input of the main amplifier, is connected to the second information output of the RAM, the information output of the ROM and the output of the input register, the first and second outputs of the switch are connected to the second input of the comparison circuit and to the address input of the direct memory access block. the third and fourth inputs of the first OR element are connected to the first and second inputs of the first OR element, the output of which is connected to the control input of the Comm control bus of the data bus; with the first and second resolving outputs of the addressing mode block, the third allowing output of which is connected to the memory access address of the microcomputer being debugged, the first and second permitting outputs of the addressing mode block are connected to the first access enable switches of the RAM and ROM, respectively, the information input of the switch , address block addressing modes. and the address inputs of the RAM and ROM are connected to the bi-directional bus of the address of the microcomputer being debugged, allowing the input of the block of addressing modes and the second inputs of the accessibility of the RAM and ROM are connected to the output of the access to the memory of the microcomputer being debugged, the first inputs of the And group are connected to the outputs of the resolution input, output resolution, memory access, recording resolution of the microcomputer being debugged, the outputs of the bits of the stop register are connected to the second inputs of the And group elements and to the inverse inputs of the second, And ,. . the output of which is connected to the first input of the second element OR, the second - the fifth inputs of which are connected to the outputs of the first - fourth elements AND of the group, respectively, the output of the second element OR is connected to the third input of the first element AND, the fifth - eighth inputs of the readiness block are connected respectively, to the output — synchronization of the microprocessor of the microcomputer being debugged to the second input of the device mode setting, to the output of the clock generator of the Microbe computer being debugged, to the output of the sign of the beginning of the command of the microcomputer being debugged. 2, the device according to claim 1, that is, in that the readiness block contains a readiness trigger, a unit impulse formation unit, an OR-NOT element, first and second AND elements, an OR element, and an NOT element, and the first - the third inputs of the OR-NOT element are the first-third inputs of the ready block, respectively, the output of the OR element is NOT connected to the information input of the ready trigger, the output of which is the output of the ready block and connected to the first input of the unit of formation signal, the second and third input of which These are the seventh and fourth inputs of the readiness unit, respectively; the first input of the first element AND is the fifth input of the readiness block; the output of the first element AND is connected to the first input of the OR element, the output of which is connected to the synchronization input of the ready trigger, the S input is connected with the output of the unit of formation of a single pulse, the sixth input of the unit is connected to the input five 0 five 0 the element NOT and the second input of the first element AND, the first input of the second element AND is the eighth input of the ready unit, the second input of the second element AND is connected to the output of the element NOT, the output of the second element AND is connected to the second input of the element OR. 3. The device according to claim 1, about tl and - h it is that the block of addressing modes contains eight elements AND, two elements OR, five elements NOT and the first and second toggle switches of the addressing mode, and the first group of bits of the first the input of the block of addressing modes is connected to the inputs of the first element AND, the second group of bits of the first input of the block of addressing modes is connected to the inputs of the second element AND whose output is connected to the first input of the third element AND and to the input of the first element NOT, the output of the first element AND is connected to the entrance of the second The element is NOT, the second input of the third element is AND, and the first input of the fourth element is AND, the outputs of the first and second elements are NOT connected to the first inputs of the fifth and sixth elements AND, respectively, the output of the third element AND is connected to the first input of the first element OR, the output of which is 9- inn with the first input of the seventh element I, the input of the third element NOT and the second input of the seventh element AND are connected to the first toggle switch for the addressing mode, the second toggle switch for the addressing mode is connected to the input of the fourth element NOT to the second inputs of the fourth and sixth elements And, the output the third element is NOT connected to the second input of the fifth element AND and the first input of the eighth element AND the output of the fourth element is NOT connected to the second inputs of the first OR element and the eighth AND element, the output of which is connected to the first input the second element OR, the second input of which is connected to the output of the sixth element AND, the output of the fifth element AND is connected to the third input of the fourth element AND, the second input of the block of addressing modes is connected to the input of the fifth element NOT to the third input of the seventh element AND to the fourth input the fourth element And, the output of the nth element is NOT connected to. the third input of the second element OR, the outputs of the seventh element AND, the fourth element AND, and the second element OR are the first, second, and third outputs of the addressing mode block, respectively. 50  J52 FIG. 2 26 Qlovaffo stop. S Hot / AM cycle SbifJ - Q stop. 8 fffft / am / gd mot / SlHX.rf: sff .five Compiled by V.Vanyuhin Editor L.Aaramenko Tehred E.Chüyu-1ar Corrector I.Muska Order 4127/49 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. „4/5 Production printing company, Tsriytiye 9 g, Uzhgorod, st. Project, 4