SU1322332A1 - Device for tracing around nodes of net model - Google Patents

Abstract

The invention relates to the field of analog-digital computing and can be used in a hybrid computing system for collecting and transmitting a solution from a grid electric model in a digital computer. The aim of the invention is to improve speed. The device contains analog multiplexer 1, digital multiplexers 15, 16, switch 2, code-to-voltage converter 3, comparison block 4, microprogram control block 5, time interval shaping unit 6, analog-digital converters 7-10, adders 11-14, register block 17, block 18 of digital-analog converters, correction code register 19, encoder 20, decoder 21. The device allows to increase speed by reducing the number of iterations in solving the problem. 6 Il. sl from to 00 with 1C

Description

The invention relates to analog digital computer technology and can be used in a hybrid computer system for collecting and transmitting a solution from a grid electric model to a digital computer (DVM).

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of a device for outputting information from a grid electric model; in fig. 2 is a block diagram of a firmware control unit and a time slot generation unit; in fig. 3-6 - algorithm of operation of the device for the output of information from the grid electric model.

The device (Fig. 1) contains an analog multiplexer 1, a switch 2, a code-to-voltage converter 3, a comparison unit 4, a microprogram control unit 5, a time interval shaping unit 6, analog-digital converters 7-10, adders 11-14, first multiplexer 15, second digital multiplexer 16, block 17 registers, block 18 digital-analog converters, register 19 of the correction code, additional encoder 20, decoder 21, bus 22 of zero potential

I

Firmware control unit 5 (FIG. 2) contains a command code register 23, a shift register 24, a first multiplexer 25, a microprogram memory block 26, a counter 27, micro-command counter 28, a transition address register 29, an encoder 30, a loop counter 31, a second multiplexer 32 re

a micro-code code master 33, a sensor address register 34, a reference value code register 35, a sample counter 36 and a generator of 37 rectangular pulses.

The time interval shaping unit 6 (FIG. 2) contains a pause code register 38, a time counter 39, an address counter 40, a start coder 41, and a trigger 42.

The device works in the following way.

To analog input analog

multiplexer 1

electric model. In the firmware memory block 26, a program of operation of the device is recorded, after which the device is ready for operation.

connect the grid 55 with digital converters 7-10 of the conversion termination signal from their second outputs to the sixth, seventh, eighth and ninth inputs of the second multiplexer 32 of block 5.

The operation of the device is synchronized by the microprogram control unit 5, the operation of the nodes of which is clocked by the generator 37

pulses. According to the program recorded in microprogram control unit 5, the sensor address code register 34 writes an array of node address addresses codes of the grid electric model that the device refers to into the reference voltage code register 35 — an array of reference voltage codes for monitoring the health of analog-to-digital converters

7-10, into the pause code register 38, the pause code for starting analog-digital converters 7-10, depending on the speed of the device nodes, and for the 31-cycle counter, the constant code equal to the number of analog-digital converters in the device.

Before starting the survey of grid point electrical models, the zero-level drift of analog-to-digital converters 7-10 is corrected. To do this, from the command control register register 33, the microinstructions code to the second inputs of the additional encoder 20 and block 6 receives a microcommand, through which the switch 2 connects the first potential bus 22-14 to the first inputs, and the trigger 42 sets to the zero state and the pause code from the exit

the pause code register 38 is recorded in a time counter 39. According to the following micro-command, a reset of the register block 17 and the installation of the trigger 42 into a single state, the transfer

timer 39 from recording mode to subtraction mode. By clock pulses, the contents of time counter 39 are reduced to zero. When the time counter 39 is zeroed, a signal appears at its output, which arrives at the first input of the start coder 41, at which a signal appears at its outputs that triggers analog-to-digital converters 7-10.

Firmware control unit 5 proceeds to wait for the end of the conversion. Upon completion of the conversion of the zero potential of the analogue, these signals from the output of the register 33 of the microinstruction code to the control input of the register block 17 receive the write enable command. Correction codes corresponding to the magnitude of the zero-level drift, from the first outputs of the analog-digital converters 7-10, are written into the block 17 of registers. Then, performance checks of all analog-to-digital converters 7-10 are carried out. Upon a command from register 33 of the microinstruction code, the codes of the reference voltages from the output of the register 35 of the code of the reference voltage are fed to the source 3 of the reference voltage and to the first input of the unit 4 of the comparison. According to the micro-command from the register 33 of the micro-command code, the trigger 42 is set to the zero state and the pause code is written to the time counter 39. The next micro-command trigger 42 is set to one and the time counter 39 goes into subtraction mode. The clock signals decrease the content of the time counter 39. When the latter is zeroed, a pulse is received from its output to the first input of the address counter 40 and to the first input of the start coder 41, through which one is added to the contents of the counter 40 of the address, and the start signals of analog-to-digital converters 7-10 are output at the outputs of the start coder 41. These signals trigger all analog-to-digital converters 7-10. Switch 2, via control signals from additional encoder 20, connects the second inputs of adders 11-14 to the output of a code to voltage converter.

At the first inputs of adders 11-14, potentials corresponding to the values of zero-level drift act. Difference potentials from the outputs of adders 11-14 are fed to the second inputs of analog-to-digital converters 7-10.

Microprogram control unit 5 proceeds to wait for the end of the conversion of the first analog-digital converter 7. According to the micro-command from register 33 of the micro-command code, the second multiplexer 16 connects the first output of the analog-to-digital converter 7 to the second input of the 4 comparison unit, at the first input which has a reference voltage code.

The result of the comparison with the output of the comparison unit 4 is written into the register 19 of the correction code according to the signal of the conversion end of the analog-to-digital converter 7 received from its second output. The contents of the counter 31 cycles reduced by one. If the contents of the cycle counter is zero, the firmware control unit 5 returns the device to its initial state. If the contents of the loop counter 31 is not zero, select the analog-to-digital converter 8 and the process of checking the operability of the analog-digital converters 7-10 repeats cyclically until the counter of the 31 cycles is reset. The following micro-command checks the status of analog-to-digital converters 7-10 by analyzing the contents of register 19 of the correction code. If there are no good analog-to-digital converters in the device, microprogram control unit 5 issues a Failure signal in the device and the device proceeds to the beginning of the algorithm. If the device has intact analog-to-digital converters, the device switches to the decision removal mode with the grid electric model.

In case of a faulty analog-digital converter, the additional encoder 20, according to the signal of the register 19 of the correction code, excludes it from the operation of the device.

The loop counter records a constant code equal to the number of healthy analog-to-digital converters in the device. The trigger 42 is set to one. Pulsing with pulses reduces the contents of time counter 39 before zeroing. According to the microcommand, register 33 of the microinstructor code into register 34 of the sensor address code writes the code of the initial address of the interrogation source array, arriving at the first input of the decoder 21, the second input of which receives the correction code from the output of the additional encoder 20. The decoder 21 in the analog multiplexer selects the corresponding the keys connecting the polling sources to the first input of the switch 2, connecting the output of the analog multiplexer 1 to the first input of the adder 11 at the command from the output of the additional encoder 20. For this purpose e command switch 2 connects

513

the first input of the adder 14 with the output of the converter 3 codes to voltage. The second inputs of adders 11 and 14 receive the potential of the zero-level drift from the output of the block of digital-analogue converters 18.

The differential signals from the outputs of the tori 11 and 14 are fed to the second inputs of the analog-digital converters 7 and 10. When the time counter 39 is zeroed, the output from the address counter 40 is increased by one and the start signals appear at the outputs of the start encoders 41. These signals trigger analog-to-digital converters 7 and 10. Analog-to-digital converter 7 converts the potential of the selected nodal point of the electric model, and analog-to-digital converter 10 operates in the self-monitoring mode. According to the micro-command from register 33 of the micro-command code, the trigger 42 is set to the zero state, and from the register 38 of the pause code to the time counter 39 a pause code is written, then the trigger 42 is switched to one and the resetting of the time counter 39 begins. When the last signal is cleared from its output, the signal increases the content of the address 40 by one and a trigger signal appears at the output of the start coder 41, which triggers the analog-digital converter 8. Similarly, the analog-digital converter 9 is started. The analog-digital converter 7 ends the conversion. analog-to-digital converter 10, According to the microinstruction from register 33 of the microinstructions code, the code from the output of the analog-to-digital converter 7 through the first multiplexer 15 enters into the digital computer. The analog-to-digital converter 7 is started, the code converter into voltage and the output of the block of digital-to-analog converters 18 are connected to the inputs of the adder 11. It finishes the conversion of the analog-digital converter 8.

The device works in a similar way until the solution is completely removed from the grid model, with three analog-digital converters operating in the data retrieval mode, and one in the health monitoring mode. Thus, during the removal and transformation of psychiatric cells into atopopax 11–14 out of 26

The node point potential subtracts the voltage corresponding to the zero-level drift of the given analog-to-digital converter.

Claims (1)

Invention Formula A device for bypassing grid model nodes containing a firmware control block consisting of a command code register, a shift register, a first multiplexer, a microprogram memory block, a micro-command counter, a transition address register, an encoder, a cycle counter, a second multiplexer, a micro-command code register , the register of the sensor address code, the register of the reference value code, the sample counter and the square pulse generator, the output of which is connected to the clock inputs of the sample counter, cycle counter, register code microinstructions, microinstructions counter, register of the transition address and register of the instruction code, the output of which is connected to the input of the shift register, the output of which is connected to the first information inputs of the first and second multiplexers, the output the first multiplexer is connected to the input of the counter, the output of which is connected to the input of the current address of the microcommand counter, the output of which is connected to the second information input of the first multiplexer, the output of which is connected to the microcontrol memory read input of the microcommand, the output of which is connected to the information of the microinstruction code register, the output the transition field of which is connected to the third information input of the first multiplexer, to the information input of the transition address register and to the write enable input and a cycle counter, the count input of which is connected to the first output of the encoder, a second output of which is connected to the input branch address register write enable, the output of which connected to the fourth information input of the first multiplexer, the first and second outputs of the register of micro-instructions are connected to the address inputs of the encoder, respectively, and the second multiplexer, the output of which is connected to the information input of the encoder, the third and fourth outputs of which are connected respectively to the input of the write resolution of the command code register and the control input of the first multiplexer, first, second and third outputs of the field of microcommands of the microcode command register are connected to the inputs of the write permission of the corresponding register of the sensor address code register of the reference voltage code and sample counter, the output of the loop counter is connected to the gate input of the second multiplexer, the analog A new multiplexer, the output of which is connected to the first information input of the switch, the second information input of which is connected to the output of the code-to-voltage converter, whose input is connected to the first input of the comparison unit and the output of the reference value code register, the time interval forming unit consisting of register of the pause code, time counter, address counter, start encoder and trigger, the output of which is connected to the time counter information recording input, the information input of which is connected to the output m of the pause code register, the output of the time counter is connected to the start gate encoder input and the address counter count input, the output of which is connected to the trigger encoder gate input, whose information input is connected to the output of the correction code register and the second information input of the second multiplexer, fourth floor output microinstructions of the microinstructions code register are connected to the enable input of the entry of the trigger coder, the enable input of the count of the address counter, the trigger input and the write enable input of the register to The pause code, the information input of which is connected to the information inputs of the register of the sensor code, the reference voltage code register, the command code register register, the microinstruction code register register write inputs, the encoder and the input multiplexer, the fifth microcode command register output is connected to the first digital multiplexer, the first, second, third, and fourth information inputs of which are connected to the outputs of the first, second, third, and fourth analog-digital signals, respectively. generators and respectively the first, second, third and fourth information inputs of the second digital multiplexer, the control input of which is connected to the sixth code of the microcommand code register register, the seventh output of the microcommand field is connected to the resolution enable input of the correction code register, the recording input of which is connected to the output of the comparison unit, the second input of which is connected to the output of the second digital multiplexer, the third, fourth, fifth and sixth information inputs of the second multiplexer connected to the outputs of the conversion end signals, respectively, of the first, second, third, and fourth analog-to-digital converters and, respectively, the first, second, third, and fourth information inputs of the correction code register, the information input of the command code register is the device start input, the output of the square pulse generator connected to the counting input of the time counter, the first, second, third and fourth outputs of the start coder are connected to the start inputs of the first, second, respectively first, third and fourth analog-to-digital converters, the output of the first digital multiplexer is an information output of the device, characterized in that, in order to improve speed, a block of registers, a block of digital-analog converters, four adders and an additional encoder are entered into it, connected to the control input of the switch and the gate input of the decoder; the first, second, third, and quarter-outputs of the switch are connected to the first inputs of the first, second, third, and the fourth adders, the outputs of which are connected to the information inputs of the first, second, third and fourth analog-to-digital converters, respectively, whose outputs are connected to the first, second, third and fourth information inputs of the register block, respectively, the first, second, third and fourth outputs of which are connected with the first, second, third and fourth inputs of the block of analog-to-digital converters, the first, second, third and fourth outputs of which are connected to the second inputs of the corresponding effectively of the first, second, third and fourth adders, the ninth output of the field of micro-commands of the register of micro-commands of the code register is connected to the input of the record of the unit 132233210 gistrov, the output of the counter vygrki connected to the gate input additional encoder, information input which is connected to the output register of the correction code. T y V f fig 2 with Start I Initial reset Device ready )  device not Yes. Reception d 34 Choosing an address 21 Reception b 23 Install source j not Command pr ta b evp I Reset 0. 38, 2 Set STC 315 not Yes Otkrenut team Jump by team Pause code / fdpec source Reference Source Code Correction code Control game J Setting trigger 2 f AT V h / ig. Control of limes Data ne / tG on SD X Yes Reception b 35 Transformation in J Podmucheaya Comparing 35 with 19 Record rez / 1yatta. With 6 19 I Setup control mode flU, n 7.8,9.10 Connection / 1SchP to J -1 STC 31 not . Install Tr V2 / Installation of JTS J / Pause code Reception b 38 fl / (LZ.S Correction code Koppeffuuff mode setup Connect /} CPU to 22 Trigger setup i Write code b counter J9 Write correction code 8 17 Conversion b 18 Source code of this / 7on voltage npueh b 35 SD - data bus device Phage. 6 Compiled by V. Rybin, Editor N. Rogulich Tehred L. Oliynps Corrector A. Zimokosov Order 2868/48 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 and /