SU1596390A1 - Buffer memory device - Google Patents

Abstract

The invention relates to automation and computing and can be used to organize the exchange of information between elements of multiprocessor computing systems, as well as in automated control systems as a buffer memory device. The purpose of the invention is to increase productivity. The device contains the first group of 1 elements AND, the input register 2, the second and third groups 3 and 4 elements AND, the elements OR signs 5 and 6, the information group 7 elements OR, the registers of record 8 and reading 9, the decoders of the address 10 and 11, M blocks 12 buffer memory. By ensuring the simultaneous recording and reading of information and by excluding the transmission to the device and deciphering the cell address of the block of the buffer memory into which (from) information is written (read), since this address is automatically generated, the exchange performance in the system is improved. 2 Il.

Description

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The invention relates to automation and computing and can be used to organize the exchange of information between elements of multiprocessor computing systems, as well as in automated control systems as a buffer memory device;

The purpose of the invention is to improve the performance of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional block buffer circuit.

The device contains (Fig. 1) the first group 1 of the elements AND, the input register 2, the second 3 and the third 4 groups of the elements AND, the elements OR 5 and b of the feature, the information group 7 of the elements U1LI, the registers of writing 8 and reading 9, the decoders 10 and 11 addresses, M blocks 12 of buffer memory, outputs 13 and 14 of the device unavailability, device address inputs 15 and 16, device write gate 17, device read gate 18, device initial setup input 19, device information input 20, information output 21 devices.

The buffer memory unit 12 contains (FIG. 2) delay elements 22-25, elements OR 26 and 27, group 28 elements OR, trigger 29, elements AND 30-33, element 34, decoders 35 and 36 (addresses), counters 37 and 38 addresses, a comparison circuit 39, N information registers 40, N groups 41 elements AND of the first block, N groups 42 elements AND the second block.

FIG. 2 also denotes a buffer memory write unavailable output 43, a buffer memory block data output 44, a buffer memory block read output 45, a buffer memory block selection input 46, a buffer memory block installation input 47, a read gate input 48 the buffer memory block, the gate input entry 49 of the buffer memory block, the buffer data block input 50, the second buffer memory block input 51.

The device works as follows.

The code set in register 8 determines the address of the buffer storage unit 12 to which information should be written upon next access to the device in recording mode. The code set on the counting 37 of the i-ro block 12 of the buffer memory (i 1, M) determines the address j-ro (j 1, N) of register 40, into which information is written during the next access to the device in recording mode .

The code set on register 9 determines the address of the buffer memory block 12, from which information should be read during the next access to the device in

reading mode. The code set on the i-ro counter 38 of the buffer memory block 12 determines the address of the j-ro register 40, from which information is read in the next access to the device in read mode.

0 Requests to write and read to the device are received asynchronously, therefore, during the operation of the device, information is recorded only into unused blocks 12 of the buffer memory, and reading

5 information is provided only from those registers 40 in which the recording was made. This is achieved as follows. After recording the information in the Nth register 40 i-ro block 12 buffer memory counter 37 i-ro

0 of block 12 is zeroed due to overflow, and the overflow signal places the trigger 29 of 1st block 12 into one state. Zero potential at the inverse output of this trigger 29

5 prohibits further recording of information in the 1st block 12. At the same time, a high potential at the forward output of the flip-flop 29 enters through the OR element 26 of the i-ro block 12 to the input of the element 31 of the i-i block 12,

0 permits reading from block 1, regardless of the state of the other control elements of the block. In other cases, reading from i-ro of block 12 is permitted when the condition of not meeting the contents of the corresponding counter 38 of the contents of the corresponding counter 37 is met. If in the 1st block 12 the contents of the counter 38 became equal to the contents of the counter 37, then the output

0 of the comparison circuit 39, a zero potential is established which, through the corresponding element OR 26, arrives at the corresponding element AND 31 and prohibits the reading of information from the i-ro block 12.

5 The trigger 29 of the i-ro block 12 is reset to its initial state after reading the information from the N-ro register 40 of the 1st block 12. In this case, an overflow signal of the corresponding counter 38 is generated,

0 which, acting on the corresponding element OR 27, performs actions for i-ro block 12. similar to the initial setup signal.

Before starting work using the im5, the pulse signal arriving at the input 19 of the device, all blocks 12 of the buffer memory reset the counters 37 and 38, the registers 40 and the trigger 29,

When entering and information, the recording signal is fed to the input 17 of the device and enables

passing information from device input 20 through group 1 of elements I to register 2. At the same time, it allows the address of the selectable buffer storage unit 12 to pass from device 15 input through group of 3 elements to register 8. As a result, the corresponding output of decoder 10 appears the potential that enters the input elements And 30 and 32 of the corresponding block 12 of the buffer memory, thereby preparing it for operation, the recording signal after a delay on the delay element 22 in the presence of a trigger 29 in the initial state through co The corresponding element AND 30 is fed to the input of blocks 41 of groups of elements AND of the corresponding block 12. Information is recorded in the corresponding register 40 when there is an enable signal at the corresponding output of the decoder 35 of this block 12. After a delay on the corresponding delay element 25, the information is written to register 40 the control signal of the record increases the content of the corresponding counter 37 by one, as a result of which the conditions for writing to the next register are prepared using the appropriate decoder 40 of this unit 12.

In case the trigger 29 of the corresponding block 12 is in the single state (the buffer memory block is full and the recording is prohibited), then a high potential is present at the input of the corresponding element 32. Therefore, the recording signal from the output of the corresponding delay element 22 passes through the corresponding element AND 32 and the element OR 5 to the output 13 of the device, indicating that it is impossible to write to the specified block 12 of the buffer memory.

The information is read when the control signal of the reader is input to input 18. This signal permits the passage of the address of the selectable buffer storage unit 12 from the input 16 of the device through a group of 4 elements AND to the register 9. As a result, a corresponding potential appears at the corresponding output of the decoder 11, which is fed to the input of elements And 31 and 33 of the corresponding block 12, thereby preparing it for work. If the reading is allowed, the reading signal after a delay on the delay element 23 through the corresponding element And 31 enters the input of the group 42 of the elements And the corresponding block 12. The readout of the information from the corresponding register 40 is performed when there is an enable signal on the corresponding output of the decoder 36 of this block 12. The information signal from the register 40 through the corresponding group of 42 elements AND and the group of 28 elements OR of this block 12 and further the group of 7 elements OR is fed to the information output 21 of the device . After a delay on the delay element 24 of the corresponding block 12, the read control information signal increases the content of the corresponding counter 38 by one by the time of reading the information, as a result of which using the corresponding decoder 36 prepares the read conditions from the next register 40 of this block 12.

If reading is prohibited, then a high potential is present at the output of the corresponding element NOT 34, which allows the reading signal from the output of the delay element 23 to pass through the corresponding element AND 33. This signal through the element OR 6 enters the output 14 of the device, signaling the impossibility of reading from the specified block 12 of the buffer memory.

Claims (1)

Claims A buffer storage device comprising an input register. M blocks of buffer memory, the first group of elements AND, and each block of buffer memory contains three delay elements, two address counters, a comparison circuit, two decoders, two OR elements, a group of OR elements. trigger, two elements AND, two blocks of N groups of elements AND (where N is the number of words of the entered information), N information registers, the first inputs of the elements AND of the first group form the information input of the device, the second inputs of the elements AND of the first group are connected to the input of the recording strobe the device and with the same inputs of all blocks of the buffer memory, the data inputs of KO1 are connected to the output of the input register, the data input of which is connected to the outputs of the And elements of the first group, the input of the initial installation of the device is connected to the input Installation of all blocks of the buffer memory, in each block of the buffer memory, the entry for recording gates through the first delay element is connected to the first input of the first element And whose output is connected to the first inputs of the elements And groups of the first block and through the second delay element to the counting input of the first address counters, the reset input of which is connected to the same inputs of the second address counter, all information registers and the trigger and the output of the first element OR, the first the input of which is the installation input of the buffer memory block, the second input of the first element OR is connected to the overflow output of the second counter of the adress. the information output of which is connected to the data input of the first decoder and the first input of the comparison circuit, the second input of which is connected to the data input of the second decoder and to the information output of the first address counter, the overflow output of which is connected to the trigger installation input, the inverse output of which is connected to the second input of the first element And, the direct output of the trigger is connected to the first input of the second element OR, the second input of which is connected to the output Not equal to the comparison circuit, the output of the second element OR is connected to the red the second input of the second element, the output of which is connected to the first inputs of the elements And groups of the second block and through the third delay element to the counting input of the second address counter, the data input of the buffer memory block is connected to the second inputs of the elements And groups of the first block, the third inputs of which connected to the corresponding outputs of the second decoder, the outputs of the first decoder are connected respectively to the second inputs of the elements AND groups of the second block, the outputs of the elements AND 1st group (i 1, N) of the first block are connected to the information input ohm of the 1st information register, the output of which is connected to the third inputs of the elements AND of the i-th group of the second block, the outputs of the elements AND of all groups of the second block are connected to the corresponding groups of inputs of the elements of the OR group, characterized in that, in order to improve performance, the device the first and second address decoders, the write register and the read register, the second and third AND group of the elements, the first and second OR elements, the information group are entered. elements OR, and in each block of buffer memory - the fourth delay element, the element NOT, the third and fourth elements AND, the recording entry gating input of the device is connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the first address input of the device, and the outputs - with bits of the information input of the record register, the output of which is connected to the input of the first address decoder, the outputs of which are connected to the first inputs of the selection of the corresponding blocks of the buffer memory, the unavailability of the recording of which dineny, the inputs of first OR feature, the output of which is the first output of the unavailability indication device input reading gating device is connected to the same inputs of all blocks of the buffer memory and the first inputs of the elements of the third group, the second inputs of which are connected to the second address input of the device, and the outputs - to the bits of the information input of the reading register, the output of which is connected to the input of the second address decoder, the outputs of which are connected to the second inputs of the selection of the corresponding blocks of the buffer memory, the readiness outputs of which are connected to the inputs of the second OR element, the output of which is the second Signs of unavailability m output device outputs data of each block of buffer memory are connected with the corresponding groups of inputs of the elements OR of the information group, the outputs of which form the information output of the device, each to the buffer memory block, the data output is connected to the outputs of the OR elements of the group, the input of the strobe reading of the buffer memory block through the fourth delay element is connected to the second input of the second element AND, the third input of which is connected to the second input of the selection of the buffer memory block, the first input of the selection of which is connected to the third input of the first element And and the first input of the third element And, the second the input of which is connected to the output of the first delay element, the direct output of the trigger is connected to the third input of the third element AND, the output of which is the output of unavailability of writing the block of the buffer memory, the output of unavailability of reading of which is connected to the output of the fourth element AND, the first input of which is NOT connected to the output of the second element OR, the second input of the fourth element AND is connected to the third input of the second element AND, the second input of which is connected to the third input of the fourth element I.