SU1347097A1 - Memory with program correction - Google Patents

Abstract

The invention relates to computing and can be used to create permanent memory devices with the possibility of correcting the recorded data. The aim of the invention is to expand the field of application of the device by coordinating the sampling time of blocks of permanent and semi-permanent memory. The device contains a control unit, permanent and semi-permanent memory blocks, a numeric register, a switch, the first and second triggers, a pulse generator, a counter, an AND-NO element. The device provides for the matching of the sampling time of the blocks of permanent and semi-permanent memory by initial setting of the counter, specifying the device cycle time corresponding to the slower sampling time of the semi-permanent memory block. 2 Il. (L 00 4 ;: About with sj

Description

The invention relates to computing and can be used to create permanent storage devices with the ability to correct the recorded data.

The aim of the invention is to expand the field of application of the device by using blocks of semi-permanent memory with different sampling times in the device.

FIG. 1 shows a block diagram of a memory device with program correction in FIG. 2, a block diagram of a control unit.

The device (Fig. 1) contains a control block 1, a block 2 of permanent memory, a register 3 of the initial state code, a numeric register 4, a block 5 of semi-permanent memory, a switch 6, the first trigger 7, a pulse generator 8, a counter 9, the second trigger 10, the element AND-NOT 11, input 12, synchronization, mode selection inputs 13, address code inputs 14, setup inputs 15, identification identification output 16 of the loop, output 17 of the end of cycle, and information outputs 18.

The control unit 1 (Fig. 2) contains the first 19 and second 20 elements AND, the address register 21, the first 22 and second 23 drivers, the first 24 and second 25 groups of elements AND, the switch 26 and the outputs 27-29 o

The volumes of blocks of constant and semi-permanent memory are the same. Counter 9 counts clock pulses from a controlled pulse generator and generates a signal (at the transfer output of the counter), which serves as a signal informing the digital computer or special calculator about the readiness of this device to issue information.

The controlled pulse generator 8 generates pulses at its output only with a single signal at its input. The switch 6 outputs to its output the contents of block 2 in the single state at the control input and the contents of the block 5 in the zero state at the control input.

The device operates in two modes: in operating mode; automatic program correction mode during initial debugging of the system or system changeover to new tasks and in the manual correction mode of the numbers recorded in block 5 of the semi-permanent memory. From here

five

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Carries and the mode of the initial input of the adjusted numbers in block 5.

According to the initial start-up signal (not shown), the first 22 and second 23 drivers are reset to the zero state, i.e. The device is ready for operation.

The operation of the device in the program automatic correction mode is set by the Read signal received via the first control bus 13, which allows clock pulses (input 12) to pass through the first element AND 19 to the input of the first driver 22. At the output 22 of the driver, a read address transmission permission signal is generated, which permits the passage of the address code from the bus 14 through the first group of 24 elements And to the first inputs of the switch 26. At the same time, the Read signal opens the switch 26 through the first inputs, i.e. permits issuance on

5 address inputs of blocks 2 and 5 of the memory of the address code. At output 22, a readout memory signal is generated, which is used to read information from blocks 2 and 5 at the previously set address. Information from blocks 2 and 5 is fed to the inputs of block 6 of the number selection. At the same time, the Read Memory signal sets the trigger 7 to one state. (the information input of the trigger 7 is connected to the logic unit level), which starts the controlled generator of 8 pulses. At the output of the latter, clock pulses are formed only if there is a single level at its input. The signals from the output of the generator 8 are fed to the summation input of the counter 9, which is preset according to the data on the input 15

c (pre-installation input of the counter 9 in FIG. 1 is not shown). The overflow output sets to zero the status of the trigger 7, which prohibits the generation of impulses of the generator 8, and the trigger 10 to one state. At the same time, the overflow output serves as the second control output of the device.

In block 5 of the semi-permanent memory, there is an additional information bit (second output of block 5), indicating the presence of a correction at each address. The ecsm information is updated, a single level on

five

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0

five

the second output of block 5, together with a single level at the output, trigger 10 generates a zero signal at the output of the NAND 11 element, allowing passage through the switch .6 from block 5. If the information in block 2 is correct, the second output of block 5 is the level logical zero, at the output of the element IS-NE .11 - the level of the logical unit passes through the switch 6 information from block 2. Signals from the control and information outputs are fed to the computing device for further processing.

After the program is executed, the calculator removes the signal. The readout and the memory operation with the program correction in the program automatic correction mode is stopped.

In the manual correction mode of the numbers recorded in block 5 of the semi-permanent memory or the initial input of corrected numbers, the write address is set on address register 21, and the information on register 3 of the initial state code. Signal Recording arriving on the second control bus 13 permits the passage of clock pulses through the second element 20 to the input of the second generator 23, at the third output 23 of which a control signal of the numeric register is generated, according to which information from register 3 of the initial state code is written to numeric register 4 Thereafter, at the output 23 of the second generator 23, a signal is generated to enable the transfer of the write address to allow the passage of the address code from the address register 21 through the second group of 25 elements AND to the second inputs to mmutatora 26 open on second inputs, and further the address inputs of units 2 and 5. At the output 24, driver 23 is formed a signal recording memory at kotoromu.proiskhodit information recording unit 5 in a semi-permanent memory. After the termination of this signal, the computing device (sig10 output

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Claims (1)

The invention is a memory device with a program correction, containing a block of permanent memory, the address inputs of which are connected to the address inputs of a block of semi-permanent memory and with the same outputs of a control unit, the output sample of a chip of which is connected to the same-name inputs of blocks of permanent and semi-permanent memory and is the identification identification output of the read cycle of the device, the inputs of the control unit are respectively the input of the synchronization mode selection and the address inputs of the device, the write outputs and page The controls of the control unit are connected respectively to the recording input of the semi-permanent memory unit and to the synchronous input of the numerical register, whose information inputs are the information inputs of the device, and the outputs are connected to the information inputs of the semi-internal memory, whose information outputs are connected to the second information inputs the switch groups, the information inputs of the first group of which are connected to the outputs of the permanent memory unit, and the outputs are the information outputs of the device, I distinguish This is because, in order to expand the application area by matching the sample time of the permanent and semi-permanent memory blocks, the device includes the first and second triggers, the pulse generator, the counter and the NAND element, and the synchronous inputs of the triggers are connected to the chip sample output The control inputs of the counter are of the same name as the inputs of the device, and the counter clock input is connected to the output of the pulse generator, the input of which is connected to the output of the first trigger, the R input of which is connected to the S input of the second trigger , And the overflow output of the counter is the output end of the apparatus cycle, the second flip-flop output being connected to a first input of AND-NO element, a second input coupled to the output of the correction feature a semi-permanent memory, and an output connected to a control input of the switch informatsion30 35 40 45 50 In FIG. 1 not shown) can form the first and second trigger inputs of the next signal Record of the charger, connected respectively to the inputs  logical unit and logical zero device. which is being recorded at a different address. . 0 five 0 The invention is a memory device with a program correction, containing a block of permanent memory, the address inputs of which are connected to the address inputs of a block of semi-permanent memory and with the same outputs of a control unit, the output sample of the crystal of which is connected to the same-name inputs of blocks of permanent and semi-permanent memory and is the identification identification output of the read cycle of the device, the inputs of the control unit are respectively the input of the synchronization mode selection and the address inputs of the device, the write outputs and The controls of the control unit are connected respectively to the recording input of the semi-permanent memory unit and to the synchronous input of the numerical register, the information inputs of which are the information inputs of the device, and the outputs are connected to the information inputs of the semi-5 memory, the information outputs of which are connected to the information inputs of the second the switch groups, the information inputs of the first group of which are connected to the outputs of the permanent memory unit, and the outputs are the information outputs of the device, I distinguish This is because, in order to expand the application area by matching the sample time of the permanent and semi-permanent memory blocks, the device includes the first and second triggers, the pulse generator, the counter and the NAND element, and the synchronous inputs of the triggers are connected to the chip sample output The control inputs of the counter are of the same name as the inputs of the device, and the counter clock input is connected to the output of the pulse generator, the input of which is connected to the output of the first trigger, the R input of which is connected to the S input of the second trigger , And the overflow output of the counter is the output end of the apparatus cycle, the second flip-flop output being connected to a first input of AND-NO element, a second input coupled to the output of the correction feature a semi-permanent memory, and an output connected to a control input of the switch informatsion0 five 0 five 0 The inputs of the first and second triggers are connected respectively to the inputs