SU1418720A1 - Device for checking programs - Google Patents

Abstract

The invention relates to computing technology and can be used for building control devices for microprocessor software programs. The aim of the invention is to improve the completeness of the control and reduce the time spent on control. The goal is achieved by tvn that the device contains a register of I commands, a decoder of 2 commands, an arithmetic logic unit 3, a block 4 of decimal correction, a distributor 5 of control signals, a register of attributes, a multiplexer 7, a block 8 re

Description

gistrov, stack pointer node 9, command counter 10, control register 11, register selection node 12. temporary storage register 13, buffer nanntb 14, buffer memory register 15, buffer register 16, address buffer register 17, block 18 decoding, clock generator 19,

random-access memory 20, permanent memory 21, display unit 22, information input unit 23, trigger 24, counter 25, AND-NE element 26, trigger 27, OR element 28, data reset button 29, switches 30-32, bus 33 addresses, bus 34 exchange, 35 data, 1 pc.

one

The invention relates to computing, and can be used to build program control devices and can be used as a training microcomputer.

The aim of the invention is to increase the completeness of control and reduce time spent on control.

The drawing shows a diagram of the proposed device.

The device contains a register of 1 commands, a decoder of 2 commands, an arithmetic logic unit 3, a block 4 for decimal correction, a distributor 5 of control signals, a register of 6 signs, a multiplexer 7, a block of 8 registers, a node 9 of the stack pointer, a counter of 10 commands controlling register 11, register selection node 12, temporary storage register 13, buffer memory 14, buffer memory register 15, buffer register 16, address buffer register 17, decryption unit 18, clock generator 19, random access memory 20, permanent memory 21, the display unit 22, the information input unit 23, trigger 24, counter 25, element AND-NOT 26, trigger 27, element OR 28, data reset button 29, switches 30-32, bus address 33, exchange bus 34, data bus 35.

The device works as follows.

When the power is turned on, the contents of the registers are block 8 and the counter. 10 is set arbitrarily by supplying a high level signal to the CBR reset input 5 by means of a button 29 to the counter.

10 is written zero. The operation is synchronized with generator 19. Commands are executed in several machine

cycles depending on the length of the command and the operations to be implemented. In the first cycle of the command execution, the contents of counter 10 are written to register 11 and then through register 17 are output to

bus 33; At the same time, a control word is output to bus 35 and signals are generated: synchronization C, PM - permission to receive information from the data bus, B P - sign of information output to the data bus. Under the action of the sync signal, the control word is recorded in block 18, the control word reflects the current state of the device, recording or

reading, entering or outputting, going on with the stack or processing; i. interruption, In accordance with this, the block of 18 states can generate signals at the corresponding outputs:

PTP - read memory, PZP - write V.pam, WBT - read I / O, VZP - write I / o. Ml - the beginning of the first cycle of the team. In this case, the state of Read from the memory is reflected, in accordance with

this control word produces a PTP signal,

Under the influence of this word, the first byte of the command, which is the operation code, is read from the zero cell 21 of the memory, goes to bus 35 and through register 16 is written to register 1, then the operation code goes to decoder 2, where it is decoded, and the decoded signal affects the driver 5, the latter produces;

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or external signals for reading the second and third bytes of the command and initiating I / O operations, or generates control signals propagating through the internal control bus. Control signals are generated in the driver in the shaper by 5 microcommands. Each team corresponds to a specific set of microinstructions. Arithmetic and logical commands are executed in block 3. The data is placed in register 13 and register 15. The result of the operation is recorded in memory 14 or fed to bus 34. Block 4 allows, if necessary, translation of the contents of memory 1 4 from a binary in binary-decimal form. Information about the result of the execution of the command is recorded in register 6. Bit Zero of register 6 is set to 1 with zero result, bit Transfer when the higher bit overflows, bit. Parity - with an even number of units per byte, bit Sign - with a single value older bit, bit Extra Carry - when going from 1 of the lower four bits to the older ones.

When executing the transfer and register loading commands, the shaper 5 decodes that part of the command in which the register address is defined and transmits the appropriate control signals to the node 12 and the multiplexer 7 via the internal control bus, and the required register of the block 8 is connected to the bus 34, through which transmission of information. If the registers are used for addressing the memory, the shaper 5 generates BT signals, according to which the information from the registers is sent to the register 11 and from there through the register 17 to the bus 33, while in control unit 18 the control word defining the memory operation mode is written. tew. The stack operation commands are executed in the same way. In this case, node 9 is used for addressing.

To process the user program in the continuous mode, it is necessary through block 23 to enter the command Start with the command indicated; the initial address of the program, switch 32 to switch to

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at the same time, Log.O dl is fed to the input of the trigger data 2 7. the formation at the output of rppjrrepa 27 of the signal is not ready, otherwise Log. 1 to form a ready signal. The step size is selected by the switch 30. At the same time, the input of the record of the trigger 27 is switched through the element IS-NOT 26

Q is either the Ml signal from block 18, which indicates that the first byte of the command is being sampled and this corresponds to the execution of the first (command) mode of operation, or the sync signal from the driver 5, which corresponds to the step-by-step execution of the program. Before transferring control of the analyzed program to trigger 24, a signal, 1 from zero bit O of bus 35, is recorded by the signal of the WWER signal, followed by a step from block 18 to the synchronous input of trigger 24, and the Log.O, the output of the counter 25, the most 25 (0,1,2) is reset to O and the logic. About the output of the counter 25 enters the element OR 28, allowing the passage of the clock signals from the driver 5. Thus, the counter 25

0 gains the ability to read command run cycles, which are determined by the clock signals coming from the imaging unit 5. After six work cycles, and the execution of commands necessary for switching to the program being processed in automatic mode, the output of counter 25 appears Log.1, which enters the input element OR 28, prohibiting further counting, since Log.1, rather than a sequence of pulses, will be permanently present at the output of this circuit. By the signal Ml in the pg command mode by the sync signal

in a step-by-step mode for executing a command received at the input of recording trigger 27, the trigger 27 records the value of the data input (in the VG - Log.O mode) of the trigger 27 and from the output of this trigger to the input of the imager 5 IT increases the signal Not Ready, which translates the & standby device (OA). Of

In this state, the op-amp exits on the positive edge of the short signal, coming from switch 31 to the trigger setup input 27. Thus, the trigger output is set

35

in 1, which corresponds to the signal Go (I

Comrade

Thus, a sequential command execution mode with indication of the address, data and control signals is provided by means of block 22,

Claims (1)

Invention Formula A device for monitoring programs containing random access memory connected by two-way information ({connected to the data bus of the device connected to the information input of the indication flock and information memories of the fixed memory and water information block, address inputs of the main memory, fixed memory ph, the display unit and the information input unit 1 are connected to the device address bus, a buffer register connected by two-way communication with the device data bus and through the device bus to information inputs-you moves of the buffer memory, regit C temp of the temporary storage and multiplexer, information outputs of the register of attributes and the arithmetic logic unit and information input of the command register, the output of which through the command decoder is connected to the information input of the control signal distributor, the first control output of which is connected with the control inputs of the time storage register, the buffer memory register and the buffer memory, the information code of which is connected to the first information through the buffer memory register The input of the arithmetic logic unit, the second information input of which is connected to the output of the temporary storage register, the input and output of features of the arithmetic logic unit is connected to the control output and the first control input of the sign register J and the correction input of the arithmetic logic unit are connected to information, respectively, the output and input of the unit of the decimal correction, the second control input of the register of attributes, the control inputs of the arithmetic logic unit and the block of the decimal correction and connected to the second control output of the control signal distributor, the third control output of which is connected with the control inputs of the buffer, register, command register, command decoder, control register, register selection node and multiplexer connected by a two-way information link with a register block connected by a two-way information link with the stack pointer node, the outputs of the register selection node spini-i with the control inputs of the register block, the stack pointer node and the command counter, the output of which through the control register is connected to the input of the address buffer register whose output is connected to the device address bus, the clock generator whose outputs are connected to the first and the second clock inputs of the distributor control signals, the output of the information sign and the output of the information reception permission of which are connected respectively to the first and second inputs of the decryption unit, whose information input is connected to the device data bus, the write control output to the memory of the decryption block is connected to the first control input of the operational memory output, the read control output from the memory of the decryption unit is connected to the second control input of the main memory and the control input of the fixed memory, the write control outputs and the read IO cm joined with the control inputs of the indicating unit respectively and a block of information input, a first flip-flop, an AND-NO element, characterized in that, in order to increase the completeness of the control and reduce the temporal costs of the control, a counter, a second trigger, three switches, an OR element are entered into it, and the output is controlled. The I / O record of the decryption unit is connected to the synchronous input of the first trigger, and the output to the installation of the counter input, the output of which is connected to the first input of the NAND element and the OR element, is connected to the first input of the first switch, control the deciphering input and the second input of the OR element, the output of which is connected to the counter input of the counter, the information input of the first trigger is connected to the device data bus, the output, control of the start of the command cycle 7 14187208 The dips of the decryption unit are connected to the I-input of the distributor readiness by the control input of the first switch, the output signals connected with the output of which the course is connected to the second input of the second trigger, the information house of the NAND element whose output of the input is connected to the output is connected to the synchronous input of the second trig-third switch, the first and the second, whose installation input is through which the inputs are connected to the bus; the second switch is connected to the buses of the unit and the numerical unit signal, respectively; device potential.