SU446060A1 - Computer control unit - Google Patents

Description

The invention relates to the field of computer technology and can be used in the construction of numerical combinations with the possibility of fault diagnosis.

Known microprogram control devices of computers, containing a long-term memory block with a sampling circuit, program register, tsuska-stop circuit, generator, command register, have a low resolution when performing automatic fault diagnosis. Hard restrictions on the order of generation of diagastic signals, imposed by the selected command system and the algorithm for performing each operation, troubleshoot the arithmetic unit,

Yaokalizatsiya high resolution malfunctions requires the supply of test signals to the input of the monitored device, determined by the device's location and the list of its geogravnosti, Diagnostics by software using, for example, the method of expanding areas 5 does not allow to establish a one-to-one correspondence with the error-suppo g PLEASE .DETT TO NWATCHABILITY®

reviewing an extremely large number of eleganes and a set of possible manifestations of each fault. In addition, in celestial devices and solutions, a way out of a situation in the event of a malfunction of Hex with a microcommand (exceeding the upper limit of time for performing operations) is performed by triggering a time control using time stamps. This leads to significant temporary

0 costs and does not provide high precision time control.

Additional equipment is inserted into the control unit, which contains a cycle counter, an actuator, and an operation mode trigger. NOT circuit and six circuits

match, with the zero output of the first overflow trigger of the clock counter connected to the first input of the first matching circuit, the third output of the long-term filling unit is connected to the second input of the first matching circuit, the second output of the long-term memory (Zlok is connected to the first input of the clock counter and the first input of the second circuit match, the single output of the second overflow trigger is connected to the first input of the third matching circuit, the output of the start-stop circuit is connected to the first input of the fourth with matching schemes with the first input of the fifth matching circuit, output of the sixth matching circuit is connected with the input of the NOT circuit and with the second input of the fifth matching circuit, output of the circuit is NOT connected to the second input of the fourth matching circuit, output of the fourth matching circuit is connected to the fourth input of a long-term the storage unit and with the counting input of the counter, the output of the second coincidence is connected with the quadrant input of the register of the program, with the second input of the counter and with the zero input of the mode trigger, the unit output of the mode trigger is connected to the first input the house of the sixth ox & tm coincidence, zero with the second input of the second matching circuit, the output of the second matching circuit is connected to the first input of the encoder, the second input of the encoder is connected to the first output of the command register, the output of the encoder is connected to the third input of the clock counter and the single trigger input mode, the third output of the register of commands is connected to the fourth input of the clock counter, the fourth output of the register of commands - with the fifth input of the program register.

This allows organizing free access to the control memory, i.e. perform any microinstruction or sequence of microinstructions; perform installation operations with a minimum amount of hardware; interrupt the work of any command on any measure of the time diagram; control the duration of operations at the lower and upper bounds, not excluding the time control of time stamps, allowing you to get out of the hang situations, and therefore increase the resolution of the ups to HenonyjeircTBeHHo

to work with faulty elements at the level of combinatorial logic; or at the time shtagram level, increase the time resolution, ensure that each sequential state of the computer is recorded at a tempo, increase the completeness of control and reduce the OTHER W wnwrnnnweu Tinaijoti

costs.

Fig. "I depicts a computer control device; in fig. 2 - format A of the unicast command system and format B of the diagnostic command, additionally entered into the existing system of commands; Fig. 3 is a diagram illustrating the operation of the temporal control over the lower and upper bounds.

The outputs I of the long-term charging unit 2 are connected to the counting inputs of the register of program 3. This link establishes the next control code. Outputs 4 are control signaling signals that enter an arithmetic unit, a memory device and an I / O device. Output 5 is the end of operation signal that is connected to the input of the first coincidence circuit 6, the first coincidence circuit generates a fault signal 7 in case when the operation ends prematurely (control at the lower boundary).

The outputs 8, associated with the input of the program register 3, with the input of the clock counter 9, with the input of the command counter 10, with the input of the command register II and with the input of the second coincidence circuit 12, control whether the control devices. The output of the coincidence circuit is 12 coupled to the encoder 13. The output of the clock frequency generator 14 is connected to the input of the start-up circuit 15. The start-stop circuit is controlled by signs 16 inputted to its input. The output of the start-stop circuit is connected to the inputs of the fourth 17 and fifth 18 matching circuits. The output of the fifth coincidence 18 is connected to the input of the register of the program 3, to the input of the clock counter b 1J G with the input of the mode 19 trigger, which is set to state 1 only when executing the diagnostic command with the format B.

Counter 9 contains the first overflow trigger 20 and the second overflow trigger 21. The single

the first flip-flop trigger 20 is connected to the input of the sixth matching circuit 22 and the third match input is 23, the second to the first coincidence circuit 6, the single output of the second overflow trigger 21 is connected to the matching input 23, which generates a fault signal 7 when exceeding the upper strash time of operations. The unit output of the trigger mode 19 is connected to the input of the sixth matching circuit 22, zero to the input of the second matching circuit 12V. The output of the sixth matching circuit 22 is connected to the input of the NOT 24 circuit to the input of the fifth matching circuit 18, The 24 HE circuit is connected match 17 "The output of the command counter 10 enters the same devices as the outputs 4 of the long-term memory unit 2.

The command register II is represented by the format B command. The operation code field 25 is connected to the input of the encoder 13 and to the proztramiy 3 register. The field of the clock counter 26 is connected to the input of the clock counter 1 clock 9, After the register of program 27 is connected to the input of the register program 3, Link 28, corresponding to the field address of the command with the format A It enters the same device as outputs 4 of block 2.

The device works as follows.

A special diagnostic command is added to the command system with the format B shown in FIG. 2

After reading the diagnostic command in the command register II, the operation code is set in the register of program 3 and, at the same time, the operation is transmitted through the encoder 13 and set in the clock counter. Transmission through cipherOiJ is possible, since the trigger of the computer 19 is in the state 0. After decoding the operation code of the diagnostic command, the encoder sets the clock counter 9 to state O and mode 19 trigger to state I.

According to the code set in the program register 3, a micro-command is read from the long-term memory block, which censors the contents of channel 26 and 27 of the command register to the clock counter and registers the program code coofMJTOfBeHHo, the field contains the initial address of some sequential code. (or microman} you) Field 26 contains the number (h) of clock .. which is according to. B1crowded1PlZ "Code 9 - / g is transmitted to counter 9

. (in addition to the 2 numbers

n}, where 77g is the weight of the first trigger trigger 11 20,

Yes, according to the arrival of pulses from the fourth coincidence circuit 17, the microcommands are sequentially executed and, simultaneous counting of read cycles by the counter 9a. The last clock sets the first overflow trigger 20 to the state. A high potential appears at the output of the sixth coincidence circuit 22, arrives at the input of the Yui coincidence circuit 18 and the input of the circuit is NOT 24, With the arrival of the next. the clock pulse from the circuit 15 the signal appears on the side of the EYTHY

6 of the coincidence circuit 18 "By this signal the mode trigger 19g is set to the state O - counter 9 and the code that is sent to the program register 3 is the code that corresponds to the final phase address of the microproper-rpar / iM / switch. It is an I P counting: well, the commands and the sampling of the background command is carried out.

If in the field 27 of the diagnostics cohort immediately indicate the final phase of execution of the microprogram 5 and in the field 26 the number of clock cycles is divided, the following command about format A, 1 will be executed

; i cycles spent on the completion of the ael phase of execution of the diastozhzhsky kosh. ntsy.

An extended control device detects in two modes: state 1 of the trigger trigger 19 and state O, described in (state I of the trigger a), in which additional equipment is used specifically and diagnostic circuits. When performing the usual computational irporpaiviMH 7.rig "the ger is in the state and the additional arrnapai ypa is used for temporary circuits

KOHfpOJffis

in the device of the request, malfunctions are possible, in which the operation ends with the time required for its time, Other timeframes lead to some time saiuiKjn Kfflire J; Go around for commandos. The end of the execution of schande phytochuvts with the generation of the signal of the horse of the operatives / 5e In Fig. 3, the time control is shown: The area located above the time axis corresponds to the time at the end of the command and lower to the right ((/ /) the output time of the command end | 1 Akitsa time & execution of the co-ordination} MohieHT finished nav ™; 1) Batsa with zetchi Js-Eurv 9 through & 1 Ibrah1Op is a definite code, corresponding to the following 11M A-iUr -: a4bhOwj and effects from the command. The Shrrrator 13 converts the Kot operadni into a number code. With a vipnenush op-ziiii account ™ chek 9 Eede-E account takGoVb If oigsyiji oiKpaiivf ;; .5 is generated before / CHUM set with the first i I first rigger renojiiiBHHH 204 scheme sovyy11 BKpadaTLiEaef HSHC equalize 7l Ush, and go to the right EE. perish 4rigt; :) and izrepolhftJiMK 20 and the state of ayosgo The MSW control module containing a long time memory register is a program register, start-octanova, generator, register, command, and command counter, and the output of the long-term memory block is connected to the first input of the program register, the second output of the long-term lock block connected to wto a log, / by the register of the programmer, with the first count input of the commands and with the first input of the command register, the output of the register g is connected with the first input of the long-term memory block. pulse generator output - with the start-stop circuit input, the first output of the command register is connected to the third input of the program register, the second output of the command register with the second input of the command counter is different in that it is used to increase the resolution of diagnostic programs and the speed of the device into it in addition, a clock counter, an encoder, a trigger with a5 a5 circuit and six coincidence diagrams are entered, and the zero output of the first cycle counter overflow trigger is connected to the first input of the first matching circuit and, the third output of the long-term filling unit is connected to the second input of the first matching circuit, the second output of the long-term storage unit is connected to the first input of the clock counter and to the first input of the second matching circuit, the single output of the second cycle overflow trigger is connected to the first input of the third circuit match, the start-stop pattern is connected by the first input of the fourth matching circuit and to the first, the input of the fifth matching pattern, the output of the sixth matching circuit is connected to the input of the skewer and the co-workers the input 1 of that coincidence circuit, the output of the circuit NOT connected to the second circuit of the fourth matching circuit, the output of the fourth coincidence circuit of the fourth input of the long-term memory block and the G46Tium input clock counter, the output of the fifth coincidence circuit is connected to the fourth input of the register / gy with BTopjM clock counter input and with zero trigger input;}, the another grgGer mode output is connected to the first input of the sixth schematic match; the zero output of the trigger is connected to the second input of the second circuit; a swarm of the coincidence circuit is connected with the first input of the encoder, the second input гг1 ||) rato15a is connected with the first output; the command register house; input clock counter, the fourth output of the command register is connected to the fifth input of the register prokhammYV

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Format A

Right

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2

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