SU830386A1 - Microprogramme-control device - Google Patents

Description

 (54) FIRMWARE CONTROL DEVICE

one

The invention relates to computer technology and can be used as a control device for a firmware computer.

A firmware control device is known, which contains two storage blocks, a register of logic conditions, counters, decryptors, registers, AND logic gates, delay elements, and a clock generator 1.

A disadvantage of this device is its low efficiency, which is caused by the large amount of memory of the memory blocks caused by the storage of a large number of repetitive operating micro-instructions.

The closest to the proposed technical essence and the achieved positive effect is a device containing a register of logical conditions, a group of elements And, a buffer register, an address register, the first decipher and the first storage unit, chitra, a clock generator, a counter of micro-instructions 2.

The disadvantage of this device is low efficiency, which is due to the large amount of storage blocks.

The purpose of the invention is to increase the efficiency of the device.

This goal is achieved by the fact that the firmware control device containing a register of logical conditions, the output of which is connected to the first input of the first block of elements AND, the second input of which is an input of logical devices, the output of the first block of elements of AND connects to the first information input of the buffer register information input and output of which are connected respectively to the output of the next sequence number of the first memory block and to the first input of the second block of elements AND, the second input and output d which are connected respectively to the output of the first element I and to the information input of the address register, the reset inputs and the operation code of which are connected respectively to the reset output of the first memory block and the input of the operation code of the device, the output of the address register connected to the information input of the first decipher, the start input which is connected to the OUTPUT of the second element I and to the inputs for setting the address counter to zero, the register of logical conditions and the buffer register, the output of the first decoder is connected to the input of the first block the memory, the outputs of the current sequence number and logical conditions of which are connected respectively to the input of the encoder and the information input of the register of logical conditions, the first and second outputs of the encoder are connected respectively to the information inputs of the microinstruction counters and the address, the output group of the microinstruction counter, and the output of which is connected to the first inputs of the first and second elements AND, and through the first element NOT to the first input of the fourth element AND, the second input of which connected to the output of the clock pulse generator and through the first and second delay elements connected to the second input of the first element I, the counting input of the micro-command counter via the second element is NOT connected to the counting input of the address counter and the first output of the second memory block whose second output and input are connected respectively, with the outputs of the device and the second decoder, the first input of which is connected to the output of the first delay element and the second input of the second element And, contains the third decoder, the third memory block, register addresses of operating microinstructions, two triggers, modulo two, fifth and sixth And elements, the third delay element, the first input of the third decoder is connected to the output of the address counter, and the output of the third decoder to the input of the third memory block, the output of which is connected to the first information input of the register of the address of operating microinstructions, the second information input of which is connected to the second input of the third decoder and the output of the fourth element I, the first bit output of the register of the address of the operating microcodes mand is connected to the second input of the second decoder, the first input of which is connected to the zero input of the first trigger, the second bit output register of the address of operating microcommands is connected to the first input of the modulo two, the second input of which is connected to the single output of the first trigger, the single input of which is connected to the output of the fifth element And, the first input of which is connected to the first output of the second memory block, and the second input - to the output of the second delay element and through the third delay element to the first input of the sixth element And, the second input of which is connected to the output of the modulo two adder, and the output of the sixth element And is connected to the single input of the second flip-flop, the single output of which is connected to the control input of the clock generator.

The essence of the invention is to improve the efficiency of the device by writing once the operating microcommands in the second memory block and organizing the control of the correctness of their reading.

The third block of memory contains addresses of microinstructions executed in various linear sequences. The number of these addresses is equal to the number of microinstructions in the firmware. The address of the next executed microcommand is stored in the address register of operating microcommands, where it is read from the third memory block. The second block of memory stores operational microcommands that are different from each other. The read order of the operating microcommands in accordance with the sequence code read from the first memory block is determined by the sequence of addresses read from the third memory block. In the operating microcomads, which are the last in the linear sequences, as well as in the corresponding addresses, one is written in the extra bit (the identifier field), in the remaining ones - zero. The essence of the control principle consists in comparing the signs of operational microinstructions and their addresses. The introduction of the first trigger and the connection of its single input with the output of the fifth element And allows you to remember the sign of the next microcommand read from the second block of memory and the linear sequence performed and allows you to block the operation of the device. The introduction of a modulo-two adder is necessary for analyzing signals from the second outputs of the address register of operating microcommands and the second memory block and generating a failure signal.

A failure signal is generated if an operational microcommand is read from the second memory block, which is the last in a linear sequence prior to reading the corresponding address from the third memory block, or if, after reading from the third memory block, the address of the last microcommand in the sequence is not read from the second memory block.

The drawing shows the functional diagram of the firmware control device.

The device contains the address register 1, the first descrambler 2, the first memory block 3, the logic condition register 4, the first block 5 AND elements, the buffer register 6, the second AND block 7, the encoder 8, the microinstruction counter 9, the third And 5 element 10, the first element 11 and 11, the second delay element 12, the first delay element 13, the second element 14 and 14, the address counter 15, the third decoder 16, the third memory block 17.

register 18 addresses of operating microinstructions, the second decoder 19, the second memory block 20, the second element is NOT 21, the fifth element is And 22, the first element is NOT 23, the fourth element is And 24, the first trigger 25, the generator 26 clock pulses, the adder 27 modulo two, the sixth element And 28, the second trigger 29, the third delay element 30, input 31 of the operation code of the device, first-quarter outputs 32-35 of the first memory block, respectively input 36 of the logical conditions of the device, second output 37 of the second memory block.

In the first block of memory 3, the address part of the microcommand is recorded, which is read as follows: from output 32, the number of the following sequence, from output 33, to the number of the current mediocrity, from output 34, the code of the logical conditions to be checked, from output 35, to the register reset signal one.

The device works as follows.

In the initial state, all the memory elements are in the zero state. The code (number) of the operation enters through input 31 into register 1 and sets the address of the corresponding cell in the first memory block 3. The generator 2 clock pulses through the first delay element 13 in the presence of an enable signal from the output of the element And 10, corresponding to the zero state of the microcomputer counter 9, sets the counter 15 to the address 15, the logical conditions register 4 and the buffer register 6, and the first decoder starts 2. The signal from the decoder 2 from the corresponding memory cell of the memory block 3 is counted: the code of the number of the subsequent linear sequence being executed, which from output 32 goes to the first input of the buffer register 6, the number of the current executed sequence, which is fed from output 33 to the input of the stripper 8, the code of checked logical conditions, which goes to the input of the register 4 of logical conditions from output 34, the signal from output 35 sets the register to zero. the output of the oscillator 26 clock pulses through the second element 12 of the delay and through the first element I 11, if there is a permitting signal at its first input corresponding to the zero state of the counter 9 micro-instructions, enters the input of the second block 7 elements I and produces The code of the number of the subsequent linear sequence from the output of the buffer register 6 to the register 1. After reading the address part of the microcommand and writing to the counter 9 microcommands the code of the number of microcommands the readings of the counter are different from zero. The signal at the output of the element And 10 takes a zero value and through the first element NOT 23 opens the element And 24.

The second clock pulse from the output of the clock pulse generator 26 triggers the third decoder 16 and confirms the zero state of the register 18 of the address of the operating micro-commands. After reading the address of the operating, microcommand from the third memory block 17, it arrives at the register 18 of the address of the operating microcommands and at its second input there appears a single signal that arrives at the first input of modulo 27 modulo two, to the second input of which a zero signal arrives a single output of the first trigger 25. The signal from the output of the first delay element 13 starts the second decoder 19 and confirms the zero state of the first trigger 25. From the second memory block 20, the operating microcommand begins reading after which, at its first output, a single signal appears, which is fed to the first input of the fifth element I 22 and to the second input counter of address 15, changing the address of the next microcommand. The signal from the output of the second delay element 12 is fed to the input of AND 22, and a single signal appears at the output of this element, which sets the first trigger 25 to one, with the result that a single signal is fed to the second input of modulo two . The same signal (from the output of the second delay element 12) interrogates the sixth And 28 element via the third delay element 30. As a result of reading the operation microcommand from the second memory block 20, a zero signal appears at the output of modulator 27 modulo two, and a failure signal in this case is not generated.

The next clock pulse output from the generator is 26 clocks x. the pulses start the third decoder 16 and reset the register 18 of the address of the operating microinstructions, with the result that a zero signal appears at its second output. This same clock pulse through the first delay element 13 triggers the second decoder 19 and sets the first trigger 25 to zero.

After that, the operation of the circuit occurs as described above. If the address of the microcommand that is the last in the sequence being executed is read from the third memory block 17, then the second output of the register 18 for the address of the operating microcommands is a zero signal. This signal is fed to the first input of the adder 27 modulo two, the second input of which receives a zero signal from the single output of the first trigger 25.

Claims (1)

After reading the operating microcommands from the second memory block 20, a zero signal appears at its second output, which arrives at the first input of the fifth element AND 22 through the second element HE 21 and reduces the content of the microcomputer counter 9 by one unit. The output signal of the generator 26 clock pulses through the first delay element 13 and the second delay element 12 is fed to the input of the fifth element And 22 and to the input of the third delay element 30. At the same time, the installation of the first trigger 25 into the unit state does not occur, and a zero signal arrives at the second input of the adder 27 modulo two. As a result, further operation of the device is permitted. After reading from the second memory block 20, the last section of the linear sequence of the microcommand counter 9 is zeroed out and a single signal appears at the output of the AND 10 element. The clock pulse passing through delay elements 13 and 12, element 11 and the address of the next address command is transferred from buffer register 6 to address register 1 via block 7 elements I. The next pulse from the clock generator 26 is through delay element 13 and element 14 resetting the address counter 15, registers 4 and 6. In addition, according to this pulse, depending on the contents of register 1 of address, decoder 2 reads the next address microcommand of memory block 3 and the device continues as before described e. During the operation of the proposed firmware control unit, failures in its operation are manifested in the reading of an extra operating microcommand from the second memory block 20, in that not all the operational microcommands are read from the second memory block 20. The device allows these failures to be recorded in the following manner. Suppose that in the register 18 of the address of the operating microinstructions is the address of the last microcommand in the executed sequence. In this case, a zero signal appears at its second output, which is fed to the first input of modulator 27 modulo two. If, after reading the operating microcommand from the second memory block 20, it turns out that the read operating microcommand is not the last one, then a second signal appears on the second output of the second memory block 20, which is fed to the first input of the p TOR element I 22. The signal c the output of the generator 26 clock pulses through the first and second delay elements 13 and 12, respectively, is fed to the second input of the fifth element And 22 and to the input of the third delay element 30. In this case, the first trigger 25 is set to the single state, and a single signal arrives at the second input of the adder 27 modulo two 27. A single signal from its output is fed to the second input of the sixth element And 28, the first input of which receives a signal from the output of the third delay element 30. As a result, a failure signal is generated, the second trigger 29 is set to one state and blocks the operation of the generator 16 clock pulses. If the register 18 of the address of operating microcommands contains the address of the next, not the last in the sequence, operational microcommand, then at its second output there appears a single signal that goes to the first input of the adder 27 modulo two. If after this, the operational microcommand that is the last in the sequence being executed is read from the second memory block 20, then the clock pulse from the generator output of 16 clock pulses through the first and second delay elements 13 and 12, respectively, is set to one of the first trigger 25 , and to the second input of the adder 27 modulo two receives a zero signal. As a result, single inputs from the output of the adder 27 modulo two and from the output of the third delay element 30 are generated to both inputs of the sixth element 28, and a failure signal is generated, according to which the trigger 29 blocks the operation of the device. Thus, the proposed device allows to significantly increase the efficiency of the device and to organize the control of its functioning. This makes it possible to build firmware control devices with increased functional reliability. A firmware control device containing a register of logical conditions, the output of which is connected to the first input of the first block of elements AND, the second input of which is the input of the logical conditions of the device, the output of the first block of elements of AND connected to the first information input of the buffer register, the second information input and output which are connected respectively with the output - the number of the next sequence of the first memory block and the first input of the second unit of the AND blocks, the second input and the output of which It is connected respectively to the output of the first element I and to the information input of the address register, the reset inputs and operation code of which are connected respectively to the reset output of the first memory block and the input of the operation code of the device, the output of the address register is connected to the information input of the first decoder, the start input which is connected to the output of the second element I and to the inputs for setting the address counter to zero, the register of logical conditions and the buffer register, the output of the first