SU1176346A1 - Device for determining intersection of sets - Google Patents

Abstract

A DEVICE FOR DETERMINING A SET OF CROSSING THE SETS containing two registers, groups of elements AND, a group of elements OR, a decoder and a memory block, the first information output of which is connected to the input of the decoder, characterized in that, in order to detect the device performance by processing two sets of elements, Two counters, an OR element, a trigger, a comparison node and a firmware control block are entered into it, the first address input of the device is connected to the information input of the first counter, the bit outputs are which are connected to information inputs of elements AND of the first group, the outputs of which are connected to the first inputs of elements OR groups, outputs of which are connected to the address input of the memory block, the second information output of which is connected to the first information input of the comparison node and to the information inputs of elements AND of the second group, the outputs of which are connected to the information input of the first register, the outputs of the bits of which are connected to the second information input of the comparison node and to the information inputs of the AND elements the third group, the outputs of which are connected to the information output of the device, the second address input of the device is connected to the information input of the second register, the outputs of the bits of which are connected to the information inputs of the elements of the fourth group, the outputs of which are connected to the information input of the second counter, the outputs of the bits of which are connected to information inputs of the elements And the fifth group, the outputs of which are connected to the second inputs of the elements. OR group, the output of the comparison node is connected to a single trigger input J. A single (0 output of which is connected to the first C control inputs of the AND elements of the third group, the first output of the microprogram control unit is connected to the control inputs of the AND elements of the first group, the second output is connected to the counting input the first counter and with the control inputs of the elements And the second group, the third, Od 4 One, the fourth, fifth and sixth outputs of the microprogram control unit are connected respectively to the control inputs of the elements And h the fourth group, the fifth group, the comparison node and the second control inputs of the AND elements of the third group, the seventh output is connected to the counting input of the second counter and the first input of the OR element, the output of which is connected to the zero input of the trigger, the zero output of which is connected to the first the input of the firmware control unit, the eighth output of which is soy

Description

dinene with a signaling output of the device and with the /. second input of the OR element, the output of the denyufrator is connected to the second input of the microprogram unit many controls, the third input of which is 1176346

pogo connected to the installation input of the device and the third input of the element Sh1I ,. the device start input is connected to the fourth input of the firmware control unit.

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The invention relates to computing and can be used in data bank management systems.

The purpose of the invention is to increase the performance of the device by processing two sets of elements.

FIG. 1 shows a diagram of the device; in fig. 2 is a block diagram of the firmware control of FIG. 3 diagram of the firmware of the device.

The circuit contains registers 1 and 2, groups of 3-7 elements AND, a group of elements OR, decoder 9, memory block 10, counters 11 and 12, elements OR 13, trigger 14, comparison node 15, block 16 Microprogrammed control, address inputs 17 and 18 devices, device installation input 19, device start input 20, device information output 21, signaling device output 22, outputs 23-29 of block 16 and inputs 30 and 31 of block 16, memory node 32, counter 33, groups 34 and 35 elements And, the decoder 36, the generator 37 pulses, -distributor 38 pulses, the elements 39 and 40 of the delay register 41 elements OR 42, 43; trigger 44 and elements 45-58.

In each block of the microprobe circuit. grams of operation of the device (Fig. 3) depict executable microoperations. The elements of the device are indicated by their positions in FIG. 1 and 2. To the right of the bar in the rectangular block is the output of block 16, under the action of a pulse on which the corresponding microoperation is performed. The positions enclosed in brackets define the outputs (contents 181

corresponding elements of the device. The arrow indicates the forwarding of information, and the question mark indicates the proprietary condition.

5 Let A and B be sets of elements. Then the intersection of two sets is the set C of elements belonging to both set A and set B. Each set is stored.

The threads are in memory block 10, with the elements of the set represented by number codes and located in consecutive cells. The last element of the set is noted in block 10

5 specific Contents of additional bits, the outputs of which are connected to the inputs of the decoder 9. If a group of additional bits is used only for this purpose,

0 then it can be replaced with one bit, and the decoder 9 can be excluded from the device circuit.

The device works as follows.

When the power is turned on, the device is reset to the initial state of the pulses from the input 19, through which the triggers 14 (via the element OR 13) and 44 (through the element OR 42) are zeroed; the distributor 38 is reset (the signal does not appear on any of its turns), and the generator 37 is in a locked state. In counter 11 at the entrance

17 records the address of the first element of set A, and register 1 at input 18, the address of the first element of set B. The device is ready for operation.

The device is put into operation by a pulse from the input 20. According to this pulse, the counter 33 forms the address of the first microcommand of the device firmware. 3 memory recorded in node 32. In this case, the first micr command is selected from it to the inputs of the decoder 36, and the address code of the next microcommand. This same pulse with the delay required for sampling the first microcommand is fed to the start input of the generator 37, which begins to produce clock pulses. They are distributed by the distributor 38 over the control points of block 16. The first pulse appears at the first output of the distributor S8 and passes through AND 45 (the micro-operation code of the first micro-command should lead to a signal at the first output of the decoder 36). With this, the contents of counter 11 are fed into a group of 3 elements AND and 8 elements OR to memory block 10, from which the first element of set A. is selected. In addition, the address of the next mic command is received in register 41. The second pulse from the output of distributor 38 opens groups 35 the element AND and the address of the following microcommand is taken into the counter 33. In the future, the sample of microcommands from the memory node 32 and their decoding is performed similarly. The code of the second micro-operation leads to the appearance of a pulse at the input 24 of the block 16, as a result of which the contents of the counter 11 are incremented (the address of the next element of the set A is formed), and the first element of the set A of the memory block 10 is received from the register 2 (because A group of 4 elements opens. In addition, the same pulse is applied to element 55. The decoder 9 is tuned to the contents of the additional bits of memory block 10, corresponding to the last element of the set. Consequently, if from the block 10 in the previous cycle the last element of set A is selected, a pulse appears at the output of the element 55, which sets the trigger 44 to the one state. When the next microcommand is executed, a pulse appears at output 25 of block 16 and the contents of register 1 are copied to counter 12. Next, a pulse appears at output 26 of block 16, which opens a group of 7 elements AND, and the contents of counter 12 is fed to memory block 10 ti. In this case, 464 of the first element of the multiple B is selected from it. By the pulse at the exit of block 27, the content at output 15 of memory 10 is compared with the contents of register 2. When these codes coincide, an output at comparison output 15 and a trigger appear 14 is set to one state by preparing to open a group of 5 elements I. The impulse from the output of block 28 is the output of the first element of set C from register 2 to 21 if the trigger 14 is in one state. If it is in the zero state, then no issue is made. When the next microinstruction is executed, a pulse appears at the output of element AND 52. Here the firmware is ramified depending on the state of trigger 14. If trigger 14 is in the zero state, an pulse appears at the output of element 57, which passes through element IL 43 and with the delay required to receive the following address in counter 33. micro-instructions, is applied to the counting input of counter 33, increasing its content by one. In this case, a microinstruction is selected from block 32, as a result of which a pulse appears at output 29 of block 16, as a result of which the contents of counter 1-2 increase by one (the address of the next element of set B is formed), and the trigger 14 is set to zero. Then a pulse appears at the output of the element 53 and a potential analysis is performed at the output of the decoder 9. If it is zero, then the element 58 does not open and the next unconditional transfer micro-command is selected. The code of this microcommand is not decoded by the decoder 36, but as a result of its execution, the address of the fourth microcommand of the microprogram is written to the counter 33. If the output of the decoder 9 is a signal, then. a pulse appears at the output of the element 58 and in the counter 33 a microcommand address is formed, as a result of which a pulse appears at the output of the element 54. If trigger 14 is in a single state, the contents of C4eiv

The sa 33 does not change, as a result of which, from the node 32, the microcommand of the unconditional transition to the microcommand is selected, along which a pulse is output at the output of the And 54 element.

A pulse from the output of the element 54 is analyzed on the state of the trigger 44. If it is in the zero state, then the microcommand of unconditional transition to the first microcommand of the microprogram is selected. If the trigger 44 is in a single state, then a pulse appears at the output of 22 devices: signals, indicating that the device has finished working. By this: the pulse is brought to the initial state.

After writing to the counter 11 and register 1 of the addresses of the first elements of the two other sets and applying a pulse to the output 20, the device starts up again.

J9 20

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23 24 25 26 27 28 29

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(1) J2 2S

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Claims (1)

A device for determining intersection of sets, containing two registers, a group of AND elements, a group of OR elements, a decoder and a memory unit, the first information output of which is connected to the decoder input, characterized in that, in order to increase the productivity of the device by processing two sets of elements, two counters, an OR element, a trigger, a comparison unit, and a firmware control unit are introduced, the first address input of the device being connected to the information input of the first counter, the discharge outputs of which connected to the information inputs of the elements of the first group, the outputs of which are connected to the first inputs of the elements of the OR group, the outputs of which are connected to the address input of the memory unit, the second information output of which is connected to the first information input of the comparison node and the information inputs of the elements of the second group, the outputs of which connected to the information input of the first register, the outputs of the bits of which are connected to the second information input of the comparison node and to the information inputs of the elements of the third group, in the outputs of which are connected to the information output of the device, the second address input of the device is connected to the information input of the second register, the outputs of the bits of which are connected to the information inputs of the elements of the fourth group, the outputs of which are connected to the information input of the second counter, the outputs of the bits of which are connected to the information inputs of the elements And fifth groups, the outputs of which are connected to the second inputs of the elements. OR groups, q the output of the comparison node is connected to a single input of the trigger, whose unit output is connected to the first control inputs of the AND elements of the third group, the first output of the microprogram control unit is connected to the control inputs of the elements of the first group, the second output is connected to the counting input of the first counter and to the control inputs of the elements of the second group, the third, fourth, fifth and sixth outputs the microprogram control unit are connected respectively to the control inputs of the AND elements of the fourth group, the fifth group, the comparison unit and the second control inputs of the AND elements of the third group, the seventh the output is connected to the counting input of the second counter and to the first input of the OR element, the output of which is connected to the zero input of the trigger, the zero output of which is connected to the first input of the microprogram control unit, the eighth output of which is> Ц „., 1176346 is connected to the signaling output of the device and with / by the second input of the OR element, the decoder output is connected to the second input of the microprogram control unit, the third input of which is connected to the installation input of the device and to the third input of the OR element. the device startup input is connected to the fourth input of the firmware control unit.