SU1552190A2 - Device for check-out of program - Google Patents

Abstract

The invention relates to digital computing, can be used when debugging programs of specialized digital computers that contain regular blocks of permanent memory with work programs, and is an improvement of the invention in a.s. N 1198525. The device solves the problem of the operational substitution of information zones located in a block of permanent memory with information located in a block of random access memory. The goal is enhanced functionality. The device contains the first to third blocks of RAM, the block of permanent memory, the first to third blocks of comparison, the first to fifth delay elements, the first to eleventh AND elements, the trigger, the P trigger, the first and second OR elements, the first and second decoders, the first and second registers. 1 il.

Description

The invention relates to digital computing, can be used for debugging programs of specialized digital computers that contain regular blocks of permanent memory with work programs, and is an improvement to the device by author. No. 1198525.

The purpose of the invention is to expand the functionality by providing operative replacement of several zones of information of a permanent memory with corresponding zones of information of a random access memory.

The drawing shows a diagram of the device.

The device contains blocks 1 and 2 of the RAM, blocks 3-5 of the comparison, delay elements 6-10, elements 11-21, trigger 22 and 23, elements OR 24 and 25, block 26 of the permanent memory, block 27 of the RAM TI, counters 28 and 29, decoder 30, registers 31 and 32, decoder 33, device access input 34, device address input 35, device information input 36, device clock input 37, device initial setup input 38, device mode setting input 39, output 40 of the device.

The device works as follows.

In the initial state, in which the device is installed when Reset 38 is fed to the initial setup signal, information is read only from the Permanent Memory Unit 26 through the AND 20 at the time of the occurrence of clock pulspun.

one

with

14)

owls arriving at the input of 37 clock pulses. Therefore, information is output to the output 40 of the device, which is located in the permanent memory unit 26. At the time of the signal occurrence. Appeal at the device access 34 is sampling from the operational memory block 1 a number corresponding to the k least significant addresses sent to the address input 35 of the device. Signal Addressing through time, equal to the time of sampling information from the RAM unit 1, 1 which is provided by the delay element 6, is fed to the clock input of the comparison unit 3.

 In the case of reading a zero number from the RAM 1, which is interpreted as no need to replace information zones of the fixed memory block 26 for all addresses with the specified value of k least significant bits, the comparison block 3 is triggered and prohibits installation in ° 1 of the trigger 22. Thus, information is still being read from the permanent memory unit 26 to the device output 40.

In the case of reading a number, other than zero, from block 1 operational

the address of the sub-list of the addresses of the substitution points and the corresponding transition commands located in the RAM block 2, the comparison block 3 allows the signal to pass through the AND 11 element Reversal delayed by the response time of the match block 3. The 11th signal from the Yyhod of the 11th signal Reversal enables the recording of the number read from the RAM 1 unit to the counter 28 and sets the state 1 to the trigger 22. The latter switches the device’s clock to pass so that the arrival of each clock pulse is carried out from block 2 of RAM, after reading the information from block 2 of RAM, which is provided by delay elements 8 and 9, respectively, incrementing the contents of counter 28 and timing of block 4 of comparison.

In the case of reading from the first

the progress of block 2 of the RAM of the zero transition command, which is interpreted as THPVPTCH as the end of the sublist of addresses

0

five

0

five

0

five

0

0

five

of substitution points and the corresponding transition commands, the comparison block 4 is triggered and the clocking of the comparison block 5 is disabled, and also through the OR element 24 sets the trigger 22 to the state O. Thus, the information is still read from output 40 of the device. In the case of a jump command other than zero, from the first output of memory 2, the number read from the second output of memory 2 is interpreted as the full address of the replacement information from the persistent memory 26. In this case, the comparison unit 4 resolves the clocking of the comparison unit 5.

When the full address supplied to the input 35 of the device address with the number read from the second output of the RAM block 2 coincides, the comparison block 5 generates a signal at the output that sets the trigger 1 through element 16. Therefore, it is forbidden to read information from block 2e the constant memory, the passage of the signal from the output of the block 5 comparing the CEREZ element AND 16, the operation of the reader 29 is permitted and the trigger 22 is set in O, which prohibits the passage of clock pulses from the input 37 of the device’s pulses to the output element And 12 and allows the passage of clock pulses at the output of the element And 13 When the clock pulse first arrives at the input of 37, after the comparison block 5 has triggered, the pulse of the command for transmitting the control signal And 17 from the first output of the black memory 2 to the output is allowed 40 of the device and the state of the address input 35 of the device in the register 31 is stored. Therefore, instead of the next program command located in the permanent memory block 26, the control transfer command is issued to the device output 40 31 is stored in the register address of the point of substitution.

Upon the command to transfer control, the contents of the program counter are loaded onto the stack in the next cycle. In this cycle, the second after the detection of the replacement point, the control transmission code is not allowed to pass through eleven.

A mentor 1 / at the output 40 of the device and the state of the input 35 of the address in the register 32, i.e. the value of the stack pointer of the program located in the block 26 of the permanent memory. In the third clock cycle after detection of the replacement point, control is transferred to the address that is uniquely determined

command transfer control code,

the clock pulses to the counting input of the counter 29 through the element 15 are prohibited, the operation of the decoder 33 is permitted, and the reading of the information from the operating unit 27 to the device output 40 through the element 21 is permitted.

Claims (1)

Invention Formula Device for debugging programs auth.St. No. 1198525, characterized in that, in order to expand the functional capabilities of the device by ensuring the operative replacement of several information zones of the permanent memory with the corresponding information zones of the operational memory, two blocks of RAM are inserted into it, the second trigger, the second counter, And from the eighth to the eleventh, second and third units of comparison, five delay elements, the second element OR, and the address input of the second operational unit memory connected to address input 15 the device, the information input and the access address of the second RAM block are connected respectively to the information input and the input ob-. device, the settings of the mode 40 of the second and third blocks of RAM are connected to the input of the device mode, the output of the second block of RAM is connected to the first information input of the second 45 comparison block, the second information input of which is connected to the zero potential bus of the device A device input input through the first delay element is connected to the input resolution house of the second comparator unit and through the second delay element. 0 0 5 th 15 0 5 n 1906 the first input of the eighth element And, the second input of which is connected to the output of the second comparison unit, the output of the eighth element And is connected to the counter enable input and the single input of the second trigger, the direct output of which is connected to the first input of the ninth And element, the second input of which is connected to the clock input of the device, the output of the ninth element. And is connected to the access input of the third RAM block, through the third delay element - to the counting input of the counter and through the fourth delay element - to the input of the third rd comparator block, a first / and the second information inputs of which are connected respectively to the alarm output of the third bhp of the RAM and the device zero potential bus, the output of the third comparison unit is connected to the first input of the second OR element, the second and third inputs of which are connected respectively to the input of the initial installation of the device and the inverse output of the first trigger, the output of the second element OR is connected to the zero input of the second trigger, the inverse output of which is connected to the first input of the tenth element And, the second input of which is connected to the clock input of the device, the output of the tenth element And is connected to the first input of the first element K, the output of the ninth delay element is connected to the first input of the eleventh element And the second input and output of which are connected respectively to the output of the third comparison unit the resolution input of the first comparison unit, the output of the second memory block is connected to the information input of the counter, the output of which is connected to the address input of the third memory block, information in the stroke and the second output of which are connected respectively to the information input of the device and the clock input of the first comparison unit.